Merge tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim <kgene.kim@samsung.com>:

add support exynos mct device tree and move into drivers/clocksource

* tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  clocksource: mct: Add terminating entry for exynos_mct_ids table
  clocksource: mct: Add missing semicolons in exynos_mct.c
  ARM: EXYNOS: move mct driver to drivers/clocksource
  ARM: EXYNOS: remove static io-remapping of mct registers for Exynos5
  ARM: dts: add mct device tree node for all supported Exynos SoC's
  ARM: EXYNOS: allow dt based discovery of mct controller using clocksource_of_init
  ARM: EXYNOS: add device tree support for MCT controller driver
  ARM: EXYNOS: prepare an array of MCT interrupt numbers and use it
  ARM: EXYNOS: add a register base address variable in mct controller driver

Conflicts:
	drivers/clocksource/Makefile
	drivers/clocksource/exynos_mct.c

[arnd: adapt to CLOCKSOURCE_OF_DECLARE interface change]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

3 files changed, 563 insertions, 1 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3167fda9bbb3..73fcddb8314d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -70,3 +70,8 @@ config CLKSRC_METAG_GENERIC
         def_bool y if METAG
         help
           This option enables support for the Meta per-thread timers.
+
+config CLKSRC_EXYNOS_MCT
+        def_bool y if ARCH_EXYNOS
+        help
+          Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index e74c8ce26bf0..cd1f09cbd61a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -19,7 +19,8 @@ obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835_timer.o
 obj-$(CONFIG_SUNXI_TIMER)       += sunxi_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
-obj-$(CONFIG_CADENCE_TTC_TIMER)         += cadence_ttc_timer.o
+obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
+obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)            += arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
new file mode 100644
index 000000000000..957af8636c9d
--- /dev/null
+++ b/drivers/clocksource/exynos_mct.c
@@ -0,0 +1,556 @@
+/* linux/arch/arm/mach-exynos4/mct.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 MCT(Multi-Core Timer) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/percpu.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/clocksource.h>
+
+#include <asm/arch_timer.h>
+#include <asm/localtimer.h>
+
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <asm/mach/time.h>
+
+#define EXYNOS4_MCTREG(x)               (x)
+#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
+#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
+#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
+#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET              (0x00)
+#define MCT_L_ICNTB_OFFSET              (0x08)
+#define MCT_L_TCON_OFFSET               (0x20)
+#define MCT_L_INT_CSTAT_OFFSET          (0x30)
+#define MCT_L_INT_ENB_OFFSET            (0x34)
+#define MCT_L_WSTAT_OFFSET              (0x40)
+#define MCT_G_TCON_START                (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
+#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
+#define MCT_L_TCON_INT_START            (1 << 1)
+#define MCT_L_TCON_TIMER_START          (1 << 0)
+
+#define TICK_BASE_CNT   1
+
+enum {
+        MCT_INT_SPI,
+        MCT_INT_PPI
+};
+
+enum {
+        MCT_G0_IRQ,
+        MCT_G1_IRQ,
+        MCT_G2_IRQ,
+        MCT_G3_IRQ,
+        MCT_L0_IRQ,
+        MCT_L1_IRQ,
+        MCT_L2_IRQ,
+        MCT_L3_IRQ,
+        MCT_NR_IRQS,
+};
+
+static void __iomem *reg_base;
+static unsigned long clk_rate;
+static unsigned int mct_int_type;
+static int mct_irqs[MCT_NR_IRQS];
+
+struct mct_clock_event_device {
+        struct clock_event_device *evt;
+        unsigned long base;
+        char name[10];
+};
+
+static void exynos4_mct_write(unsigned int value, unsigned long offset)
+{
+        unsigned long stat_addr;
+        u32 mask;
+        u32 i;
+
+        __raw_writel(value, reg_base + offset);
+
+        if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
+                stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+                switch (offset & EXYNOS4_MCT_L_MASK) {
+                case MCT_L_TCON_OFFSET:
+                        mask = 1 << 3;          /* L_TCON write status */
+                        break;
+                case MCT_L_ICNTB_OFFSET:
+                        mask = 1 << 1;          /* L_ICNTB write status */
+                        break;
+                case MCT_L_TCNTB_OFFSET:
+                        mask = 1 << 0;          /* L_TCNTB write status */
+                        break;
+                default:
+                        return;
+                }
+        } else {
+                switch (offset) {
+                case EXYNOS4_MCT_G_TCON:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 16;         /* G_TCON write status */
+                        break;
+                case EXYNOS4_MCT_G_COMP0_L:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 0;          /* G_COMP0_L write status */
+                        break;
+                case EXYNOS4_MCT_G_COMP0_U:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 1;          /* G_COMP0_U write status */
+                        break;
+                case EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
+                        break;
+                case EXYNOS4_MCT_G_CNT_L:
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 0;          /* G_CNT_L write status */
+                        break;
+                case EXYNOS4_MCT_G_CNT_U:
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 1;          /* G_CNT_U write status */
+                        break;
+                default:
+                        return;
+                }
+        }
+
+        /* Wait maximum 1 ms until written values are applied */
+        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
+                if (__raw_readl(reg_base + stat_addr) & mask) {
+                        __raw_writel(mask, reg_base + stat_addr);
+                        return;
+                }
+
+        panic("MCT hangs af