diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-01-28 18:33:08 -0500 |
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committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-04-16 06:03:22 -0400 |
commit | 5cfe2d151f8f55052f5463e725d3d3a4aa51335d (patch) | |
tree | b645697ab42596ed34abd02d272228f15c70d2e3 /drivers/clocksource/sh_tmu.c | |
parent | a5de49f436e2bc498c1d13f6f8a9afaf19cb5f95 (diff) |
clocksource: sh_tmu: Replace hardcoded register values with macros
Define symbolic macros for all used registers bits.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/clocksource/sh_tmu.c')
-rw-r--r-- | drivers/clocksource/sh_tmu.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c index 55b7a37f0c9b..63ed92d56c8f 100644 --- a/drivers/clocksource/sh_tmu.c +++ b/drivers/clocksource/sh_tmu.c | |||
@@ -69,6 +69,15 @@ static DEFINE_RAW_SPINLOCK(sh_tmu_lock); | |||
69 | #define TCNT 1 /* channel register */ | 69 | #define TCNT 1 /* channel register */ |
70 | #define TCR 2 /* channel register */ | 70 | #define TCR 2 /* channel register */ |
71 | 71 | ||
72 | #define TCR_UNF (1 << 8) | ||
73 | #define TCR_UNIE (1 << 5) | ||
74 | #define TCR_TPSC_CLK4 (0 << 0) | ||
75 | #define TCR_TPSC_CLK16 (1 << 0) | ||
76 | #define TCR_TPSC_CLK64 (2 << 0) | ||
77 | #define TCR_TPSC_CLK256 (3 << 0) | ||
78 | #define TCR_TPSC_CLK1024 (4 << 0) | ||
79 | #define TCR_TPSC_MASK (7 << 0) | ||
80 | |||
72 | static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) | 81 | static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) |
73 | { | 82 | { |
74 | unsigned long offs; | 83 | unsigned long offs; |
@@ -140,7 +149,7 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch) | |||
140 | 149 | ||
141 | /* configure channel to parent clock / 4, irq off */ | 150 | /* configure channel to parent clock / 4, irq off */ |
142 | ch->rate = clk_get_rate(ch->tmu->clk) / 4; | 151 | ch->rate = clk_get_rate(ch->tmu->clk) / 4; |
143 | sh_tmu_write(ch, TCR, 0x0000); | 152 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
144 | 153 | ||
145 | /* enable channel */ | 154 | /* enable channel */ |
146 | sh_tmu_start_stop_ch(ch, 1); | 155 | sh_tmu_start_stop_ch(ch, 1); |
@@ -165,7 +174,7 @@ static void __sh_tmu_disable(struct sh_tmu_channel *ch) | |||
165 | sh_tmu_start_stop_ch(ch, 0); | 174 | sh_tmu_start_stop_ch(ch, 0); |
166 | 175 | ||
167 | /* disable interrupts in TMU block */ | 176 | /* disable interrupts in TMU block */ |
168 | sh_tmu_write(ch, TCR, 0x0000); | 177 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
169 | 178 | ||
170 | /* stop clock */ | 179 | /* stop clock */ |
171 | clk_disable(ch->tmu->clk); | 180 | clk_disable(ch->tmu->clk); |
@@ -195,7 +204,7 @@ static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, | |||
195 | sh_tmu_read(ch, TCR); | 204 | sh_tmu_read(ch, TCR); |
196 | 205 | ||
197 | /* enable interrupt */ | 206 | /* enable interrupt */ |
198 | sh_tmu_write(ch, TCR, 0x0020); | 207 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
199 | 208 | ||
200 | /* reload delta value in case of periodic timer */ | 209 | /* reload delta value in case of periodic timer */ |
201 | if (periodic) | 210 | if (periodic) |
@@ -215,9 +224,9 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) | |||
215 | 224 | ||
216 | /* disable or acknowledge interrupt */ | 225 | /* disable or acknowledge interrupt */ |
217 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) | 226 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) |
218 | sh_tmu_write(ch, TCR, 0x0000); | 227 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
219 | else | 228 | else |
220 | sh_tmu_write(ch, TCR, 0x0020); | 229 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
221 | 230 | ||
222 | /* notify clockevent layer */ | 231 | /* notify clockevent layer */ |
223 | ch->ced.event_handler(&ch->ced); | 232 | ch->ced.event_handler(&ch->ced); |