Merge tag 'v3.11-rockchip-basics' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc

From Heiko Stuebner:

Adds basic support for Rockchip Cortex-A9 SoCs.

* tag 'v3.11-rockchip-basics' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm: add basic support for Rockchip RK3066a boards
  arm: add debug uarts for rockchip rk29xx and rk3xxx series
  arm: Add basic clocks for Rockchip rk3066a SoCs
  clocksource: dw_apb_timer_of: use clocksource_of_init
  clocksource: dw_apb_timer_of: select DW_APB_TIMER
  clocksource: dw_apb_timer_of: add clock-handling
  clocksource: dw_apb_timer_of: enable the use the clocksource as sched clock

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 63 insertions, 32 deletions

diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index ab09ed3742ee..cef554432a33 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -20,6 +20,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/clk.h>
 
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
@@ -27,14 +28,37 @@
 static void timer_get_base_and_rate(struct device_node *np,
                                     void __iomem **base, u32 *rate)
 {
+        struct clk *timer_clk;
+        struct clk *pclk;
+
         *base = of_iomap(np, 0);
 
         if (!*base)
                 panic("Unable to map regs for %s", np->name);
 
+        /*
+         * Not all implementations use a periphal clock, so don't panic
+         * if it's not present
+         */
+        pclk = of_clk_get_by_name(np, "pclk");
+        if (!IS_ERR(pclk))
+                if (clk_prepare_enable(pclk))
+                        pr_warn("pclk for %s is present, but could not be activated\n",
+                                np->name);
+
+        timer_clk = of_clk_get_by_name(np, "timer");
+        if (IS_ERR(timer_clk))
+                goto try_clock_freq;
+
+        if (!clk_prepare_enable(timer_clk)) {
+                *rate = clk_get_rate(timer_clk);
+                return;
+        }
+
+try_clock_freq:
         if (of_property_read_u32(np, "clock-freq", rate) &&
                 of_property_read_u32(np, "clock-frequency", rate))
-                panic("No clock-frequency property for %s", np->name);
+                panic("No clock nor clock-frequency property for %s", np->name);
 }
 
 static void add_clockevent(struct device_node *event_timer)
@@ -57,6 +81,9 @@ static void add_clockevent(struct device_node *event_timer)
         dw_apb_clockevent_register(ced);
 }
 
+static void __iomem *sched_io_base;
+static u32 sched_rate;
+
 static void add_clocksource(struct device_node *source_timer)
 {
         void __iomem *iobase;
@@ -71,9 +98,15 @@ static void add_clocksource(struct device_node *source_timer)
 
         dw_apb_clocksource_start(cs);
         dw_apb_clocksource_register(cs);
-}
 
-static void __iomem *sched_io_base;
+        /*
+         * Fallback to use the clocksource as sched_clock if no separate
+         * timer is found. sched_io_base then points to the current_value
+         * register of the clocksource timer.
+         */
+        sched_io_base = iobase + 0x04;
+        sched_rate = rate;
+}
 
 static u32 read_sched_clock(void)
 {
@@ -89,39 +122,37 @@ static const struct of_device_id sptimer_ids[] __initconst = {
 static void init_sched_clock(void)
 {
         struct device_node *sched_timer;
-        u32 rate;
 
         sched_timer = of_find_matching_node(NULL, sptimer_ids);
-        if (!sched_timer)
-                panic("No RTC for sched clock to use");
+        if (sched_timer) {
+                timer_get_base_and_rate(sched_timer, &sched_io_base,
+                                        &sched_rate);
+                of_node_put(sched_timer);
+        }
 
-        timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
-        of_node_put(sched_timer);
-
-        setup_sched_clock(read_sched_clock, 32, rate);
+        setup_sched_clock(read_sched_clock, 32, sched_rate);
 }
 
-static const struct of_device_id osctimer_ids[] __initconst = {
-        { .compatible = "picochip,pc3x2-timer" },
-        { .compatible = "snps,dw-apb-timer-osc" },
-        {},
-};
-
-void __init dw_apb_timer_init(void)
+static int num_called;
+static void __init dw_apb_timer_init(struct device_node *timer)
 {
-        struct device_node *event_timer, *source_timer;
-
-        event_timer = of_find_matching_node(NULL, osctimer_ids);
-        if (!event_timer)
-                panic("No timer for clockevent");
-        add_clockevent(event_timer);
-
-        source_timer = of_find_matching_node(event_timer, osctimer_ids);
-        if (!source_timer)
-                panic("No timer for clocksource");
-        add_clocksource(source_timer);
-
-        of_node_put(source_timer);
-
-        init_sched_clock();
+        switch (num_called) {
+        case 0:
+                pr_debug("%s: found clockevent timer\n", __func__);
+                add_clockevent(timer);
+                of_node_put(timer);
+                break;
+        case 1:
+                pr_debug("%s: found clocksource timer\n", __func__);
+                add_clocksource(timer);
+                of_node_put(timer);
+                init_sched_clock();
+                break;
+        default:
+                break;
+        }
+
+        num_called++;
 }
+CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
+CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init);