clk: st: Support for ClockGenA9/DDR/GPU

The patch added support for DT registration of ClockGenA9/DDR/GPU

ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence
only CLK_OF_DECLARE implementation is required.

ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence
only CLK_OF_DECLARE implementation is required.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 139 insertions, 0 deletions

diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index c6b38b05df1c..bca0a0badbfa 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -110,6 +110,76 @@ static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
         .ops            = &stm_pll3200c32_ops,
 };
 
+/* 415 specific */
+static struct clkgen_pll_data st_pll3200c32_a9_415 = {
+        .pdn_status     = CLKGEN_FIELD(0x0,     0x1,                    0),
+        .locked_status  = CLKGEN_FIELD(0x6C,    0x1,                    0),
+        .ndiv           = CLKGEN_FIELD(0x0,     C32_NDIV_MASK,          9),
+        .idf            = CLKGEN_FIELD(0x0,     C32_IDF_MASK,           22),
+        .num_odfs = 1,
+        .odf =          { CLKGEN_FIELD(0x0,     C32_ODF_MASK,           3) },
+        .odf_gate =     { CLKGEN_FIELD(0x0,     0x1,                    28) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
+static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
+        .pdn_status     = CLKGEN_FIELD(0x0,     0x1,                    0),
+        .locked_status  = CLKGEN_FIELD(0x100,   0x1,                    0),
+        .ndiv           = CLKGEN_FIELD(0x8,     C32_NDIV_MASK,          0),
+        .idf            = CLKGEN_FIELD(0x0,     C32_IDF_MASK,           25),
+        .num_odfs = 2,
+        .odf            = { CLKGEN_FIELD(0x8,   C32_ODF_MASK,           8),
+                            CLKGEN_FIELD(0x8,   C32_ODF_MASK,           14) },
+        .odf_gate       = { CLKGEN_FIELD(0x4,   0x1,                    28),
+                            CLKGEN_FIELD(0x4,   0x1,                    29) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
+static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
+        .pdn_status     = CLKGEN_FIELD(0x144,   0x1,                    3),
+        .locked_status  = CLKGEN_FIELD(0x168,   0x1,                    0),
+        .ldf            = CLKGEN_FIELD(0x0,     C32_LDF_MASK,           3),
+        .idf            = CLKGEN_FIELD(0x0,     C32_IDF_MASK,           0),
+        .num_odfs = 0,
+        .odf            = { CLKGEN_FIELD(0x0,   C32_ODF_MASK,           10) },
+        .ops            = &st_pll1200c32_ops,
+};
+
+/* 416 specific */
+static struct clkgen_pll_data st_pll3200c32_a9_416 = {
+        .pdn_status     = CLKGEN_FIELD(0x0,     0x1,                    0),
+        .locked_status  = CLKGEN_FIELD(0x6C,    0x1,                    0),
+        .ndiv           = CLKGEN_FIELD(0x8,     C32_NDIV_MASK,          0),
+        .idf            = CLKGEN_FIELD(0x0,     C32_IDF_MASK,           25),
+        .num_odfs = 1,
+        .odf            = { CLKGEN_FIELD(0x8,   C32_ODF_MASK,           8) },
+        .odf_gate       = { CLKGEN_FIELD(0x4,   0x1,                    28) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
+static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
+        .pdn_status     = CLKGEN_FIELD(0x0,     0x1,                    0),
+        .locked_status  = CLKGEN_FIELD(0x10C,   0x1,                    0),
+        .ndiv           = CLKGEN_FIELD(0x8,     C32_NDIV_MASK,          0),
+        .idf            = CLKGEN_FIELD(0x0,     C32_IDF_MASK,           25),
+        .num_odfs = 2,
+        .odf            = { CLKGEN_FIELD(0x8,   C32_ODF_MASK,           8),
+                            CLKGEN_FIELD(0x8,   C32_ODF_MASK,           14) },
+        .odf_gate       = { CLKGEN_FIELD(0x4,   0x1,                    28),
+                            CLKGEN_FIELD(0x4,   0x1,                    29) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
+static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
+        .pdn_status     = CLKGEN_FIELD(0x8E4,   0x1,                    3),
+        .locked_status  = CLKGEN_FIELD(0x90C,   0x1,                    0),
+        .ldf            = CLKGEN_FIELD(0x0,     C32_LDF_MASK,           3),
+        .idf            = CLKGEN_FIELD(0x0,     C32_IDF_MASK,           0),
+        .num_odfs = 0,
+        .odf            = { CLKGEN_FIELD(0x0,   C32_ODF_MASK,           10) },
+        .ops            = &st_pll1200c32_ops,
+};
+
 /**
  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  *
@@ -484,6 +554,22 @@ static struct of_device_id c32_pll_of_match[] = {
                 .compatible = "st,plls-c32-a1x-1",
                 .data = &st_pll3200c32_a1x_1,
         },
+        {
+                .compatible = "st,stih415-plls-c32-a9",
+                .data = &st_pll3200c32_a9_415,
+        },
+        {
+                .compatible = "st,stih415-plls-c32-ddr",
+                .data = &st_pll3200c32_ddr_415,
+        },
+        {
+                .compatible = "st,stih416-plls-c32-a9",
+                .data = &st_pll3200c32_a9_416,
+        },
+        {
+                .compatible = "st,stih416-plls-c32-ddr",
+                .data = &st_pll3200c32_ddr_416,
+        },
         {}
 };
 
@@ -557,3 +643,56 @@ err:
         kfree(clk_data);
 }
 CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
+
+static struct of_device_id c32_gpu_pll_of_match[] = {
+        {
+                .compatible = "st,stih415-gpu-pll-c32",
+                .data = &st_pll1200c32_gpu_415,
+        },
+        {
+                .compatible = "st,stih416-gpu-pll-c32",
+                .data = &st_pll1200c32_gpu_416,
+        },
+};
+
+static void __init clkgengpu_c32_pll_setup(struct device_node *np)
+{
+        const struct of_device_id *match;
+        struct clk *clk;
+        const char *parent_name;
+        void __iomem *reg;
+        const char *clk_name;
+        struct clkgen_pll_data  *data;
+
+        match = of_match_node(c32_gpu_pll_of_match, np);
+        if (!match) {
+                pr_err("%s: No matching data\n", __func__);
+                return;
+        }
+
+        data = (struct clkgen_pll_data *)match->data;
+
+        parent_name = of_clk_get_parent_name(np, 0);
+        if (!parent_name)
+                return;
+
+        reg = clkgen_get_register_base(np);
+        if (!reg)
+                return;
+
+        if (of_property_read_string_index(np, "clock-output-names",
+                                          0, &clk_name))
+                return;
+
+        /*
+         * PLL 1200MHz output
+         */
+        clk = clkgen_pll_register(parent_name, data, reg, clk_name);
+
+        if (!IS_ERR(clk))
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+        return;
+}
+CLK_OF_DECLARE(clkgengpu_c32_pll,
+               "st,clkgengpu-pll-c32", clkgengpu_c32_pll_setup);