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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 18:49:04 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 18:49:04 -0400
commitbef4a0ab984662d4ccd68d431a7c4ef3daebcb43 (patch)
tree3f1a2797dbf2fde9235c47e023be929e32fa9265 /drivers/clk
parent7eb69529cbaf4229baf5559a400a7a46352c6e52 (diff)
parent12d298865ec5d0f14dd570c3506c270880769ed7 (diff)
Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux
Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/Kconfig8
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-bcm2835.c2
-rw-r--r--drivers/clk/clk-divider.c8
-rw-r--r--drivers/clk/clk-fixed-factor.c2
-rw-r--r--drivers/clk/clk-fixed-rate.c1
-rw-r--r--drivers/clk/clk-gate.c7
-rw-r--r--drivers/clk/clk-mux.c19
-rw-r--r--drivers/clk/clk-nomadik.c4
-rw-r--r--drivers/clk/clk-prima2.c2
-rw-r--r--drivers/clk/clk-s2mps11.c273
-rw-r--r--drivers/clk/clk-u300.c4
-rw-r--r--drivers/clk/clk-wm831x.c16
-rw-r--r--drivers/clk/clk.c450
-rw-r--r--drivers/clk/mmp/clk-mmp2.c39
-rw-r--r--drivers/clk/mmp/clk-pxa168.c40
-rw-r--r--drivers/clk/mmp/clk-pxa910.c31
-rw-r--r--drivers/clk/mvebu/armada-370.c14
-rw-r--r--drivers/clk/mvebu/armada-xp.c12
-rw-r--r--drivers/clk/mvebu/clk-cpu.c4
-rw-r--r--drivers/clk/mvebu/common.c18
-rw-r--r--drivers/clk/mvebu/dove.c12
-rw-r--r--drivers/clk/mvebu/kirkwood.c14
-rw-r--r--drivers/clk/mxs/clk-imx23.c1
-rw-r--r--drivers/clk/mxs/clk.h4
-rw-r--r--drivers/clk/samsung/Makefile3
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c8
-rw-r--r--drivers/clk/samsung/clk-exynos4.c605
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c129
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c123
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c18
-rw-r--r--drivers/clk/samsung/clk-pll.c701
-rw-r--r--drivers/clk/samsung/clk-pll.h85
-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c473
-rw-r--r--drivers/clk/samsung/clk.c10
-rw-r--r--drivers/clk/samsung/clk.h55
-rw-r--r--drivers/clk/spear/spear1310_clock.c179
-rw-r--r--drivers/clk/spear/spear1340_clock.c97
-rw-r--r--drivers/clk/spear/spear3xx_clock.c57
-rw-r--r--drivers/clk/spear/spear6xx_clock.c35
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c270
-rw-r--r--drivers/clk/tegra/clk-tegra114.c38
-rw-r--r--drivers/clk/tegra/clk-tegra20.c8
-rw-r--r--drivers/clk/tegra/clk-tegra30.c37
-rw-r--r--drivers/clk/versatile/clk-vexpress.c4
-rw-r--r--drivers/clk/zynq/clkc.c82
-rw-r--r--drivers/clk/zynq/pll.c19
47 files changed, 2953 insertions, 1069 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 51380d655d1a..279407a36391 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -27,7 +27,7 @@ config COMMON_CLK_DEBUG
27 bool "DebugFS representation of clock tree" 27 bool "DebugFS representation of clock tree"
28 select DEBUG_FS 28 select DEBUG_FS
29 ---help--- 29 ---help---
30 Creates a directory hierchy in debugfs for visualizing the clk 30 Creates a directory hierarchy in debugfs for visualizing the clk
31 tree structure. Each directory contains read-only members 31 tree structure. Each directory contains read-only members
32 that export information specific to that clk node: clk_rate, 32 that export information specific to that clk node: clk_rate,
33 clk_flags, clk_prepare_count, clk_enable_count & 33 clk_flags, clk_prepare_count, clk_enable_count &
@@ -64,6 +64,12 @@ config COMMON_CLK_SI5351
64 This driver supports Silicon Labs 5351A/B/C programmable clock 64 This driver supports Silicon Labs 5351A/B/C programmable clock
65 generators. 65 generators.
66 66
67config COMMON_CLK_S2MPS11
68 tristate "Clock driver for S2MPS11 MFD"
69 depends on MFD_SEC_CORE
70 ---help---
71 This driver supports S2MPS11 crystal oscillator clock.
72
67config CLK_TWL6040 73config CLK_TWL6040
68 tristate "External McPDM functional clock from twl6040" 74 tristate "External McPDM functional clock from twl6040"
69 depends on TWL6040_CORE 75 depends on TWL6040_CORE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2bdf334..7b111062ccba 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -40,5 +40,6 @@ obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
40obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 40obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
41obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o 41obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
42obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o 42obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
43obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
43obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o 44obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
44obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o 45obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
index 792bc57a9db7..5fb4ff53d088 100644
--- a/drivers/clk/clk-bcm2835.c
+++ b/drivers/clk/clk-bcm2835.c
@@ -23,7 +23,7 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/of.h> 24#include <linux/of.h>
25 25
26static const __initconst struct of_device_id clk_match[] = { 26static const struct of_device_id clk_match[] __initconst = {
27 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, 27 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
28 { } 28 { }
29}; 29};
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2cb959..8d3009e44fba 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
104 struct clk_divider *divider = to_clk_divider(hw); 104 struct clk_divider *divider = to_clk_divider(hw);
105 unsigned int div, val; 105 unsigned int div, val;
106 106
107 val = readl(divider->reg) >> divider->shift; 107 val = clk_readl(divider->reg) >> divider->shift;
108 val &= div_mask(divider); 108 val &= div_mask(divider);
109 109
110 div = _get_div(divider, val); 110 div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
230 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { 230 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
231 val = div_mask(divider) << (divider->shift + 16); 231 val = div_mask(divider) << (divider->shift + 16);
232 } else { 232 } else {
233 val = readl(divider->reg); 233 val = clk_readl(divider->reg);
234 val &= ~(div_mask(divider) << divider->shift); 234 val &= ~(div_mask(divider) << divider->shift);
235 } 235 }
236 val |= value << divider->shift; 236 val |= value << divider->shift;
237 writel(val, divider->reg); 237 clk_writel(val, divider->reg);
238 238
239 if (divider->lock) 239 if (divider->lock)
240 spin_unlock_irqrestore(divider->lock, flags); 240 spin_unlock_irqrestore(divider->lock, flags);
@@ -317,6 +317,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
317 return _register_divider(dev, name, parent_name, flags, reg, shift, 317 return _register_divider(dev, name, parent_name, flags, reg, shift,
318 width, clk_divider_flags, NULL, lock); 318 width, clk_divider_flags, NULL, lock);
319} 319}
320EXPORT_SYMBOL_GPL(clk_register_divider);
320 321
321/** 322/**
322 * clk_register_divider_table - register a table based divider clock with 323 * clk_register_divider_table - register a table based divider clock with
@@ -341,3 +342,4 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
341 return _register_divider(dev, name, parent_name, flags, reg, shift, 342 return _register_divider(dev, name, parent_name, flags, reg, shift,
342 width, clk_divider_flags, table, lock); 343 width, clk_divider_flags, table, lock);
343} 344}
345EXPORT_SYMBOL_GPL(clk_register_divider_table);
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 9ff7d510faa3..0e1d89b4321b 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -97,6 +97,8 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
97 97
98 return clk; 98 return clk;
99} 99}
100EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
101
100#ifdef CONFIG_OF 102#ifdef CONFIG_OF
101/** 103/**
102 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock 104 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index dc58fbd8516f..1ed591ab8b1d 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -80,6 +80,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
80 80
81 return clk; 81 return clk;
82} 82}
83EXPORT_SYMBOL_GPL(clk_register_fixed_rate);
83 84
84#ifdef CONFIG_OF 85#ifdef CONFIG_OF
85/** 86/**
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 790306e921c8..4a58c55255bd 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
58 if (set) 58 if (set)
59 reg |= BIT(gate->bit_idx); 59 reg |= BIT(gate->bit_idx);
60 } else { 60 } else {
61 reg = readl(gate->reg); 61 reg = clk_readl(gate->reg);
62 62
63 if (set) 63 if (set)
64 reg |= BIT(gate->bit_idx); 64 reg |= BIT(gate->bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
66 reg &= ~BIT(gate->bit_idx); 66 reg &= ~BIT(gate->bit_idx);
67 } 67 }
68 68
69 writel(reg, gate->reg); 69 clk_writel(reg, gate->reg);
70 70
71 if (gate->lock) 71 if (gate->lock)
72 spin_unlock_irqrestore(gate->lock, flags); 72 spin_unlock_irqrestore(gate->lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
89 u32 reg; 89 u32 reg;
90 struct clk_gate *gate = to_clk_gate(hw); 90 struct clk_gate *gate = to_clk_gate(hw);
91 91
92 reg = readl(gate->reg); 92 reg = clk_readl(gate->reg);
93 93
94 /* if a set bit disables this clk, flip it before masking */ 94 /* if a set bit disables this clk, flip it before masking */
95 if (gate->flags & CLK_GATE_SET_TO_DISABLE) 95 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
@@ -161,3 +161,4 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
161 161
162 return clk; 162 return clk;
163} 163}
164EXPORT_SYMBOL_GPL(clk_register_gate);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 614444ca40cd..4f96ff3ba728 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
42 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so 42 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
43 * val = 0x4 really means "bit 2, index starts at bit 0" 43 * val = 0x4 really means "bit 2, index starts at bit 0"
44 */ 44 */
45 val = readl(mux->reg) >> mux->shift; 45 val = clk_readl(mux->reg) >> mux->shift;
46 val &= mux->mask; 46 val &= mux->mask;
47 47
48 if (mux->table) { 48 if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
89 if (mux->flags & CLK_MUX_HIWORD_MASK) { 89 if (mux->flags & CLK_MUX_HIWORD_MASK) {
90 val = mux->mask << (mux->shift + 16); 90 val = mux->mask << (mux->shift + 16);
91 } else { 91 } else {
92 val = readl(mux->reg); 92 val = clk_readl(mux->reg);
93 val &= ~(mux->mask << mux->shift); 93 val &= ~(mux->mask << mux->shift);
94 } 94 }
95 val |= index << mux->shift; 95 val |= index << mux->shift;
96 writel(val, mux->reg); 96 clk_writel(val, mux->reg);
97 97
98 if (mux->lock) 98 if (mux->lock)
99 spin_unlock_irqrestore(mux->lock, flags); 99 spin_unlock_irqrestore(mux->lock, flags);
@@ -104,9 +104,15 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
104const struct clk_ops clk_mux_ops = { 104const struct clk_ops clk_mux_ops = {
105 .get_parent = clk_mux_get_parent, 105 .get_parent = clk_mux_get_parent,
106 .set_parent = clk_mux_set_parent, 106 .set_parent = clk_mux_set_parent,
107 .determine_rate = __clk_mux_determine_rate,
107}; 108};
108EXPORT_SYMBOL_GPL(clk_mux_ops); 109EXPORT_SYMBOL_GPL(clk_mux_ops);
109 110
111const struct clk_ops clk_mux_ro_ops = {
112 .get_parent = clk_mux_get_parent,
113};
114EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
115
110struct clk *clk_register_mux_table(struct device *dev, const char *name, 116struct clk *clk_register_mux_table(struct device *dev, const char *name,
111 const char **parent_names, u8 num_parents, unsigned long flags, 117 const char **parent_names, u8 num_parents, unsigned long flags,
112 void __iomem *reg, u8 shift, u32 mask, 118 void __iomem *reg, u8 shift, u32 mask,
@@ -133,7 +139,10 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
133 } 139 }
134 140
135 init.name = name; 141 init.name = name;
136 init.ops = &clk_mux_ops; 142 if (clk_mux_flags & CLK_MUX_READ_ONLY)
143 init.ops = &clk_mux_ro_ops;
144 else
145 init.ops = &clk_mux_ops;
137 init.flags = flags | CLK_IS_BASIC; 146 init.flags = flags | CLK_IS_BASIC;
138 init.parent_names = parent_names; 147 init.parent_names = parent_names;
139 init.num_parents = num_parents; 148 init.num_parents = num_parents;
@@ -154,6 +163,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
154 163
155 return clk; 164 return clk;
156} 165}
166EXPORT_SYMBOL_GPL(clk_register_mux_table);
157 167
158struct clk *clk_register_mux(struct device *dev, const char *name, 168struct clk *clk_register_mux(struct device *dev, const char *name,
159 const char **parent_names, u8 num_parents, unsigned long flags, 169 const char **parent_names, u8 num_parents, unsigned long flags,
@@ -166,3 +176,4 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
166 flags, reg, shift, mask, clk_mux_flags, 176 flags, reg, shift, mask, clk_mux_flags,
167 NULL, lock); 177 NULL, lock);
168} 178}
179EXPORT_SYMBOL_GPL(clk_register_mux);
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
index 6d819a37f647..51410c2ac2cb 100644
--- a/drivers/clk/clk-nomadik.c
+++ b/drivers/clk/clk-nomadik.c
@@ -479,12 +479,12 @@ static void __init of_nomadik_src_clk_setup(struct device_node *np)
479 of_clk_add_provider(np, of_clk_src_simple_get, clk); 479 of_clk_add_provider(np, of_clk_src_simple_get, clk);
480} 480}
481 481
482static const __initconst struct of_device_id nomadik_src_match[] = { 482static const struct of_device_id nomadik_src_match[] __initconst = {
483 { .compatible = "stericsson,nomadik-src" }, 483 { .compatible = "stericsson,nomadik-src" },
484 { /* sentinel */ } 484 { /* sentinel */ }
485}; 485};
486 486
487static const __initconst struct of_device_id nomadik_src_clk_match[] = { 487static const struct of_device_id nomadik_src_clk_match[] __initconst = {
488 { 488 {
489 .compatible = "fixed-clock", 489 .compatible = "fixed-clock",
490 .data = of_fixed_clk_setup, 490 .data = of_fixed_clk_setup,
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c
index 643ca653fef0..5ab95f1ad579 100644
--- a/drivers/clk/clk-prima2.c
+++ b/drivers/clk/clk-prima2.c
@@ -1034,7 +1034,7 @@ enum prima2_clk_index {
1034 usb0, usb1, maxclk, 1034 usb0, usb1, maxclk,
1035}; 1035};
1036 1036
1037static __initdata struct clk_hw* prima2_clk_hw_array[maxclk] = { 1037static struct clk_hw *prima2_clk_hw_array[maxclk] __initdata = {
1038 NULL, /* dummy */ 1038 NULL, /* dummy */
1039 NULL, 1039 NULL,
1040 &clk_pll1.hw, 1040 &clk_pll1.hw,
diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
new file mode 100644
index 000000000000..7be41e676a64
--- /dev/null
+++ b/drivers/clk/clk-s2mps11.c
@@ -0,0 +1,273 @@
1/*
2 * clk-s2mps11.c - Clock driver for S2MPS11.
3 *
4 * Copyright (C) 2013 Samsung Electornics
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/err.h>
24#include <linux/of.h>
25#include <linux/clkdev.h>
26#include <linux/regmap.h>
27#include <linux/clk-provider.h>
28#include <linux/platform_device.h>
29#include <linux/mfd/samsung/s2mps11.h>
30#include <linux/mfd/samsung/core.h>
31
32#define s2mps11_name(a) (a->hw.init->name)
33
34static struct clk **clk_table;
35static struct clk_onecell_data clk_data;
36
37enum {
38 S2MPS11_CLK_AP = 0,
39 S2MPS11_CLK_CP,
40 S2MPS11_CLK_BT,
41 S2MPS11_CLKS_NUM,
42};
43
44struct s2mps11_clk {
45 struct sec_pmic_dev *iodev;
46 struct clk_hw hw;
47 struct clk *clk;
48 struct clk_lookup *lookup;
49 u32 mask;
50 bool enabled;
51};
52
53static struct s2mps11_clk *to_s2mps11_clk(struct clk_hw *hw)
54{
55 return container_of(hw, struct s2mps11_clk, hw);
56}
57
58static int s2mps11_clk_prepare(struct clk_hw *hw)
59{
60 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
61 int ret;
62
63 ret = regmap_update_bits(s2mps11->iodev->regmap,
64 S2MPS11_REG_RTC_CTRL,
65 s2mps11->mask, s2mps11->mask);
66 if (!ret)
67 s2mps11->enabled = true;
68
69 return ret;
70}
71
72static void s2mps11_clk_unprepare(struct clk_hw *hw)
73{
74 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
75 int ret;
76
77 ret = regmap_update_bits(s2mps11->iodev->regmap, S2MPS11_REG_RTC_CTRL,
78 s2mps11->mask, ~s2mps11->mask);
79
80 if (!ret)
81 s2mps11->enabled = false;
82}
83
84static int s2mps11_clk_is_enabled(struct clk_hw *hw)
85{
86 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
87
88 return s2mps11->enabled;
89}
90
91static unsigned long s2mps11_clk_recalc_rate(struct clk_hw *hw,
92 unsigned long parent_rate)
93{
94 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
95 if (s2mps11->enabled)
96 return 32768;
97 else
98 return 0;
99}
100
101static struct clk_ops s2mps11_clk_ops = {
102 .prepare = s2mps11_clk_prepare,
103 .unprepare = s2mps11_clk_unprepare,
104 .is_enabled = s2mps11_clk_is_enabled,
105 .recalc_rate = s2mps11_clk_recalc_rate,
106};
107
108static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
109 [S2MPS11_CLK_AP] = {
110 .name = "s2mps11_ap",
111 .ops = &s2mps11_clk_ops,
112 .flags = CLK_IS_ROOT,
113 },
114 [S2MPS11_CLK_CP] = {
115 .name = "s2mps11_cp",
116 .ops = &s2mps11_clk_ops,
117 .flags = CLK_IS_ROOT,
118 },
119 [S2MPS11_CLK_BT] = {
120 .name = "s2mps11_bt",
121 .ops = &s2mps11_clk_ops,
122 .flags = CLK_IS_ROOT,
123 },
124};
125
126static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev)
127{
128 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
129 struct device_node *clk_np;
130 int i;
131
132 if (!iodev->dev->of_node)
133 return NULL;
134
135 clk_np = of_find_node_by_name(iodev->dev->of_node, "clocks");
136 if (!clk_np) {
137 dev_err(&pdev->dev, "could not find clock sub-node\n");
138 return ERR_PTR(-EINVAL);
139 }
140
141 clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) *
142 S2MPS11_CLKS_NUM, GFP_KERNEL);
143 if (!clk_table)
144 return ERR_PTR(-ENOMEM);
145
146 for (i = 0; i < S2MPS11_CLKS_NUM; i++)
147 of_property_read_string_index(clk_np, "clock-output-names", i,
148 &s2mps11_clks_init[i].name);
149
150 return clk_np;
151}
152
153static int s2mps11_clk_probe(struct platform_device *pdev)
154{
155 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
156 struct s2mps11_clk *s2mps11_clks, *s2mps11_clk;
157 struct device_node *clk_np = NULL;
158 int i, ret = 0;
159 u32 val;
160
161 s2mps11_clks = devm_kzalloc(&pdev->dev, sizeof(*s2mps11_clk) *
162 S2MPS11_CLKS_NUM, GFP_KERNEL);
163 if (!s2mps11_clks)
164 return -ENOMEM;
165
166 s2mps11_clk = s2mps11_clks;
167
168 clk_np = s2mps11_clk_parse_dt(pdev);
169 if (IS_ERR(clk_np))
170 return PTR_ERR(clk_np);
171
172 for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) {
173 s2mps11_clk->iodev = iodev;
174 s2mps11_clk->hw.init = &s2mps11_clks_init[i];
175 s2mps11_clk->mask = 1 << i;
176
177 ret = regmap_read(s2mps11_clk->iodev->regmap,
178 S2MPS11_REG_RTC_CTRL, &val);
179 if (ret < 0)
180 goto err_reg;
181
182 s2mps11_clk->enabled = val & s2mps11_clk->mask;
183
184 s2mps11_clk->clk = devm_clk_register(&pdev->dev,
185 &s2mps11_clk->hw);
186 if (IS_ERR(s2mps11_clk->clk)) {
187 dev_err(&pdev->dev, "Fail to register : %s\n",
188 s2mps11_name(s2mps11_clk));
189 ret = PTR_ERR(s2mps11_clk->clk);
190 goto err_reg;
191 }
192
193 s2mps11_clk->lookup = devm_kzalloc(&pdev->dev,
194 sizeof(struct clk_lookup), GFP_KERNEL);
195 if (!s2mps11_clk->lookup) {
196 ret = -ENOMEM;
197 goto err_lup;
198 }
199
200 s2mps11_clk->lookup->con_id = s2mps11_name(s2mps11_clk);
201 s2mps11_clk->lookup->clk = s2mps11_clk->clk;
202
203 clkdev_add(s2mps11_clk->lookup);
204 }
205
206 if (clk_table) {
207 for (i = 0; i < S2MPS11_CLKS_NUM; i++)
208 clk_table[i] = s2mps11_clks[i].clk;
209
210 clk_data.clks = clk_table;
211 clk_data.clk_num = S2MPS11_CLKS_NUM;
212 of_clk_add_provider(clk_np, of_clk_src_onecell_get, &clk_data);
213 }
214
215 platform_set_drvdata(pdev, s2mps11_clks);
216
217 return ret;
218err_lup:
219 devm_clk_unregister(&pdev->dev, s2mps11_clk->clk);
220err_reg:
221 while (s2mps11_clk > s2mps11_clks) {
222 if (s2mps11_clk->lookup) {
223 clkdev_drop(s2mps11_clk->lookup);
224 devm_clk_unregister(&pdev->dev, s2mps11_clk->clk);
225 }
226 s2mps11_clk--;
227 }
228
229 return ret;
230}
231
232static int s2mps11_clk_remove(struct platform_device *pdev)
233{
234 struct s2mps11_clk *s2mps11_clks = platform_get_drvdata(pdev);
235 int i;
236
237 for (i = 0; i < S2MPS11_CLKS_NUM; i++)
238 clkdev_drop(s2mps11_clks[i].lookup);
239
240 return 0;
241}
242
243static const struct platform_device_id s2mps11_clk_id[] = {
244 { "s2mps11-clk", 0},
245 { },
246};
247MODULE_DEVICE_TABLE(platform, s2mps11_clk_id);
248
249static struct platform_driver s2mps11_clk_driver = {
250 .driver = {
251 .name = "s2mps11-clk",
252 .owner = THIS_MODULE,
253 },
254 .probe = s2mps11_clk_probe,
255 .remove = s2mps11_clk_remove,
256 .id_table = s2mps11_clk_id,
257};
258
259static int __init s2mps11_clk_init(void)
260{
261 return platform_driver_register(&s2mps11_clk_driver);
262}
263subsys_initcall(s2mps11_clk_init);
264
265static void __init s2mps11_clk_cleanup(void)
266{
267 platform_driver_unregister(&s2mps11_clk_driver);
268}
269module_exit(s2mps11_clk_cleanup);
270
271MODULE_DESCRIPTION("S2MPS11 Clock Driver");
272MODULE_AUTHOR("Yadwinder Singh Brar <yadi.brar@samsung.com>");
273MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 8774e058cb6c..3efbdd078d14 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -746,7 +746,7 @@ struct u300_clock {
746 u16 clk_val; 746 u16 clk_val;
747}; 747};
748 748
749struct u300_clock const __initconst u300_clk_lookup[] = { 749static struct u300_clock const u300_clk_lookup[] __initconst = {
750 { 750 {
751 .type = U300_CLK_TYPE_REST, 751 .type = U300_CLK_TYPE_REST,
752 .id = 3, 752 .id = 3,
@@ -1151,7 +1151,7 @@ static void __init of_u300_syscon_mclk_init(struct device_node *np)
1151 of_clk_add_provider(np, of_clk_src_simple_get, clk); 1151 of_clk_add_provider(np, of_clk_src_simple_get, clk);
1152} 1152}
1153 1153
1154static const __initconst struct of_device_id u300_clk_match[] = { 1154static const struct of_device_id u300_clk_match[] __initconst = {
1155 { 1155 {
1156 .compatible = "fixed-clock", 1156 .compatible = "fixed-clock",
1157 .data = of_fixed_clk_setup, 1157 .data = of_fixed_clk_setup,
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 1b3f8c9b98cc..805b4c344006 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -31,7 +31,7 @@ struct wm831x_clk {
31 bool xtal_ena; 31 bool xtal_ena;
32}; 32};
33 33
34static int wm831x_xtal_is_enabled(struct clk_hw *hw) 34static int wm831x_xtal_is_prepared(struct clk_hw *hw)
35{ 35{
36 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 36 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
37 xtal_hw); 37 xtal_hw);
@@ -52,7 +52,7 @@ static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
52} 52}
53 53
54static const struct clk_ops wm831x_xtal_ops = { 54static const struct clk_ops wm831x_xtal_ops = {
55 .is_enabled = wm831x_xtal_is_enabled, 55 .is_prepared = wm831x_xtal_is_prepared,
56 .recalc_rate = wm831x_xtal_recalc_rate, 56 .recalc_rate = wm831x_xtal_recalc_rate,
57}; 57};
58 58
@@ -73,7 +73,7 @@ static const unsigned long wm831x_fll_auto_rates[] = {
73 24576000, 73 24576000,
74}; 74};
75 75
76static int wm831x_fll_is_enabled(struct clk_hw *hw) 76static int wm831x_fll_is_prepared(struct clk_hw *hw)
77{ 77{
78 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 78 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
79 fll_hw); 79 fll_hw);
@@ -170,7 +170,7 @@ static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
170 if (i == ARRAY_SIZE(wm831x_fll_auto_rates)) 170 if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
171 return -EINVAL; 171 return -EINVAL;
172 172
173 if (wm831x_fll_is_enabled(hw)) 173 if (wm831x_fll_is_prepared(hw))
174 return -EPERM; 174 return -EPERM;
175 175
176 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2, 176 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
@@ -220,7 +220,7 @@ static u8 wm831x_fll_get_parent(struct clk_hw *hw)
220} 220}
221 221
222static const struct clk_ops wm831x_fll_ops = { 222static const struct clk_ops wm831x_fll_ops = {
223 .is_enabled = wm831x_fll_is_enabled, 223 .is_prepared = wm831x_fll_is_prepared,
224 .prepare = wm831x_fll_prepare, 224 .prepare = wm831x_fll_prepare,
225 .unprepare = wm831x_fll_unprepare, 225 .unprepare = wm831x_fll_unprepare,
226 .round_rate = wm831x_fll_round_rate, 226 .round_rate = wm831x_fll_round_rate,
@@ -237,7 +237,7 @@ static struct clk_init_data wm831x_fll_init = {
237 .flags = CLK_SET_RATE_GATE, 237 .flags = CLK_SET_RATE_GATE,
238}; 238};
239 239
240static int wm831x_clkout_is_enabled(struct clk_hw *hw) 240static int wm831x_clkout_is_prepared(struct clk_hw *hw)
241{ 241{
242 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 242 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
243 clkout_hw); 243 clkout_hw);
@@ -335,7 +335,7 @@ static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
335} 335}
336 336
337static const struct clk_ops wm831x_clkout_ops = { 337static const struct clk_ops wm831x_clkout_ops = {
338 .is_enabled = wm831x_clkout_is_enabled, 338 .is_prepared = wm831x_clkout_is_prepared,
339 .prepare = wm831x_clkout_prepare, 339 .prepare = wm831x_clkout_prepare,
340 .unprepare = wm831x_clkout_unprepare, 340 .unprepare = wm831x_clkout_unprepare,
341 .get_parent = wm831x_clkout_get_parent, 341 .get_parent = wm831x_clkout_get_parent,
@@ -360,6 +360,8 @@ static int wm831x_clk_probe(struct platform_device *pdev)
360 if (!clkdata) 360 if (!clkdata)
361 return -ENOMEM; 361 return -ENOMEM;
362 362
363 clkdata->wm831x = wm831x;
364
363 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */ 365 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
364 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); 366 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
365 if (ret < 0) { 367 if (ret < 0) {
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 54a191c5bbf0..a004769528e6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -458,7 +458,6 @@ static void clk_unprepare_unused_subtree(struct clk *clk)
458 clk->ops->unprepare(clk->hw); 458 clk->ops->unprepare(clk->hw);
459 } 459 }
460} 460}
461EXPORT_SYMBOL_GPL(__clk_get_flags);
462 461
463/* caller must hold prepare_lock */ 462/* caller must hold prepare_lock */
464static void clk_disable_unused_subtree(struct clk *clk) 463static void clk_disable_unused_subtree(struct clk *clk)
@@ -559,6 +558,19 @@ struct clk *__clk_get_parent(struct clk *clk)
559 return !clk ? NULL : clk->parent; 558 return !clk ? NULL : clk->parent;
560} 559}
561 560
561struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
562{
563 if (!clk || index >= clk->num_parents)
564 return NULL;
565 else if (!clk->parents)
566 return __clk_lookup(clk->parent_names[index]);
567 else if (!clk->parents[index])
568 return clk->parents[index] =
569 __clk_lookup(clk->parent_names[index]);
570 else
571 return clk->parents[index];
572}
573
562unsigned int __clk_get_enable_count(struct clk *clk) 574unsigned int __clk_get_enable_count(struct clk *clk)
563{ 575{
564 return !clk ? 0 : clk->enable_count; 576 return !clk ? 0 : clk->enable_count;
@@ -594,6 +606,7 @@ unsigned long __clk_get_flags(struct clk *clk)
594{ 606{
595 return !clk ? 0 : clk->flags; 607 return !clk ? 0 : clk->flags;
596} 608}
609EXPORT_SYMBOL_GPL(__clk_get_flags);
597 610
598bool __clk_is_prepared(struct clk *clk) 611bool __clk_is_prepared(struct clk *clk)
599{ 612{
@@ -679,6 +692,55 @@ struct clk *__clk_lookup(const char *name)
679 return NULL; 692 return NULL;
680} 693}
681 694
695/*
696 * Helper for finding best parent to provide a given frequency. This can be used
697 * directly as a determine_rate callback (e.g. for a mux), or from a more
698 * complex clock that may combine a mux with other operations.
699 */
700long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
701 unsigned long *best_parent_rate,
702 struct clk **best_parent_p)
703{
704 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
705 int i, num_parents;
706 unsigned long parent_rate, best = 0;
707
708 /* if NO_REPARENT flag set, pass through to current parent */
709 if (clk->flags & CLK_SET_RATE_NO_REPARENT) {
710 parent = clk->parent;
711 if (clk->flags & CLK_SET_RATE_PARENT)
712 best = __clk_round_rate(parent, rate);
713 else if (parent)
714 best = __clk_get_rate(parent);
715 else
716 best = __clk_get_rate(clk);
717 goto out;
718 }
719
720 /* find the parent that can provide the fastest rate <= rate */
721 num_parents = clk->num_parents;
722 for (i = 0; i < num_parents; i++) {
723 parent = clk_get_parent_by_index(clk, i);
724 if (!parent)
725 continue;
726 if (clk->flags & CLK_SET_RATE_PARENT)
727 parent_rate = __clk_round_rate(parent, rate);
728 else
729 parent_rate = __clk_get_rate(parent);
730 if (parent_rate <= rate && parent_rate > best) {
731 best_parent = parent;
732 best = parent_rate;
733 }
734 }
735
736out:
737 if (best_parent)
738 *best_parent_p = best_parent;
739 *best_parent_rate = best;
740
741 return best;
742}
743
682/*** clk api ***/ 744/*** clk api ***/
683 745
684void __clk_unprepare(struct clk *clk) 746void __clk_unprepare(struct clk *clk)
@@ -702,7 +764,7 @@ void __clk_unprepare(struct clk *clk)
702 764
703/** 765/**
704 * clk_unprepare - undo preparation of a clock source 766 * clk_unprepare - undo preparation of a clock source
705 * @clk: the clk being unprepare 767 * @clk: the clk being unprepared
706 * 768 *
707 * clk_unprepare may sleep, which differentiates it from clk_disable. In a 769 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
708 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk 770 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
@@ -869,27 +931,31 @@ EXPORT_SYMBOL_GPL(clk_enable);
869/** 931/**
870 * __clk_round_rate - round the given rate for a clk 932 * __clk_round_rate - round the given rate for a clk
871 * @clk: round the rate of this clock 933 * @clk: round the rate of this clock
934 * @rate: the rate which is to be rounded
872 * 935 *
873 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate 936 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate
874 */ 937 */
875unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) 938unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
876{ 939{
877 unsigned long parent_rate = 0; 940 unsigned long parent_rate = 0;
941 struct clk *parent;
878 942
879 if (!clk) 943 if (!clk)
880 return 0; 944 return 0;
881 945
882 if (!clk->ops->round_rate) { 946 parent = clk->parent;
883 if (clk->flags & CLK_SET_RATE_PARENT) 947 if (parent)
884 return __clk_round_rate(clk->parent, rate); 948 parent_rate = parent->rate;
885 else 949
886 return clk->rate; 950 if (clk->ops->determine_rate)
887 } 951 return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
888 952 &parent);
889 if (clk->parent) 953 else if (clk->ops->round_rate)
890 parent_rate = clk->parent->rate; 954 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
891 955 else if (clk->flags & CLK_SET_RATE_PARENT)
892 return clk->ops->round_rate(clk->hw, rate, &parent_rate); 956 return __clk_round_rate(clk->parent, rate);
957 else
958 return clk->rate;
893} 959}
894 960
895/** 961/**
@@ -956,7 +1022,7 @@ static int __clk_notify(struct clk *clk, unsigned long msg,
956 * 1022 *
957 * Walks the subtree of clks starting with clk and recalculates rates as it 1023 * Walks the subtree of clks starting with clk and recalculates rates as it
958 * goes. Note that if a clk does not implement the .recalc_rate callback then 1024 * goes. Note that if a clk does not implement the .recalc_rate callback then
959 * it is assumed that the clock will take on the rate of it's parent. 1025 * it is assumed that the clock will take on the rate of its parent.
960 * 1026 *
961 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification, 1027 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
962 * if necessary. 1028 * if necessary.
@@ -1014,6 +1080,115 @@ unsigned long clk_get_rate(struct clk *clk)
1014} 1080}
1015EXPORT_SYMBOL_GPL(clk_get_rate); 1081EXPORT_SYMBOL_GPL(clk_get_rate);
1016 1082
1083static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
1084{
1085 u8 i;
1086
1087 if (!clk->parents)
1088 clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
1089 GFP_KERNEL);
1090
1091 /*
1092 * find index of new parent clock using cached parent ptrs,
1093 * or if not yet cached, use string name comparison and cache
1094 * them now to avoid future calls to __clk_lookup.
1095 */
1096 for (i = 0; i < clk->num_parents; i++) {
1097 if (clk->parents && clk->parents[i] == parent)
1098 break;
1099 else if (!strcmp(clk->parent_names[i], parent->name)) {
1100 if (clk->parents)
1101 clk->parents[i] = __clk_lookup(parent->name);
1102 break;
1103 }
1104 }
1105
1106 return i;
1107}
1108
1109static void clk_reparent(struct clk *clk, struct clk *new_parent)
1110{
1111 hlist_del(&clk->child_node);
1112
1113 if (new_parent) {
1114 /* avoid duplicate POST_RATE_CHANGE notifications */
1115 if (new_parent->new_child == clk)
1116 new_parent->new_child = NULL;
1117
1118 hlist_add_head(&clk->child_node, &new_parent->children);
1119 } else {
1120 hlist_add_head(&clk->child_node, &clk_orphan_list);
1121 }
1122
1123 clk->parent = new_parent;
1124}
1125
1126static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1127{
1128 unsigned long flags;
1129 int ret = 0;
1130 struct clk *old_parent = clk->parent;
1131
1132 /*
1133 * Migrate prepare state between parents and prevent race with
1134 * clk_enable().
1135 *
1136 * If the clock is not prepared, then a race with
1137 * clk_enable/disable() is impossible since we already have the
1138 * prepare lock (future calls to clk_enable() need to be preceded by
1139 * a clk_prepare()).
1140 *
1141 * If the clock is prepared, migrate the prepared state to the new
1142 * parent and also protect against a race with clk_enable() by
1143 * forcing the clock and the new parent on. This ensures that all
1144 * future calls to clk_enable() are practically NOPs with respect to
1145 * hardware and software states.
1146 *
1147 * See also: Comment for clk_set_parent() below.
1148 */
1149 if (clk->prepare_count) {
1150 __clk_prepare(parent);
1151 clk_enable(parent);
1152 clk_enable(clk);
1153 }
1154
1155 /* update the clk tree topology */
1156 flags = clk_enable_lock();
1157 clk_reparent(clk, parent);
1158 clk_enable_unlock(flags);
1159
1160 /* change clock input source */
1161 if (parent && clk->ops->set_parent)
1162 ret = clk->ops->set_parent(clk->hw, p_index);
1163
1164 if (ret) {
1165 flags = clk_enable_lock();
1166 clk_reparent(clk, old_parent);
1167 clk_enable_unlock(flags);
1168
1169 if (clk->prepare_count) {
1170 clk_disable(clk);
1171 clk_disable(parent);
1172 __clk_unprepare(parent);
1173 }
1174 return ret;
1175 }
1176
1177 /*
1178 * Finish the migration of prepare state and undo the changes done
1179 * for preventing a race with clk_enable().
1180 */
1181 if (clk->prepare_count) {
1182 clk_disable(clk);
1183 clk_disable(old_parent);
1184 __clk_unprepare(old_parent);
1185 }
1186
1187 /* update debugfs with new clk tree topology */
1188 clk_debug_reparent(clk, parent);
1189 return 0;
1190}
1191
1017/** 1192/**
1018 * __clk_speculate_rates 1193 * __clk_speculate_rates
1019 * @clk: first clk in the subtree 1194 * @clk: first clk in the subtree
@@ -1026,7 +1201,7 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
1026 * pre-rate change notifications and returns early if no clks in the 1201 * pre-rate change notifications and returns early if no clks in the
1027 * subtree have subscribed to the notifications. Note that if a clk does not 1202 * subtree have subscribed to the notifications. Note that if a clk does not
1028 * implement the .recalc_rate callback then it is assumed that the clock will 1203 * implement the .recalc_rate callback then it is assumed that the clock will
1029 * take on the rate of it's parent. 1204 * take on the rate of its parent.
1030 * 1205 *
1031 * Caller must hold prepare_lock. 1206 * Caller must hold prepare_lock.
1032 */ 1207 */
@@ -1058,18 +1233,25 @@ out:
1058 return ret; 1233 return ret;
1059} 1234}
1060 1235
1061static void clk_calc_subtree(struct clk *clk, unsigned long new_rate) 1236static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
1237 struct clk *new_parent, u8 p_index)
1062{ 1238{
1063 struct clk *child; 1239 struct clk *child;
1064 1240
1065 clk->new_rate = new_rate; 1241 clk->new_rate = new_rate;
1242 clk->new_parent = new_parent;
1243 clk->new_parent_index = p_index;
1244 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1245 clk->new_child = NULL;
1246 if (new_parent && new_parent != clk->parent)
1247 new_parent->new_child = clk;
1066 1248
1067 hlist_for_each_entry(child, &clk->children, child_node) { 1249 hlist_for_each_entry(child, &clk->children, child_node) {
1068 if (child->ops->recalc_rate) 1250 if (child->ops->recalc_rate)
1069 child->new_rate = child->ops->recalc_rate(child->hw, new_rate); 1251 child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
1070 else 1252 else
1071 child->new_rate = new_rate; 1253 child->new_rate = new_rate;
1072 clk_calc_subtree(child, child->new_rate); 1254 clk_calc_subtree(child, child->new_rate, NULL, 0);
1073 } 1255 }
1074} 1256}
1075 1257
@@ -1080,50 +1262,63 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
1080static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate) 1262static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
1081{ 1263{
1082 struct clk *top = clk; 1264 struct clk *top = clk;
1265 struct clk *old_parent, *parent;
1083 unsigned long best_parent_rate = 0; 1266 unsigned long best_parent_rate = 0;
1084 unsigned long new_rate; 1267 unsigned long new_rate;
1268 u8 p_index = 0;
1085 1269
1086 /* sanity */ 1270 /* sanity */
1087 if (IS_ERR_OR_NULL(clk)) 1271 if (IS_ERR_OR_NULL(clk))
1088 return NULL; 1272 return NULL;
1089 1273
1090 /* save parent rate, if it exists */ 1274 /* save parent rate, if it exists */
1091 if (clk->parent) 1275 parent = old_parent = clk->parent;
1092 best_parent_rate = clk->parent->rate; 1276 if (parent)
1093 1277 best_parent_rate = parent->rate;
1094 /* never propagate up to the parent */ 1278
1095 if (!(clk->flags & CLK_SET_RATE_PARENT)) { 1279 /* find the closest rate and parent clk/rate */
1096 if (!clk->ops->round_rate) { 1280 if (clk->ops->determine_rate) {
1097 clk->new_rate = clk->rate; 1281 new_rate = clk->ops->determine_rate(clk->hw, rate,
1098 return NULL; 1282 &best_parent_rate,
1099 } 1283 &parent);
1100 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate); 1284 } else if (clk->ops->round_rate) {
1285 new_rate = clk->ops->round_rate(clk->hw, rate,
1286 &best_parent_rate);
1287 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
1288 /* pass-through clock without adjustable parent */
1289 clk->new_rate = clk->rate;
1290 return NULL;
1291 } else {
1292 /* pass-through clock with adjustable parent */
1293 top = clk_calc_new_rates(parent, rate);
1294 new_rate = parent->new_rate;
1101 goto out; 1295 goto out;
1102 } 1296 }
1103 1297
1104 /* need clk->parent from here on out */ 1298 /* some clocks must be gated to change parent */
1105 if (!clk->parent) { 1299 if (parent != old_parent &&
1106 pr_debug("%s: %s has NULL parent\n", __func__, clk->name); 1300 (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
1301 pr_debug("%s: %s not gated but wants to reparent\n",
1302 __func__, clk->name);
1107 return NULL; 1303 return NULL;
1108 } 1304 }
1109 1305
1110 if (!clk->ops->round_rate) { 1306 /* try finding the new parent index */
1111 top = clk_calc_new_rates(clk->parent, rate); 1307 if (parent) {
1112 new_rate = clk->parent->new_rate; 1308 p_index = clk_fetch_parent_index(clk, parent);
1113 1309 if (p_index == clk->num_parents) {
1114 goto out; 1310 pr_debug("%s: clk %s can not be parent of clk %s\n",
1311 __func__, parent->name, clk->name);
1312 return NULL;
1313 }
1115 } 1314 }
1116 1315
1117 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate); 1316 if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
1118 1317 best_parent_rate != parent->rate)
1119 if (best_parent_rate != clk->parent->rate) { 1318 top = clk_calc_new_rates(parent, best_parent_rate);
1120 top = clk_calc_new_rates(clk->parent, best_parent_rate);
1121
1122 goto out;
1123 }
1124 1319
1125out: 1320out:
1126 clk_calc_subtree(clk, new_rate); 1321 clk_calc_subtree(clk, new_rate, parent, p_index);
1127 1322
1128 return top; 1323 return top;
1129} 1324}
@@ -1135,7 +1330,7 @@ out:
1135 */ 1330 */
1136static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event) 1331static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
1137{ 1332{
1138 struct clk *child, *fail_clk = NULL; 1333 struct clk *child, *tmp_clk, *fail_clk = NULL;
1139 int ret = NOTIFY_DONE; 1334 int ret = NOTIFY_DONE;
1140 1335
1141 if (clk->rate == clk->new_rate) 1336 if (clk->rate == clk->new_rate)
@@ -1148,9 +1343,19 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
1148 } 1343 }
1149 1344
1150 hlist_for_each_entry(child, &clk->children, child_node) { 1345 hlist_for_each_entry(child, &clk->children, child_node) {
1151 clk = clk_propagate_rate_change(child, event); 1346 /* Skip children who will be reparented to another clock */
1152 if (clk) 1347 if (child->new_parent && child->new_parent != clk)
1153 fail_clk = clk; 1348 continue;
1349 tmp_clk = clk_propagate_rate_change(child, event);
1350 if (tmp_clk)
1351 fail_clk = tmp_clk;
1352 }
1353
1354 /* handle the new child who might not be in clk->children yet */
1355 if (clk->new_child) {
1356 tmp_clk = clk_propagate_rate_change(clk->new_child, event);
1357 if (tmp_clk)
1358 fail_clk = tmp_clk;
1154 } 1359 }
1155 1360
1156 return fail_clk; 1361 return fail_clk;
@@ -1168,6 +1373,10 @@ static void clk_change_rate(struct clk *clk)
1168 1373
1169 old_rate = clk->rate; 1374 old_rate = clk->rate;
1170 1375
1376 /* set parent */
1377 if (clk->new_parent && clk->new_parent != clk->parent)
1378 __clk_set_parent(clk, clk->new_parent, clk->new_parent_index);
1379
1171 if (clk->parent) 1380 if (clk->parent)
1172 best_parent_rate = clk->parent->rate; 1381 best_parent_rate = clk->parent->rate;
1173 1382
@@ -1182,8 +1391,16 @@ static void clk_change_rate(struct clk *clk)
1182 if (clk->notifier_count && old_rate != clk->rate) 1391 if (clk->notifier_count && old_rate != clk->rate)
1183 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); 1392 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
1184 1393
1185 hlist_for_each_entry(child, &clk->children, child_node) 1394 hlist_for_each_entry(child, &clk->children, child_node) {
1395 /* Skip children who will be reparented to another clock */
1396 if (child->new_parent && child->new_parent != clk)
1397 continue;
1186 clk_change_rate(child); 1398 clk_change_rate(child);
1399 }
1400
1401 /* handle the new child who might not be in clk->children yet */
1402 if (clk->new_child)
1403 clk_change_rate(clk->new_child);
1187} 1404}
1188 1405
1189/** 1406/**
@@ -1198,7 +1415,7 @@ static void clk_change_rate(struct clk *clk)
1198 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged 1415 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1199 * after calling .round_rate then upstream parent propagation is ignored. If 1416 * after calling .round_rate then upstream parent propagation is ignored. If
1200 * *parent_rate comes back with a new rate for clk's parent then we propagate 1417 * *parent_rate comes back with a new rate for clk's parent then we propagate
1201 * up to clk's parent and set it's rate. Upward propagation will continue 1418 * up to clk's parent and set its rate. Upward propagation will continue
1202 * until either a clk does not support the CLK_SET_RATE_PARENT flag or 1419 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1203 * .round_rate stops requesting changes to clk's parent_rate. 1420 * .round_rate stops requesting changes to clk's parent_rate.
1204 * 1421 *
@@ -1212,6 +1429,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
1212 struct clk *top, *fail_clk; 1429 struct clk *top, *fail_clk;
1213 int ret = 0; 1430 int ret = 0;
1214 1431
1432 if (!clk)
1433 return 0;
1434
1215 /* prevent racing with updates to the clock topology */ 1435 /* prevent racing with updates to the clock topology */
1216 clk_prepare_lock(); 1436 clk_prepare_lock();
1217 1437
@@ -1315,30 +1535,12 @@ static struct clk *__clk_init_parent(struct clk *clk)
1315 kzalloc((sizeof(struct clk*) * clk->num_parents), 1535 kzalloc((sizeof(struct clk*) * clk->num_parents),
1316 GFP_KERNEL); 1536 GFP_KERNEL);
1317 1537
1318 if (!clk->parents) 1538 ret = clk_get_parent_by_index(clk, index);
1319 ret = __clk_lookup(clk->parent_names[index]);
1320 else if (!clk->parents[index])
1321 ret = clk->parents[index] =
1322 __clk_lookup(clk->parent_names[index]);
1323 else
1324 ret = clk->parents[index];
1325 1539
1326out: 1540out:
1327 return ret; 1541 return ret;
1328} 1542}
1329 1543
1330static void clk_reparent(struct clk *clk, struct clk *new_parent)
1331{
1332 hlist_del(&clk->child_node);
1333
1334 if (new_parent)
1335 hlist_add_head(&clk->child_node, &new_parent->children);
1336 else
1337 hlist_add_head(&clk->child_node, &clk_orphan_list);
1338
1339 clk->parent = new_parent;
1340}
1341
1342void __clk_reparent(struct clk *clk, struct clk *new_parent) 1544void __clk_reparent(struct clk *clk, struct clk *new_parent)
1343{ 1545{
1344 clk_reparent(clk, new_parent); 1546 clk_reparent(clk, new_parent);
@@ -1346,98 +1548,6 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
1346 __clk_recalc_rates(clk, POST_RATE_CHANGE); 1548 __clk_recalc_rates(clk, POST_RATE_CHANGE);
1347} 1549}
1348 1550
1349static u8 clk_fetch_parent_index(struct clk *clk, struct clk *parent)
1350{
1351 u8 i;
1352
1353 if (!clk->parents)
1354 clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
1355 GFP_KERNEL);
1356
1357 /*
1358 * find index of new parent clock using cached parent ptrs,
1359 * or if not yet cached, use string name comparison and cache
1360 * them now to avoid future calls to __clk_lookup.
1361 */
1362 for (i = 0; i < clk->num_parents; i++) {
1363 if (clk->parents && clk->parents[i] == parent)
1364 break;
1365 else if (!strcmp(clk->parent_names[i], parent->name)) {
1366 if (clk->parents)
1367 clk->parents[i] = __clk_lookup(parent->name);
1368 break;
1369 }
1370 }
1371
1372 return i;
1373}
1374
1375static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1376{
1377 unsigned long flags;
1378 int ret = 0;
1379 struct clk *old_parent = clk->parent;
1380
1381 /*
1382 * Migrate prepare state between parents and prevent race with
1383 * clk_enable().
1384 *
1385 * If the clock is not prepared, then a race with
1386 * clk_enable/disable() is impossible since we already have the
1387 * prepare lock (future calls to clk_enable() need to be preceded by
1388 * a clk_prepare()).
1389 *
1390 * If the clock is prepared, migrate the prepared state to the new
1391 * parent and also protect against a race with clk_enable() by
1392 * forcing the clock and the new parent on. This ensures that all
1393 * future calls to clk_enable() are practically NOPs with respect to
1394 * hardware and software states.
1395 *
1396 * See also: Comment for clk_set_parent() below.
1397 */
1398 if (clk->prepare_count) {
1399 __clk_prepare(parent);
1400 clk_enable(parent);
1401 clk_enable(clk);
1402 }
1403
1404 /* update the clk tree topology */
1405 flags = clk_enable_lock();
1406 clk_reparent(clk, parent);
1407 clk_enable_unlock(flags);
1408
1409 /* change clock input source */
1410 if (parent && clk->ops->set_parent)
1411 ret = clk->ops->set_parent(clk->hw, p_index);
1412
1413 if (ret) {
1414 flags = clk_enable_lock();
1415 clk_reparent(clk, old_parent);
1416 clk_enable_unlock(flags);
1417
1418 if (clk->prepare_count) {
1419 clk_disable(clk);
1420 clk_disable(parent);
1421 __clk_unprepare(parent);
1422 }
1423 return ret;
1424 }
1425
1426 /*
1427 * Finish the migration of prepare state and undo the changes done
1428 * for preventing a race with clk_enable().
1429 */
1430 if (clk->prepare_count) {
1431 clk_disable(clk);
1432 clk_disable(old_parent);
1433 __clk_unprepare(old_parent);
1434 }
1435
1436 /* update debugfs with new clk tree topology */
1437 clk_debug_reparent(clk, parent);
1438 return 0;
1439}
1440
1441/** 1551/**
1442 * clk_set_parent - switch the parent of a mux clk 1552 * clk_set_parent - switch the parent of a mux clk
1443 * @clk: the mux clk whose input we are switching 1553 * @clk: the mux clk whose input we are switching
@@ -1461,7 +1571,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
1461 u8 p_index = 0; 1571 u8 p_index = 0;
1462 unsigned long p_rate = 0; 1572 unsigned long p_rate = 0;
1463 1573
1464 if (!clk || !clk->ops) 1574 if (!clk)
1575 return 0;
1576
1577 if (!clk->ops)
1465 return -EINVAL; 1578 return -EINVAL;
1466 1579
1467 /* verify ops for for multi-parent clks */ 1580 /* verify ops for for multi-parent clks */
@@ -1544,8 +1657,9 @@ int __clk_init(struct device *dev, struct clk *clk)
1544 1657
1545 /* check that clk_ops are sane. See Documentation/clk.txt */ 1658 /* check that clk_ops are sane. See Documentation/clk.txt */
1546 if (clk->ops->set_rate && 1659 if (clk->ops->set_rate &&
1547 !(clk->ops->round_rate && clk->ops->recalc_rate)) { 1660 !((clk->ops->round_rate || clk->ops->determine_rate) &&
1548 pr_warning("%s: %s must implement .round_rate & .recalc_rate\n", 1661 clk->ops->recalc_rate)) {
1662 pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
1549 __func__, clk->name); 1663 __func__, clk->name);
1550 ret = -EINVAL; 1664 ret = -EINVAL;
1551 goto out; 1665 goto out;
@@ -1628,7 +1742,7 @@ int __clk_init(struct device *dev, struct clk *clk)
1628 * this clock 1742 * this clock
1629 */ 1743 */
1630 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) { 1744 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
1631 if (orphan->ops->get_parent) { 1745 if (orphan->num_parents && orphan->ops->get_parent) {
1632 i = orphan->ops->get_parent(orphan->hw); 1746 i = orphan->ops->get_parent(orphan->hw);
1633 if (!strcmp(clk->name, orphan->parent_names[i])) 1747 if (!strcmp(clk->name, orphan->parent_names[i]))
1634 __clk_reparent(orphan, clk); 1748 __clk_reparent(orphan, clk);
@@ -1648,7 +1762,7 @@ int __clk_init(struct device *dev, struct clk *clk)
1648 * The .init callback is not used by any of the basic clock types, but 1762 * The .init callback is not used by any of the basic clock types, but
1649 * exists for weird hardware that must perform initialization magic. 1763 * exists for weird hardware that must perform initialization magic.
1650 * Please consider other ways of solving initialization problems before 1764 * Please consider other ways of solving initialization problems before
1651 * using this callback, as it's use is discouraged. 1765 * using this callback, as its use is discouraged.
1652 */ 1766 */
1653 if (clk->ops->init) 1767 if (clk->ops->init)
1654 clk->ops->init(clk->hw); 1768 clk->ops->init(clk->hw);
@@ -1675,7 +1789,7 @@ out:
1675 * very large numbers of clocks that need to be statically initialized. It is 1789 * very large numbers of clocks that need to be statically initialized. It is
1676 * a layering violation to include clk-private.h from any code which implements 1790 * a layering violation to include clk-private.h from any code which implements
1677 * a clock's .ops; as such any statically initialized clock data MUST be in a 1791 * a clock's .ops; as such any statically initialized clock data MUST be in a
1678 * separate C file from the logic that implements it's operations. Returns 0 1792 * separate C file from the logic that implements its operations. Returns 0
1679 * on success, otherwise an error code. 1793 * on success, otherwise an error code.
1680 */ 1794 */
1681struct clk *__clk_register(struct device *dev, struct clk_hw *hw) 1795struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
@@ -2115,13 +2229,13 @@ EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
2115 */ 2229 */
2116void __init of_clk_init(const struct of_device_id *matches) 2230void __init of_clk_init(const struct of_device_id *matches)
2117{ 2231{
2232 const struct of_device_id *match;
2118 struct device_node *np; 2233 struct device_node *np;
2119 2234
2120 if (!matches) 2235 if (!matches)
2121 matches = __clk_of_table; 2236 matches = __clk_of_table;
2122 2237
2123 for_each_matching_node(np, matches) { 2238 for_each_matching_node_and_match(np, matches, &match) {
2124 const struct of_device_id *match = of_match_node(matches, np);
2125 of_clk_init_cb_t clk_init_cb = match->data; 2239 of_clk_init_cb_t clk_init_cb = match->data;
2126 clk_init_cb(np); 2240 clk_init_cb(np);
2127 } 2241 }
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index d1f1a19d4351..b2721cae257a 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -248,7 +248,8 @@ void __init mmp2_clk_init(void)
248 clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); 248 clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
249 249
250 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 250 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
251 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 251 ARRAY_SIZE(uart_parent),
252 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
252 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 253 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
253 clk_set_parent(clk, vctcxo); 254 clk_set_parent(clk, vctcxo);
254 clk_register_clkdev(clk, "uart_mux.0", NULL); 255 clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -258,7 +259,8 @@ void __init mmp2_clk_init(void)
258 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 259 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
259 260
260 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 261 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
261 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 262 ARRAY_SIZE(uart_parent),
263 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
262 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 264 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
263 clk_set_parent(clk, vctcxo); 265 clk_set_parent(clk, vctcxo);
264 clk_register_clkdev(clk, "uart_mux.1", NULL); 266 clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -268,7 +270,8 @@ void __init mmp2_clk_init(void)
268 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 270 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
269 271
270 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 272 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
271 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 273 ARRAY_SIZE(uart_parent),
274 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
272 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); 275 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
273 clk_set_parent(clk, vctcxo); 276 clk_set_parent(clk, vctcxo);
274 clk_register_clkdev(clk, "uart_mux.2", NULL); 277 clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -278,7 +281,8 @@ void __init mmp2_clk_init(void)
278 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 281 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
279 282
280 clk = clk_register_mux(NULL, "uart3_mux", uart_parent, 283 clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
281 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 284 ARRAY_SIZE(uart_parent),
285 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
282 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); 286 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
283 clk_set_parent(clk, vctcxo); 287 clk_set_parent(clk, vctcxo);
284 clk_register_clkdev(clk, "uart_mux.3", NULL); 288 clk_register_clkdev(clk, "uart_mux.3", NULL);
@@ -288,7 +292,8 @@ void __init mmp2_clk_init(void)
288 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); 292 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
289 293
290 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 294 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
291 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 295 ARRAY_SIZE(ssp_parent),
296 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
292 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 297 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
293 clk_register_clkdev(clk, "uart_mux.0", NULL); 298 clk_register_clkdev(clk, "uart_mux.0", NULL);
294 299
@@ -297,7 +302,8 @@ void __init mmp2_clk_init(void)
297 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 302 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
298 303
299 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 304 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
300 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 305 ARRAY_SIZE(ssp_parent),
306 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
301 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 307 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
302 clk_register_clkdev(clk, "ssp_mux.1", NULL); 308 clk_register_clkdev(clk, "ssp_mux.1", NULL);
303 309
@@ -306,7 +312,8 @@ void __init mmp2_clk_init(void)
306 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 312 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
307 313
308 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, 314 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
309 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 315 ARRAY_SIZE(ssp_parent),
316 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
310 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); 317 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
311 clk_register_clkdev(clk, "ssp_mux.2", NULL); 318 clk_register_clkdev(clk, "ssp_mux.2", NULL);
312 319
@@ -315,7 +322,8 @@ void __init mmp2_clk_init(void)
315 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); 322 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
316 323
317 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, 324 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
318 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 325 ARRAY_SIZE(ssp_parent),
326 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
319 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); 327 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
320 clk_register_clkdev(clk, "ssp_mux.3", NULL); 328 clk_register_clkdev(clk, "ssp_mux.3", NULL);
321 329
@@ -324,7 +332,8 @@ void __init mmp2_clk_init(void)
324 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); 332 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
325 333
326 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, 334 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
327 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 335 ARRAY_SIZE(sdh_parent),
336 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
328 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); 337 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
329 clk_register_clkdev(clk, "sdh_mux", NULL); 338 clk_register_clkdev(clk, "sdh_mux", NULL);
330 339
@@ -354,7 +363,8 @@ void __init mmp2_clk_init(void)
354 clk_register_clkdev(clk, "usb_clk", NULL); 363 clk_register_clkdev(clk, "usb_clk", NULL);
355 364
356 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 365 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
357 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 366 ARRAY_SIZE(disp_parent),
367 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
358 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); 368 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
359 clk_register_clkdev(clk, "disp_mux.0", NULL); 369 clk_register_clkdev(clk, "disp_mux.0", NULL);
360 370
@@ -376,7 +386,8 @@ void __init mmp2_clk_init(void)
376 clk_register_clkdev(clk, "disp_sphy.0", NULL); 386 clk_register_clkdev(clk, "disp_sphy.0", NULL);
377 387
378 clk = clk_register_mux(NULL, "disp1_mux", disp_parent, 388 clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
379 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 389 ARRAY_SIZE(disp_parent),
390 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
380 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); 391 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
381 clk_register_clkdev(clk, "disp_mux.1", NULL); 392 clk_register_clkdev(clk, "disp_mux.1", NULL);
382 393
@@ -394,7 +405,8 @@ void __init mmp2_clk_init(void)
394 clk_register_clkdev(clk, "ccic_arbiter", NULL); 405 clk_register_clkdev(clk, "ccic_arbiter", NULL);
395 406
396 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 407 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
397 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 408 ARRAY_SIZE(ccic_parent),
409 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
398 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); 410 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
399 clk_register_clkdev(clk, "ccic_mux.0", NULL); 411 clk_register_clkdev(clk, "ccic_mux.0", NULL);
400 412
@@ -421,7 +433,8 @@ void __init mmp2_clk_init(void)
421 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); 433 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
422 434
423 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, 435 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
424 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 436 ARRAY_SIZE(ccic_parent),
437 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
425 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); 438 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
426 clk_register_clkdev(clk, "ccic_mux.1", NULL); 439 clk_register_clkdev(clk, "ccic_mux.1", NULL);
427 440
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 28b3b51c794b..014396b028a2 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -199,7 +199,8 @@ void __init pxa168_clk_init(void)
199 clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); 199 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
200 200
201 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 201 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
202 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 202 ARRAY_SIZE(uart_parent),
203 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
203 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 204 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
204 clk_set_parent(clk, uart_pll); 205 clk_set_parent(clk, uart_pll);
205 clk_register_clkdev(clk, "uart_mux.0", NULL); 206 clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -209,7 +210,8 @@ void __init pxa168_clk_init(void)
209 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 210 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
210 211
211 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 212 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
212 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 213 ARRAY_SIZE(uart_parent),
214 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
213 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 215 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
214 clk_set_parent(clk, uart_pll); 216 clk_set_parent(clk, uart_pll);
215 clk_register_clkdev(clk, "uart_mux.1", NULL); 217 clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -219,7 +221,8 @@ void __init pxa168_clk_init(void)
219 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 221 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
220 222
221 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 223 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
222 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 224 ARRAY_SIZE(uart_parent),
225 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
223 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); 226 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
224 clk_set_parent(clk, uart_pll); 227 clk_set_parent(clk, uart_pll);
225 clk_register_clkdev(clk, "uart_mux.2", NULL); 228 clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -229,7 +232,8 @@ void __init pxa168_clk_init(void)
229 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 232 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
230 233
231 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 234 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
232 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 235 ARRAY_SIZE(ssp_parent),
236 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
233 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 237 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
234 clk_register_clkdev(clk, "uart_mux.0", NULL); 238 clk_register_clkdev(clk, "uart_mux.0", NULL);
235 239
@@ -238,7 +242,8 @@ void __init pxa168_clk_init(void)
238 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 242 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
239 243
240 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 244 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
241 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 245 ARRAY_SIZE(ssp_parent),
246 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
242 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 247 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
243 clk_register_clkdev(clk, "ssp_mux.1", NULL); 248 clk_register_clkdev(clk, "ssp_mux.1", NULL);
244 249
@@ -247,7 +252,8 @@ void __init pxa168_clk_init(void)
247 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 252 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
248 253
249 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, 254 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
250 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 255 ARRAY_SIZE(ssp_parent),
256 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
251 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); 257 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
252 clk_register_clkdev(clk, "ssp_mux.2", NULL); 258 clk_register_clkdev(clk, "ssp_mux.2", NULL);
253 259
@@ -256,7 +262,8 @@ void __init pxa168_clk_init(void)
256 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); 262 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
257 263
258 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, 264 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
259 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 265 ARRAY_SIZE(ssp_parent),
266 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
260 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); 267 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
261 clk_register_clkdev(clk, "ssp_mux.3", NULL); 268 clk_register_clkdev(clk, "ssp_mux.3", NULL);
262 269
@@ -265,7 +272,8 @@ void __init pxa168_clk_init(void)
265 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); 272 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
266 273
267 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, 274 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
268 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 275 ARRAY_SIZE(ssp_parent),
276 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
269 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); 277 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
270 clk_register_clkdev(clk, "ssp_mux.4", NULL); 278 clk_register_clkdev(clk, "ssp_mux.4", NULL);
271 279
@@ -278,7 +286,8 @@ void __init pxa168_clk_init(void)
278 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); 286 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
279 287
280 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, 288 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
281 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 289 ARRAY_SIZE(sdh_parent),
290 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
282 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); 291 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
283 clk_register_clkdev(clk, "sdh0_mux", NULL); 292 clk_register_clkdev(clk, "sdh0_mux", NULL);
284 293
@@ -287,7 +296,8 @@ void __init pxa168_clk_init(void)
287 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); 296 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
288 297
289 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, 298 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
290 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 299 ARRAY_SIZE(sdh_parent),
300 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
291 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); 301 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
292 clk_register_clkdev(clk, "sdh1_mux", NULL); 302 clk_register_clkdev(clk, "sdh1_mux", NULL);
293 303
@@ -304,7 +314,8 @@ void __init pxa168_clk_init(void)
304 clk_register_clkdev(clk, "sph_clk", NULL); 314 clk_register_clkdev(clk, "sph_clk", NULL);
305 315
306 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 316 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
307 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 317 ARRAY_SIZE(disp_parent),
318 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
308 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); 319 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
309 clk_register_clkdev(clk, "disp_mux.0", NULL); 320 clk_register_clkdev(clk, "disp_mux.0", NULL);
310 321
@@ -317,7 +328,8 @@ void __init pxa168_clk_init(void)
317 clk_register_clkdev(clk, "hclk", "mmp-disp.0"); 328 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
318 329
319 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 330 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
320 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 331 ARRAY_SIZE(ccic_parent),
332 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
321 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); 333 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
322 clk_register_clkdev(clk, "ccic_mux.0", NULL); 334 clk_register_clkdev(clk, "ccic_mux.0", NULL);
323 335
@@ -327,8 +339,8 @@ void __init pxa168_clk_init(void)
327 339
328 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, 340 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
329 ARRAY_SIZE(ccic_phy_parent), 341 ARRAY_SIZE(ccic_phy_parent),
330 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 342 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
331 7, 1, 0, &clk_lock); 343 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
332 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); 344 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
333 345
334 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", 346 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 6ec05698ed38..9efc6a47535d 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -204,7 +204,8 @@ void __init pxa910_clk_init(void)
204 clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); 204 clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
205 205
206 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 206 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
207 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 207 ARRAY_SIZE(uart_parent),
208 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
208 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 209 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
209 clk_set_parent(clk, uart_pll); 210 clk_set_parent(clk, uart_pll);
210 clk_register_clkdev(clk, "uart_mux.0", NULL); 211 clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -214,7 +215,8 @@ void __init pxa910_clk_init(void)
214 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 215 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
215 216
216 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 217 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
217 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 218 ARRAY_SIZE(uart_parent),
219 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
218 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 220 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
219 clk_set_parent(clk, uart_pll); 221 clk_set_parent(clk, uart_pll);
220 clk_register_clkdev(clk, "uart_mux.1", NULL); 222 clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -224,7 +226,8 @@ void __init pxa910_clk_init(void)
224 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 226 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
225 227
226 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 228 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
227 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 229 ARRAY_SIZE(uart_parent),
230 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
228 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); 231 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
229 clk_set_parent(clk, uart_pll); 232 clk_set_parent(clk, uart_pll);
230 clk_register_clkdev(clk, "uart_mux.2", NULL); 233 clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -234,7 +237,8 @@ void __init pxa910_clk_init(void)
234 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 237 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
235 238
236 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 239 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
237 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 240 ARRAY_SIZE(ssp_parent),
241 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 242 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
239 clk_register_clkdev(clk, "uart_mux.0", NULL); 243 clk_register_clkdev(clk, "uart_mux.0", NULL);
240 244
@@ -243,7 +247,8 @@ void __init pxa910_clk_init(void)
243 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 247 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
244 248
245 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 249 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
246 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 250 ARRAY_SIZE(ssp_parent),
251 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
247 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 252 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
248 clk_register_clkdev(clk, "ssp_mux.1", NULL); 253 clk_register_clkdev(clk, "ssp_mux.1", NULL);
249 254
@@ -256,7 +261,8 @@ void __init pxa910_clk_init(void)
256 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); 261 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
257 262
258 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, 263 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
259 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 264 ARRAY_SIZE(sdh_parent),
265 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
260 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); 266 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
261 clk_register_clkdev(clk, "sdh0_mux", NULL); 267 clk_register_clkdev(clk, "sdh0_mux", NULL);
262 268
@@ -265,7 +271,8 @@ void __init pxa910_clk_init(void)
265 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); 271 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
266 272
267 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, 273 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
268 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 274 ARRAY_SIZE(sdh_parent),
275 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
269 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); 276 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
270 clk_register_clkdev(clk, "sdh1_mux", NULL); 277 clk_register_clkdev(clk, "sdh1_mux", NULL);
271 278
@@ -282,7 +289,8 @@ void __init pxa910_clk_init(void)
282 clk_register_clkdev(clk, "sph_clk", NULL); 289 clk_register_clkdev(clk, "sph_clk", NULL);
283 290
284 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 291 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
285 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 292 ARRAY_SIZE(disp_parent),
293 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
286 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); 294 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
287 clk_register_clkdev(clk, "disp_mux.0", NULL); 295 clk_register_clkdev(clk, "disp_mux.0", NULL);
288 296
@@ -291,7 +299,8 @@ void __init pxa910_clk_init(void)
291 clk_register_clkdev(clk, NULL, "mmp-disp.0"); 299 clk_register_clkdev(clk, NULL, "mmp-disp.0");
292 300
293 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 301 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
294 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 302 ARRAY_SIZE(ccic_parent),
303 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
295 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); 304 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
296 clk_register_clkdev(clk, "ccic_mux.0", NULL); 305 clk_register_clkdev(clk, "ccic_mux.0", NULL);
297 306
@@ -301,8 +310,8 @@ void __init pxa910_clk_init(void)
301 310
302 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, 311 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
303 ARRAY_SIZE(ccic_phy_parent), 312 ARRAY_SIZE(ccic_phy_parent),
304 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 313 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
305 7, 1, 0, &clk_lock); 314 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
306 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); 315 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
307 316
308 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", 317 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
index 079960e7c304..fc777bdc1886 100644
--- a/drivers/clk/mvebu/armada-370.c
+++ b/drivers/clk/mvebu/armada-370.c
@@ -32,13 +32,13 @@
32 32
33enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK }; 33enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
34 34
35static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = { 35static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = {
36 { .id = A370_CPU_TO_NBCLK, .name = "nbclk" }, 36 { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
37 { .id = A370_CPU_TO_HCLK, .name = "hclk" }, 37 { .id = A370_CPU_TO_HCLK, .name = "hclk" },
38 { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" }, 38 { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
39}; 39};
40 40
41static const u32 __initconst a370_tclk_freqs[] = { 41static const u32 a370_tclk_freqs[] __initconst = {
42 16600000, 42 16600000,
43 20000000, 43 20000000,
44}; 44};
@@ -52,7 +52,7 @@ static u32 __init a370_get_tclk_freq(void __iomem *sar)
52 return a370_tclk_freqs[tclk_freq_select]; 52 return a370_tclk_freqs[tclk_freq_select];
53} 53}
54 54
55static const u32 __initconst a370_cpu_freqs[] = { 55static const u32 a370_cpu_freqs[] __initconst = {
56 400000000, 56 400000000,
57 533000000, 57 533000000,
58 667000000, 58 667000000,
@@ -78,7 +78,7 @@ static u32 __init a370_get_cpu_freq(void __iomem *sar)
78 return cpu_freq; 78 return cpu_freq;
79} 79}
80 80
81static const int __initconst a370_nbclk_ratios[32][2] = { 81static const int a370_nbclk_ratios[32][2] __initconst = {
82 {0, 1}, {1, 2}, {2, 2}, {2, 2}, 82 {0, 1}, {1, 2}, {2, 2}, {2, 2},
83 {1, 2}, {1, 2}, {1, 1}, {2, 3}, 83 {1, 2}, {1, 2}, {1, 1}, {2, 3},
84 {0, 1}, {1, 2}, {2, 4}, {0, 1}, 84 {0, 1}, {1, 2}, {2, 4}, {0, 1},
@@ -89,7 +89,7 @@ static const int __initconst a370_nbclk_ratios[32][2] = {
89 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 89 {0, 1}, {0, 1}, {0, 1}, {0, 1},
90}; 90};
91 91
92static const int __initconst a370_hclk_ratios[32][2] = { 92static const int a370_hclk_ratios[32][2] __initconst = {
93 {0, 1}, {1, 2}, {2, 6}, {2, 3}, 93 {0, 1}, {1, 2}, {2, 6}, {2, 3},
94 {1, 3}, {1, 4}, {1, 2}, {2, 6}, 94 {1, 3}, {1, 4}, {1, 2}, {2, 6},
95 {0, 1}, {1, 6}, {2, 10}, {0, 1}, 95 {0, 1}, {1, 6}, {2, 10}, {0, 1},
@@ -100,7 +100,7 @@ static const int __initconst a370_hclk_ratios[32][2] = {
100 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 100 {0, 1}, {0, 1}, {0, 1}, {0, 1},
101}; 101};
102 102
103static const int __initconst a370_dramclk_ratios[32][2] = { 103static const int a370_dramclk_ratios[32][2] __initconst = {
104 {0, 1}, {1, 2}, {2, 3}, {2, 3}, 104 {0, 1}, {1, 2}, {2, 3}, {2, 3},
105 {1, 3}, {1, 2}, {1, 2}, {2, 6}, 105 {1, 3}, {1, 2}, {1, 2}, {2, 6},
106 {0, 1}, {1, 3}, {2, 5}, {0, 1}, 106 {0, 1}, {1, 3}, {2, 5}, {0, 1},
@@ -152,7 +152,7 @@ CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
152 * Clock Gating Control 152 * Clock Gating Control
153 */ 153 */
154 154
155static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = { 155static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
156 { "audio", NULL, 0, 0 }, 156 { "audio", NULL, 0, 0 },
157 { "pex0_en", NULL, 1, 0 }, 157 { "pex0_en", NULL, 1, 0 },
158 { "pex1_en", NULL, 2, 0 }, 158 { "pex1_en", NULL, 2, 0 },
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index 13b62ceb3407..9922c4475aa8 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -40,7 +40,7 @@
40 40
41enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK }; 41enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
42 42
43static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = { 43static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
44 { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" }, 44 { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
45 { .id = AXP_CPU_TO_HCLK, .name = "hclk" }, 45 { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
46 { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" }, 46 { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
@@ -52,7 +52,7 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
52 return 250000000; 52 return 250000000;
53} 53}
54 54
55static const u32 __initconst axp_cpu_freqs[] = { 55static const u32 axp_cpu_freqs[] __initconst = {
56 1000000000, 56 1000000000,
57 1066000000, 57 1066000000,
58 1200000000, 58 1200000000,
@@ -89,7 +89,7 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
89 return cpu_freq; 89 return cpu_freq;
90} 90}
91 91
92static const int __initconst axp_nbclk_ratios[32][2] = { 92static const int axp_nbclk_ratios[32][2] __initconst = {
93 {0, 1}, {1, 2}, {2, 2}, {2, 2}, 93 {0, 1}, {1, 2}, {2, 2}, {2, 2},
94 {1, 2}, {1, 2}, {1, 1}, {2, 3}, 94 {1, 2}, {1, 2}, {1, 1}, {2, 3},
95 {0, 1}, {1, 2}, {2, 4}, {0, 1}, 95 {0, 1}, {1, 2}, {2, 4}, {0, 1},
@@ -100,7 +100,7 @@ static const int __initconst axp_nbclk_ratios[32][2] = {
100 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 100 {0, 1}, {0, 1}, {0, 1}, {0, 1},
101}; 101};
102 102
103static const int __initconst axp_hclk_ratios[32][2] = { 103static const int axp_hclk_ratios[32][2] __initconst = {
104 {0, 1}, {1, 2}, {2, 6}, {2, 3}, 104 {0, 1}, {1, 2}, {2, 6}, {2, 3},
105 {1, 3}, {1, 4}, {1, 2}, {2, 6}, 105 {1, 3}, {1, 4}, {1, 2}, {2, 6},
106 {0, 1}, {1, 6}, {2, 10}, {0, 1}, 106 {0, 1}, {1, 6}, {2, 10}, {0, 1},
@@ -111,7 +111,7 @@ static const int __initconst axp_hclk_ratios[32][2] = {
111 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 111 {0, 1}, {0, 1}, {0, 1}, {0, 1},
112}; 112};
113 113
114static const int __initconst axp_dramclk_ratios[32][2] = { 114static const int axp_dramclk_ratios[32][2] __initconst = {
115 {0, 1}, {1, 2}, {2, 3}, {2, 3}, 115 {0, 1}, {1, 2}, {2, 3}, {2, 3},
116 {1, 3}, {1, 2}, {1, 2}, {2, 6}, 116 {1, 3}, {1, 2}, {1, 2}, {2, 6},
117 {0, 1}, {1, 3}, {2, 5}, {0, 1}, 117 {0, 1}, {1, 3}, {2, 5}, {0, 1},
@@ -169,7 +169,7 @@ CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
169 * Clock Gating Control 169 * Clock Gating Control
170 */ 170 */
171 171
172static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = { 172static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
173 { "audio", NULL, 0, 0 }, 173 { "audio", NULL, 0, 0 },
174 { "ge3", NULL, 1, 0 }, 174 { "ge3", NULL, 1, 0 },
175 { "ge2", NULL, 2, 0 }, 175 { "ge2", NULL, 2, 0 },
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index b0fbc0715491..1466865b0743 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -119,7 +119,7 @@ void __init of_cpu_clk_setup(struct device_node *node)
119 119
120 cpuclk = kzalloc(ncpus * sizeof(*cpuclk), GFP_KERNEL); 120 cpuclk = kzalloc(ncpus * sizeof(*cpuclk), GFP_KERNEL);
121 if (WARN_ON(!cpuclk)) 121 if (WARN_ON(!cpuclk))
122 return; 122 goto cpuclk_out;
123 123
124 clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL); 124 clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL);
125 if (WARN_ON(!clks)) 125 if (WARN_ON(!clks))
@@ -170,6 +170,8 @@ bail_out:
170 kfree(cpuclk[ncpus].clk_name); 170 kfree(cpuclk[ncpus].clk_name);
171clks_out: 171clks_out:
172 kfree(cpuclk); 172 kfree(cpuclk);
173cpuclk_out:
174 iounmap(clock_complex_base);
173} 175}
174 176
175CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock", 177CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index adaa4a1821b8..25ceccf939ad 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -45,8 +45,10 @@ void __init mvebu_coreclk_setup(struct device_node *np,
45 clk_data.clk_num = 2 + desc->num_ratios; 45 clk_data.clk_num = 2 + desc->num_ratios;
46 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), 46 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
47 GFP_KERNEL); 47 GFP_KERNEL);
48 if (WARN_ON(!clk_data.clks)) 48 if (WARN_ON(!clk_data.clks)) {
49 iounmap(base);
49 return; 50 return;
51 }
50 52
51 /* Register TCLK */ 53 /* Register TCLK */
52 of_property_read_string_index(np, "clock-output-names", 0, 54 of_property_read_string_index(np, "clock-output-names", 0,
@@ -134,7 +136,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
134 136
135 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 137 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
136 if (WARN_ON(!ctrl)) 138 if (WARN_ON(!ctrl))
137 return; 139 goto ctrl_out;
138 140
139 spin_lock_init(&ctrl->lock); 141 spin_lock_init(&ctrl->lock);
140 142
@@ -145,10 +147,8 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
145 ctrl->num_gates = n; 147 ctrl->num_gates = n;
146 ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), 148 ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
147 GFP_KERNEL); 149 GFP_KERNEL);
148 if (WARN_ON(!ctrl->gates)) { 150 if (WARN_ON(!ctrl->gates))
149 kfree(ctrl); 151 goto gates_out;
150 return;
151 }
152 152
153 for (n = 0; n < ctrl->num_gates; n++) { 153 for (n = 0; n < ctrl->num_gates; n++) {
154 const char *parent = 154 const char *parent =
@@ -160,4 +160,10 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
160 } 160 }
161 161
162 of_clk_add_provider(np, clk_gating_get_src, ctrl); 162 of_clk_add_provider(np, clk_gating_get_src, ctrl);
163
164 return;
165gates_out:
166 kfree(ctrl);
167ctrl_out:
168 iounmap(base);
163} 169}
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
index 79d7aedf03fb..38aee1e3f242 100644
--- a/drivers/clk/mvebu/dove.c
+++ b/drivers/clk/mvebu/dove.c
@@ -74,12 +74,12 @@
74 74
75enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR }; 75enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
76 76
77static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = { 77static const struct coreclk_ratio dove_coreclk_ratios[] __initconst = {
78 { .id = DOVE_CPU_TO_L2, .name = "l2clk", }, 78 { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
79 { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", } 79 { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
80}; 80};
81 81
82static const u32 __initconst dove_tclk_freqs[] = { 82static const u32 dove_tclk_freqs[] __initconst = {
83 166666667, 83 166666667,
84 125000000, 84 125000000,
85 0, 0 85 0, 0
@@ -92,7 +92,7 @@ static u32 __init dove_get_tclk_freq(void __iomem *sar)
92 return dove_tclk_freqs[opt]; 92 return dove_tclk_freqs[opt];
93} 93}
94 94
95static const u32 __initconst dove_cpu_freqs[] = { 95static const u32 dove_cpu_freqs[] __initconst = {
96 0, 0, 0, 0, 0, 96 0, 0, 0, 0, 0,
97 1000000000, 97 1000000000,
98 933333333, 933333333, 98 933333333, 933333333,
@@ -111,12 +111,12 @@ static u32 __init dove_get_cpu_freq(void __iomem *sar)
111 return dove_cpu_freqs[opt]; 111 return dove_cpu_freqs[opt];
112} 112}
113 113
114static const int __initconst dove_cpu_l2_ratios[8][2] = { 114static const int dove_cpu_l2_ratios[8][2] __initconst = {
115 { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, 115 { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
116 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 } 116 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
117}; 117};
118 118
119static const int __initconst dove_cpu_ddr_ratios[16][2] = { 119static const int dove_cpu_ddr_ratios[16][2] __initconst = {
120 { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 }, 120 { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
121 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }, 121 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
122 { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 }, 122 { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
@@ -164,7 +164,7 @@ CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
164 * Clock Gating Control 164 * Clock Gating Control
165 */ 165 */
166 166
167static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = { 167static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
168 { "usb0", NULL, 0, 0 }, 168 { "usb0", NULL, 0, 0 },
169 { "usb1", NULL, 1, 0 }, 169 { "usb1", NULL, 1, 0 },
170 { "ge", "gephy", 2, 0 }, 170 { "ge", "gephy", 2, 0 },
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
index 71d24619ccdb..2636a55f29f9 100644
--- a/drivers/clk/mvebu/kirkwood.c
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -78,7 +78,7 @@
78 78
79enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR }; 79enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
80 80
81static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = { 81static const struct coreclk_ratio kirkwood_coreclk_ratios[] __initconst = {
82 { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", }, 82 { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
83 { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", } 83 { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
84}; 84};
@@ -90,7 +90,7 @@ static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
90 return (opt) ? 166666667 : 200000000; 90 return (opt) ? 166666667 : 200000000;
91} 91}
92 92
93static const u32 __initconst kirkwood_cpu_freqs[] = { 93static const u32 kirkwood_cpu_freqs[] __initconst = {
94 0, 0, 0, 0, 94 0, 0, 0, 0,
95 600000000, 95 600000000,
96 0, 96 0,
@@ -111,12 +111,12 @@ static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
111 return kirkwood_cpu_freqs[opt]; 111 return kirkwood_cpu_freqs[opt];
112} 112}
113 113
114static const int __initconst kirkwood_cpu_l2_ratios[8][2] = { 114static const int kirkwood_cpu_l2_ratios[8][2] __initconst = {
115 { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 }, 115 { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
116 { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 } 116 { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
117}; 117};
118 118
119static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = { 119static const int kirkwood_cpu_ddr_ratios[16][2] __initconst = {
120 { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, 120 { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
121 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 }, 121 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
122 { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 }, 122 { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
@@ -145,7 +145,7 @@ static void __init kirkwood_get_clk_ratio(
145 } 145 }
146} 146}
147 147
148static const u32 __initconst mv88f6180_cpu_freqs[] = { 148static const u32 mv88f6180_cpu_freqs[] __initconst = {
149 0, 0, 0, 0, 0, 149 0, 0, 0, 0, 0,
150 600000000, 150 600000000,
151 800000000, 151 800000000,
@@ -158,7 +158,7 @@ static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
158 return mv88f6180_cpu_freqs[opt]; 158 return mv88f6180_cpu_freqs[opt];
159} 159}
160 160
161static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = { 161static const int mv88f6180_cpu_ddr_ratios[8][2] __initconst = {
162 { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, 162 { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
163 { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 } 163 { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
164}; 164};
@@ -219,7 +219,7 @@ CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
219 * Clock Gating Control 219 * Clock Gating Control
220 */ 220 */
221 221
222static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = { 222static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {
223 { "ge0", NULL, 0, 0 }, 223 { "ge0", NULL, 0, 0 },
224 { "pex0", NULL, 2, 0 }, 224 { "pex0", NULL, 2, 0 },
225 { "usb0", NULL, 3, 0 }, 225 { "usb0", NULL, 3, 0 },
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index f6a74872f14e..c396fe361589 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/clk/mxs.h>
13#include <linux/clkdev.h> 14#include <linux/clkdev.h>
14#include <linux/err.h> 15#include <linux/err.h>
15#include <linux/init.h> 16#include <linux/init.h>
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 81421e28e69c..ef10ad9b5daa 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -52,8 +52,8 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
52 u8 shift, u8 width, const char **parent_names, int num_parents) 52 u8 shift, u8 width, const char **parent_names, int num_parents)
53{ 53{
54 return clk_register_mux(NULL, name, parent_names, num_parents, 54 return clk_register_mux(NULL, name, parent_names, num_parents,
55 CLK_SET_RATE_PARENT, reg, shift, width, 55 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
56 0, &mxs_lock); 56 reg, shift, width, 0, &mxs_lock);
57} 57}
58 58
59static inline struct clk *mxs_clk_fixed_factor(const char *name, 59static inline struct clk *mxs_clk_fixed_factor(const char *name,
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 5d4d432cc4ac..3413380086d5 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -8,3 +8,6 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
11ifdef CONFIG_COMMON_CLK
12obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
13endif
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd52fd1f..39b40aaede2b 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -62,7 +62,7 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
62#endif /* CONFIG_PM_SLEEP */ 62#endif /* CONFIG_PM_SLEEP */
63 63
64/* register exynos_audss clocks */ 64/* register exynos_audss clocks */
65void __init exynos_audss_clk_init(struct device_node *np) 65static void __init exynos_audss_clk_init(struct device_node *np)
66{ 66{
67 reg_base = of_iomap(np, 0); 67 reg_base = of_iomap(np, 0);
68 if (!reg_base) { 68 if (!reg_base) {
@@ -82,11 +82,13 @@ void __init exynos_audss_clk_init(struct device_node *np)
82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
83 83
84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", 84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
85 mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, 85 mout_audss_p, ARRAY_SIZE(mout_audss_p),
86 CLK_SET_RATE_NO_REPARENT,
86 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 87 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
87 88
88 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", 89 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
89 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, 90 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
91 CLK_SET_RATE_NO_REPARENT,
90 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 92 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
91 93
92 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", 94 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 4e5739773c33..ad5ff50c5f28 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -17,7 +17,6 @@
17#include <linux/of_address.h> 17#include <linux/of_address.h>
18 18
19#include "clk.h" 19#include "clk.h"
20#include "clk-pll.h"
21 20
22/* Exynos4 clock controller register offsets */ 21/* Exynos4 clock controller register offsets */
23#define SRC_LEFTBUS 0x4200 22#define SRC_LEFTBUS 0x4200
@@ -97,12 +96,15 @@
97#define GATE_IP_PERIL 0xc950 96#define GATE_IP_PERIL 0xc950
98#define E4210_GATE_IP_PERIR 0xc960 97#define E4210_GATE_IP_PERIR 0xc960
99#define GATE_BLOCK 0xc970 98#define GATE_BLOCK 0xc970
99#define E4X12_MPLL_LOCK 0x10008
100#define E4X12_MPLL_CON0 0x10108 100#define E4X12_MPLL_CON0 0x10108
101#define SRC_DMC 0x10200 101#define SRC_DMC 0x10200
102#define SRC_MASK_DMC 0x10300 102#define SRC_MASK_DMC 0x10300
103#define DIV_DMC0 0x10500 103#define DIV_DMC0 0x10500
104#define DIV_DMC1 0x10504 104#define DIV_DMC1 0x10504
105#define GATE_IP_DMC 0x10900 105#define GATE_IP_DMC 0x10900
106#define APLL_LOCK 0x14000
107#define E4210_MPLL_LOCK 0x14008
106#define APLL_CON0 0x14100 108#define APLL_CON0 0x14100
107#define E4210_MPLL_CON0 0x14108 109#define E4210_MPLL_CON0 0x14108
108#define SRC_CPU 0x14200 110#define SRC_CPU 0x14200
@@ -121,6 +123,12 @@ enum exynos4_soc {
121 EXYNOS4X12, 123 EXYNOS4X12,
122}; 124};
123 125
126/* list of PLLs to be registered */
127enum exynos4_plls {
128 apll, mpll, epll, vpll,
129 nr_plls /* number of PLLs */
130};
131
124/* 132/*
125 * Let each supported clock get a unique id. This id is used to lookup the clock 133 * Let each supported clock get a unique id. This id is used to lookup the clock
126 * for device tree based platforms. The clocks are categorized into three 134 * for device tree based platforms. The clocks are categorized into three
@@ -169,7 +177,7 @@ enum exynos4_clks {
169 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, 177 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
170 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, 178 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
171 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, 179 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
172 spi1_isp_sclk, uart_isp_sclk, 180 spi1_isp_sclk, uart_isp_sclk, tmu_apbif,
173 181
174 /* mux clocks */ 182 /* mux clocks */
175 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, 183 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
@@ -187,7 +195,7 @@ enum exynos4_clks {
187 * list of controller registers to be saved and restored during a 195 * list of controller registers to be saved and restored during a
188 * suspend/resume cycle. 196 * suspend/resume cycle.
189 */ 197 */
190static __initdata unsigned long exynos4210_clk_save[] = { 198static unsigned long exynos4210_clk_save[] __initdata = {
191 E4210_SRC_IMAGE, 199 E4210_SRC_IMAGE,
192 E4210_SRC_LCD1, 200 E4210_SRC_LCD1,
193 E4210_SRC_MASK_LCD1, 201 E4210_SRC_MASK_LCD1,
@@ -198,7 +206,7 @@ static __initdata unsigned long exynos4210_clk_save[] = {
198 E4210_MPLL_CON0, 206 E4210_MPLL_CON0,
199}; 207};
200 208
201static __initdata unsigned long exynos4x12_clk_save[] = { 209static unsigned long exynos4x12_clk_save[] __initdata = {
202 E4X12_GATE_IP_IMAGE, 210 E4X12_GATE_IP_IMAGE,
203 E4X12_GATE_IP_PERIR, 211 E4X12_GATE_IP_PERIR,
204 E4X12_SRC_CAM1, 212 E4X12_SRC_CAM1,
@@ -207,7 +215,7 @@ static __initdata unsigned long exynos4x12_clk_save[] = {
207 E4X12_MPLL_CON0, 215 E4X12_MPLL_CON0,
208}; 216};
209 217
210static __initdata unsigned long exynos4_clk_regs[] = { 218static unsigned long exynos4_clk_regs[] __initdata = {
211 SRC_LEFTBUS, 219 SRC_LEFTBUS,
212 DIV_LEFTBUS, 220 DIV_LEFTBUS,
213 GATE_IP_LEFTBUS, 221 GATE_IP_LEFTBUS,
@@ -338,24 +346,24 @@ PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
338PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 346PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
339 347
340/* fixed rate clocks generated outside the soc */ 348/* fixed rate clocks generated outside the soc */
341struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 349static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
342 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), 350 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
343 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), 351 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
344}; 352};
345 353
346/* fixed rate clocks generated inside the soc */ 354/* fixed rate clocks generated inside the soc */
347struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 355static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
348 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 356 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
349 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 357 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
350 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 358 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
351}; 359};
352 360
353struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 361static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
354 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 362 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
355}; 363};
356 364
357/* list of mux clocks supported in all exynos4 soc's */ 365/* list of mux clocks supported in all exynos4 soc's */
358struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 366static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
359 MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 367 MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
360 CLK_SET_RATE_PARENT, 0, "mout_apll"), 368 CLK_SET_RATE_PARENT, 0, "mout_apll"),
361 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 369 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
@@ -367,17 +375,20 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
367 CLK_SET_RATE_PARENT, 0), 375 CLK_SET_RATE_PARENT, 0),
368 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 376 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
369 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 377 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
370 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"), 378 MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
371 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 379 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
372}; 380};
373 381
374/* list of mux clocks supported in exynos4210 soc */ 382/* list of mux clocks supported in exynos4210 soc */
375struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 383static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
384 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
385};
386
387static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
376 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 388 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
377 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 389 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
378 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 390 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
379 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 391 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
380 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
381 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 392 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
382 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 393 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
383 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 394 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
@@ -385,11 +396,9 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
385 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 396 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
386 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 397 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
387 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 398 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
388 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), 399 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
389 MUX_A(mout_core, "mout_core", mout_core_p4210, 400 MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
390 SRC_CPU, 16, 1, "moutcore"), 401 MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
391 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
392 SRC_TOP0, 8, 1, "sclk_vpll"),
393 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 402 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
394 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 403 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
395 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 404 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
@@ -423,9 +432,9 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
423}; 432};
424 433
425/* list of mux clocks supported in exynos4x12 soc */ 434/* list of mux clocks supported in exynos4x12 soc */
426struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 435static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
427 MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, 436 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
428 SRC_CPU, 24, 1, "mout_mpll"), 437 SRC_CPU, 24, 1),
429 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 438 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
430 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 439 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
431 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, 440 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
@@ -445,12 +454,9 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
445 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 454 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
446 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 455 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
447 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 456 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
448 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, 457 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
449 SRC_DMC, 12, 1, "sclk_mpll"), 458 MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
450 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, 459 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
451 SRC_TOP0, 8, 1, "sclk_vpll"),
452 MUX_A(mout_core, "mout_core", mout_core_p4x12,
453 SRC_CPU, 16, 1, "moutcore"),
454 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 460 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
455 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 461 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
456 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 462 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
@@ -491,7 +497,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
491}; 497};
492 498
493/* list of divider clocks supported in all exynos4 soc's */ 499/* list of divider clocks supported in all exynos4 soc's */
494struct samsung_div_clock exynos4_div_clks[] __initdata = { 500static struct samsung_div_clock exynos4_div_clks[] __initdata = {
495 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), 501 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
496 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), 502 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
497 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 503 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
@@ -538,9 +544,8 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
538 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 544 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
539 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 545 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
540 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 546 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
541 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), 547 DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
542 DIV_A(sclk_apll, "sclk_apll", "mout_apll", 548 DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
543 DIV_CPU0, 24, 3, "sclk_apll"),
544 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 549 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
545 CLK_SET_RATE_PARENT, 0), 550 CLK_SET_RATE_PARENT, 0),
546 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 551 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
@@ -554,7 +559,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
554}; 559};
555 560
556/* list of divider clocks supported in exynos4210 soc */ 561/* list of divider clocks supported in exynos4210 soc */
557struct samsung_div_clock exynos4210_div_clks[] __initdata = { 562static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
558 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 563 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
559 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 564 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
560 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 565 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
@@ -565,7 +570,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata = {
565}; 570};
566 571
567/* list of divider clocks supported in exynos4x12 soc */ 572/* list of divider clocks supported in exynos4x12 soc */
568struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 573static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
569 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 574 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
570 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 575 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
571 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 576 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
@@ -594,7 +599,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
594}; 599};
595 600
596/* list of gate clocks supported in all exynos4 soc's */ 601/* list of gate clocks supported in all exynos4 soc's */
597struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 602static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
598 /* 603 /*
599 * After all Exynos4 based platforms are migrated to use device tree, 604 * After all Exynos4 based platforms are migrated to use device tree,
600 * the device name and clock alias names specified below for some 605 * the device name and clock alias names specified below for some
@@ -629,164 +634,151 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
629 CLK_SET_RATE_PARENT, 0), 634 CLK_SET_RATE_PARENT, 0),
630 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 635 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
631 CLK_SET_RATE_PARENT, 0), 636 CLK_SET_RATE_PARENT, 0),
632 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 637 GATE(vp, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
633 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 638 GATE(mixer, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
634 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 639 GATE(hdmi, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
635 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"), 640 GATE(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
636 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"), 641 GATE(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
637 GATE_A(usb_host, "usb_host", "aclk133", 642 GATE(usb_host, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
638 GATE_IP_FSYS, 12, 0, 0, "usbhost"), 643 GATE(sclk_fimc0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
639 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0", 644 CLK_SET_RATE_PARENT, 0),
640 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 645 GATE(sclk_fimc1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
641 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1", 646 CLK_SET_RATE_PARENT, 0),
642 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 647 GATE(sclk_fimc2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
643 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2", 648 CLK_SET_RATE_PARENT, 0),
644 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 649 GATE(sclk_fimc3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
645 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3", 650 CLK_SET_RATE_PARENT, 0),
646 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 651 GATE(sclk_csis0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
647 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0", 652 CLK_SET_RATE_PARENT, 0),
648 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"), 653 GATE(sclk_csis1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
649 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1", 654 CLK_SET_RATE_PARENT, 0),
650 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"), 655 GATE(sclk_fimd0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
651 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0", 656 CLK_SET_RATE_PARENT, 0),
652 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), 657 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
653 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0", 658 CLK_SET_RATE_PARENT, 0),
654 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0, 659 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
655 "mmc_busclk.2"), 660 CLK_SET_RATE_PARENT, 0),
656 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1", 661 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
657 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0, 662 CLK_SET_RATE_PARENT, 0),
658 "mmc_busclk.2"), 663 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
659 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2", 664 CLK_SET_RATE_PARENT, 0),
660 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0, 665 GATE(sclk_mmc4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
661 "mmc_busclk.2"), 666 CLK_SET_RATE_PARENT, 0),
662 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3", 667 GATE(sclk_uart0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
663 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0, 668 CLK_SET_RATE_PARENT, 0),
664 "mmc_busclk.2"), 669 GATE(sclk_uart1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
665 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4", 670 CLK_SET_RATE_PARENT, 0),
666 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"), 671 GATE(sclk_uart2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
667 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0", 672 CLK_SET_RATE_PARENT, 0),
668 SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT, 673 GATE(sclk_uart3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
669 0, "clk_uart_baud0"), 674 CLK_SET_RATE_PARENT, 0),
670 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1", 675 GATE(sclk_uart4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
671 SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT, 676 CLK_SET_RATE_PARENT, 0),
672 0, "clk_uart_baud0"),
673 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
674 SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
675 0, "clk_uart_baud0"),
676 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
677 SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
678 0, "clk_uart_baud0"),
679 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
680 SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
681 0, "clk_uart_baud0"),
682 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 677 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
683 CLK_SET_RATE_PARENT, 0), 678 CLK_SET_RATE_PARENT, 0),
684 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", 679 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
685 SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT, 680 CLK_SET_RATE_PARENT, 0),
686 0, "spi_busclk0"), 681 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
687 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", 682 CLK_SET_RATE_PARENT, 0),
688 SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT, 683 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
689 0, "spi_busclk0"), 684 CLK_SET_RATE_PARENT, 0),
690 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", 685 GATE(fimc0, "fimc0", "aclk160", GATE_IP_CAM, 0,
691 SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT, 686 0, 0),
692 0, "spi_busclk0"), 687 GATE(fimc1, "fimc1", "aclk160", GATE_IP_CAM, 1,
693 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", 688 0, 0),
694 GATE_IP_CAM, 0, 0, 0, "fimc"), 689 GATE(fimc2, "fimc2", "aclk160", GATE_IP_CAM, 2,
695 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160", 690 0, 0),
696 GATE_IP_CAM, 1, 0, 0, "fimc"), 691 GATE(fimc3, "fimc3", "aclk160", GATE_IP_CAM, 3,
697 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160", 692 0, 0),
698 GATE_IP_CAM, 2, 0, 0, "fimc"), 693 GATE(csis0, "csis0", "aclk160", GATE_IP_CAM, 4,
699 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160", 694 0, 0),
700 GATE_IP_CAM, 3, 0, 0, "fimc"), 695 GATE(csis1, "csis1", "aclk160", GATE_IP_CAM, 5,
701 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160", 696 0, 0),
702 GATE_IP_CAM, 4, 0, 0, "fimc"), 697 GATE(smmu_fimc0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
703 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160", 698 0, 0),
704 GATE_IP_CAM, 5, 0, 0, "fimc"), 699 GATE(smmu_fimc1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
705 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160", 700 0, 0),
706 GATE_IP_CAM, 7, 0, 0, "sysmmu"), 701 GATE(smmu_fimc2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
707 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160", 702 0, 0),
708 GATE_IP_CAM, 8, 0, 0, "sysmmu"), 703 GATE(smmu_fimc3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
709 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160", 704 0, 0),
710 GATE_IP_CAM, 9, 0, 0, "sysmmu"), 705 GATE(smmu_jpeg, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
711 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160", 706 0, 0),
712 GATE_IP_CAM, 10, 0, 0, "sysmmu"),
713 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
714 GATE_IP_CAM, 11, 0, 0, "sysmmu"),
715 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
716 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
717 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", 709 GATE(smmu_tv, "smmu_tv", "aclk160", GATE_IP_TV, 4,
718 GATE_IP_TV, 4, 0, 0, "sysmmu"), 710 0, 0),
719 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), 711 GATE(mfc, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
720 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100", 712 GATE(smmu_mfcl, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
721 GATE_IP_MFC, 1, 0, 0, "sysmmu"), 713 0, 0),
722 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100", 714 GATE(smmu_mfcr, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
723 GATE_IP_MFC, 2, 0, 0, "sysmmu"), 715 0, 0),
724 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160", 716 GATE(fimd0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
725 GATE_IP_LCD0, 0, 0, 0, "fimd"), 717 0, 0),
726 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160", 718 GATE(smmu_fimd0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
727 GATE_IP_LCD0, 4, 0, 0, "sysmmu"), 719 0, 0),
728 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133", 720 GATE(pdma0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
729 GATE_IP_FSYS, 0, 0, 0, "dma"), 721 0, 0),
730 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133", 722 GATE(pdma1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
731 GATE_IP_FSYS, 1, 0, 0, "dma"), 723 0, 0),
732 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133", 724 GATE(sdmmc0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
733 GATE_IP_FSYS, 5, 0, 0, "hsmmc"), 725 0, 0),
734 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133", 726 GATE(sdmmc1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
735 GATE_IP_FSYS, 6, 0, 0, "hsmmc"), 727 0, 0),
736 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133", 728 GATE(sdmmc2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
737 GATE_IP_FSYS, 7, 0, 0, "hsmmc"), 729 0, 0),
738 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133", 730 GATE(sdmmc3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
739 GATE_IP_FSYS, 8, 0, 0, "hsmmc"), 731 0, 0),
740 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100", 732 GATE(uart0, "uart0", "aclk100", GATE_IP_PERIL, 0,
741 GATE_IP_PERIL, 0, 0, 0, "uart"), 733 0, 0),
742 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100", 734 GATE(uart1, "uart1", "aclk100", GATE_IP_PERIL, 1,
743 GATE_IP_PERIL, 1, 0, 0, "uart"), 735 0, 0),
744 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100", 736 GATE(uart2, "uart2", "aclk100", GATE_IP_PERIL, 2,
745 GATE_IP_PERIL, 2, 0, 0, "uart"), 737 0, 0),
746 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100", 738 GATE(uart3, "uart3", "aclk100", GATE_IP_PERIL, 3,
747 GATE_IP_PERIL, 3, 0, 0, "uart"), 739 0, 0),
748 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100", 740 GATE(uart4, "uart4", "aclk100", GATE_IP_PERIL, 4,
749 GATE_IP_PERIL, 4, 0, 0, "uart"), 741 0, 0),
750 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100", 742 GATE(i2c0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
751 GATE_IP_PERIL, 6, 0, 0, "i2c"), 743 0, 0),
752 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100", 744 GATE(i2c1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
753 GATE_IP_PERIL, 7, 0, 0, "i2c"), 745 0, 0),
754 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100", 746 GATE(i2c2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
755 GATE_IP_PERIL, 8, 0, 0, "i2c"), 747 0, 0),
756 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100", 748 GATE(i2c3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
757 GATE_IP_PERIL, 9, 0, 0, "i2c"), 749 0, 0),
758 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100", 750 GATE(i2c4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
759 GATE_IP_PERIL, 10, 0, 0, "i2c"), 751 0, 0),
760 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100", 752 GATE(i2c5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
761 GATE_IP_PERIL, 11, 0, 0, "i2c"), 753 0, 0),
762 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100", 754 GATE(i2c6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
763 GATE_IP_PERIL, 12, 0, 0, "i2c"), 755 0, 0),
764 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100", 756 GATE(i2c7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
765 GATE_IP_PERIL, 13, 0, 0, "i2c"), 757 0, 0),
766 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100", 758 GATE(i2c_hdmi, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
767 GATE_IP_PERIL, 14, 0, 0, "i2c"), 759 0, 0),
768 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100", 760 GATE(spi0, "spi0", "aclk100", GATE_IP_PERIL, 16,
769 GATE_IP_PERIL, 16, 0, 0, "spi"), 761 0, 0),
770 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100", 762 GATE(spi1, "spi1", "aclk100", GATE_IP_PERIL, 17,
771 GATE_IP_PERIL, 17, 0, 0, "spi"), 763 0, 0),
772 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100", 764 GATE(spi2, "spi2", "aclk100", GATE_IP_PERIL, 18,
773 GATE_IP_PERIL, 18, 0, 0, "spi"), 765 0, 0),
774 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100", 766 GATE(i2s1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
775 GATE_IP_PERIL, 20, 0, 0, "iis"), 767 0, 0),
776 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100", 768 GATE(i2s2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
777 GATE_IP_PERIL, 21, 0, 0, "iis"), 769 0, 0),
778 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100", 770 GATE(pcm1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
779 GATE_IP_PERIL, 22, 0, 0, "pcm"), 771 0, 0),
780 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100", 772 GATE(pcm2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
781 GATE_IP_PERIL, 23, 0, 0, "pcm"), 773 0, 0),
782 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100", 774 GATE(spdif, "spdif", "aclk100", GATE_IP_PERIL, 26,
783 GATE_IP_PERIL, 26, 0, 0, "spdif"), 775 0, 0),
784 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100", 776 GATE(ac97, "ac97", "aclk100", GATE_IP_PERIL, 27,
785 GATE_IP_PERIL, 27, 0, 0, "ac97"), 777 0, 0),
786}; 778};
787 779
788/* list of gate clocks supported in exynos4210 soc */ 780/* list of gate clocks supported in exynos4210 soc */
789struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 781static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
790 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
791 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
792 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
@@ -811,17 +803,23 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
811 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 803 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
812 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 804 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
813 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 805 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
814 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), 806 GATE(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15,
815 GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"), 807 0, 0),
816 GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"), 808 GATE(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
817 GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"), 809 0, 0),
818 GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), 810 GATE(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
819 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", 811 0, 0),
820 E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), 812 GATE(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
813 0, 0),
814 GATE(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
815 0, 0),
816 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
817 CLK_SET_RATE_PARENT, 0),
818 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0),
821}; 819};
822 820
823/* list of gate clocks supported in exynos4x12 soc */ 821/* list of gate clocks supported in exynos4x12 soc */
824struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 822static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
825 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 823 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
826 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 824 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
827 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 825 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
@@ -840,10 +838,11 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
840 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 838 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
841 GATE(smmu_rotator, "smmu_rotator", "aclk200", 839 GATE(smmu_rotator, "smmu_rotator", "aclk200",
842 E4X12_GATE_IP_IMAGE, 4, 0, 0), 840 E4X12_GATE_IP_IMAGE, 4, 0, 0),
843 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"), 841 GATE(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
844 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), 842 0, 0),
845 GATE_A(keyif, "keyif", "aclk100", 843 GATE(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
846 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"), 844 0, 0),
845 GATE(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
847 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", 846 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
848 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 847 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
849 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", 848 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
@@ -860,12 +859,11 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
860 E4X12_GATE_IP_ISP, 2, 0, 0), 859 E4X12_GATE_IP_ISP, 2, 0, 0),
861 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", 860 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
862 E4X12_GATE_IP_ISP, 3, 0, 0), 861 E4X12_GATE_IP_ISP, 3, 0, 0),
863 GATE_A(wdt, "watchdog", "aclk100", 862 GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
864 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"), 863 GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
865 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100", 864 0, 0),
866 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), 865 GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
867 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", 866 0, 0),
868 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
869 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 867 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
870 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 868 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
871 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 869 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
@@ -919,6 +917,21 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
919 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 917 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
920 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 918 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
921 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 919 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
920 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0),
921};
922
923static struct samsung_clock_alias exynos4_aliases[] __initdata = {
924 ALIAS(mout_core, NULL, "moutcore"),
925 ALIAS(arm_clk, NULL, "armclk"),
926 ALIAS(sclk_apll, NULL, "mout_apll"),
927};
928
929static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
930 ALIAS(sclk_mpll, NULL, "mout_mpll"),
931};
932
933static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
934 ALIAS(mout_mpll_user_c, NULL, "mout_mpll"),
922}; 935};
923 936
924/* 937/*
@@ -973,36 +986,116 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
973 986
974} 987}
975 988
976/* 989static struct of_device_id ext_clk_match[] __initdata = {
977 * This function allows non-dt platforms to specify the clock speed of the
978 * xxti and xusbxti clocks. These clocks are then registered with the specified
979 * clock speed.
980 */
981void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
982 unsigned long xusbxti_f)
983{
984 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
985 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
986 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
987 ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
988}
989
990static __initdata struct of_device_id ext_clk_match[] = {
991 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 990 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
992 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 991 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
993 {}, 992 {},
994}; 993};
995 994
995/* PLLs PMS values */
996static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {
997 PLL_45XX_RATE(1200000000, 150, 3, 1, 28),
998 PLL_45XX_RATE(1000000000, 250, 6, 1, 28),
999 PLL_45XX_RATE( 800000000, 200, 6, 1, 28),
1000 PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
1001 PLL_45XX_RATE( 600000000, 100, 4, 1, 13),
1002 PLL_45XX_RATE( 533000000, 533, 24, 1, 5),
1003 PLL_45XX_RATE( 500000000, 250, 6, 2, 28),
1004 PLL_45XX_RATE( 400000000, 200, 6, 2, 28),
1005 PLL_45XX_RATE( 200000000, 200, 6, 3, 28),
1006 { /* sentinel */ }
1007};
1008
1009static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {
1010 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0),
1011 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
1012 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0),
1013 PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
1014 PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
1015 PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0),
1016 PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
1017 { /* sentinel */ }
1018};
1019
1020static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {
1021 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),
1022 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1),
1023 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
1024 PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),
1025 PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
1026 { /* sentinel */ }
1027};
1028
1029static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {
1030 PLL_35XX_RATE(1500000000, 250, 4, 0),
1031 PLL_35XX_RATE(1400000000, 175, 3, 0),
1032 PLL_35XX_RATE(1300000000, 325, 6, 0),
1033 PLL_35XX_RATE(1200000000, 200, 4, 0),
1034 PLL_35XX_RATE(1100000000, 275, 6, 0),
1035 PLL_35XX_RATE(1000000000, 125, 3, 0),
1036 PLL_35XX_RATE( 900000000, 150, 4, 0),
1037 PLL_35XX_RATE( 800000000, 100, 3, 0),
1038 PLL_35XX_RATE( 700000000, 175, 3, 1),
1039 PLL_35XX_RATE( 600000000, 200, 4, 1),
1040 PLL_35XX_RATE( 500000000, 125, 3, 1),
1041 PLL_35XX_RATE( 400000000, 100, 3, 1),
1042 PLL_35XX_RATE( 300000000, 200, 4, 2),
1043 PLL_35XX_RATE( 200000000, 100, 3, 2),
1044 { /* sentinel */ }
1045};
1046
1047static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {
1048 PLL_36XX_RATE(192000000, 48, 3, 1, 0),
1049 PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
1050 PLL_36XX_RATE(180000000, 45, 3, 1, 0),
1051 PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
1052 PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
1053 PLL_36XX_RATE( 49151992, 49, 3, 3, 9961),
1054 PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
1055 { /* sentinel */ }
1056};
1057
1058static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
1059 PLL_36XX_RATE(533000000, 133, 3, 1, 16384),
1060 PLL_36XX_RATE(440000000, 110, 3, 1, 0),
1061 PLL_36XX_RATE(350000000, 175, 3, 2, 0),
1062 PLL_36XX_RATE(266000000, 133, 3, 2, 0),
1063 PLL_36XX_RATE(160000000, 160, 3, 3, 0),
1064 PLL_36XX_RATE(106031250, 53, 3, 2, 1024),
1065 PLL_36XX_RATE( 53015625, 53, 3, 3, 1024),
1066 { /* sentinel */ }
1067};
1068
1069static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1070 [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
1071 APLL_CON0, "fout_apll", NULL),
1072 [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll",
1073 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
1074 [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
1075 EPLL_CON0, "fout_epll", NULL),
1076 [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc",
1077 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
1078};
1079
1080static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1081 [apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll",
1082 APLL_LOCK, APLL_CON0, NULL),
1083 [mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",
1084 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1085 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll",
1086 EPLL_LOCK, EPLL_CON0, NULL),
1087 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll",
1088 VPLL_LOCK, VPLL_CON0, NULL),
1089};
1090
996/* register exynos4 clocks */ 1091/* register exynos4 clocks */
997void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom) 1092static void __init exynos4_clk_init(struct device_node *np,
1093 enum exynos4_soc exynos4_soc,
1094 void __iomem *reg_base, unsigned long xom)
998{ 1095{
999 struct clk *apll, *mpll, *epll, *vpll; 1096 reg_base = of_iomap(np, 0);
1000 1097 if (!reg_base)
1001 if (np) { 1098 panic("%s: failed to map registers\n", __func__);
1002 reg_base = of_iomap(np, 0);
1003 if (!reg_base)
1004 panic("%s: failed to map registers\n", __func__);
1005 }
1006 1099
1007 if (exynos4_soc == EXYNOS4210) 1100 if (exynos4_soc == EXYNOS4210)
1008 samsung_clk_init(np, reg_base, nr_clks, 1101 samsung_clk_init(np, reg_base, nr_clks,
@@ -1013,37 +1106,42 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
1013 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1106 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1014 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); 1107 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1015 1108
1016 if (np) 1109 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
1017 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
1018 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1110 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1019 ext_clk_match); 1111 ext_clk_match);
1020 1112
1021 exynos4_clk_register_finpll(xom); 1113 exynos4_clk_register_finpll(xom);
1022 1114
1023 if (exynos4_soc == EXYNOS4210) { 1115 if (exynos4_soc == EXYNOS4210) {
1024 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll", 1116 samsung_clk_register_mux(exynos4210_mux_early,
1025 reg_base + APLL_CON0, pll_4508); 1117 ARRAY_SIZE(exynos4210_mux_early));
1026 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", 1118
1027 reg_base + E4210_MPLL_CON0, pll_4508); 1119 if (_get_rate("fin_pll") == 24000000) {
1028 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", 1120 exynos4210_plls[apll].rate_table =
1029 reg_base + EPLL_CON0, pll_4600); 1121 exynos4210_apll_rates;
1030 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", 1122 exynos4210_plls[epll].rate_table =
1031 reg_base + VPLL_CON0, pll_4650c); 1123 exynos4210_epll_rates;
1124 }
1125
1126 if (_get_rate("mout_vpllsrc") == 24000000)
1127 exynos4210_plls[vpll].rate_table =
1128 exynos4210_vpll_rates;
1129
1130 samsung_clk_register_pll(exynos4210_plls,
1131 ARRAY_SIZE(exynos4210_plls), reg_base);
1032 } else { 1132 } else {
1033 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", 1133 if (_get_rate("fin_pll") == 24000000) {
1034 reg_base + APLL_CON0); 1134 exynos4x12_plls[apll].rate_table =
1035 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", 1135 exynos4x12_apll_rates;
1036 reg_base + E4X12_MPLL_CON0); 1136 exynos4x12_plls[epll].rate_table =
1037 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", 1137 exynos4x12_epll_rates;
1038 reg_base + EPLL_CON0); 1138 exynos4x12_plls[vpll].rate_table =
1039 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", 1139 exynos4x12_vpll_rates;
1040 reg_base + VPLL_CON0); 1140 }
1041 }
1042 1141
1043 samsung_clk_add_lookup(apll, fout_apll); 1142 samsung_clk_register_pll(exynos4x12_plls,
1044 samsung_clk_add_lookup(mpll, fout_mpll); 1143 ARRAY_SIZE(exynos4x12_plls), reg_base);
1045 samsung_clk_add_lookup(epll, fout_epll); 1144 }
1046 samsung_clk_add_lookup(vpll, fout_vpll);
1047 1145
1048 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, 1146 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
1049 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1147 ARRAY_SIZE(exynos4_fixed_rate_clks));
@@ -1063,6 +1161,8 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
1063 ARRAY_SIZE(exynos4210_div_clks)); 1161 ARRAY_SIZE(exynos4210_div_clks));
1064 samsung_clk_register_gate(exynos4210_gate_clks, 1162 samsung_clk_register_gate(exynos4210_gate_clks,
1065 ARRAY_SIZE(exynos4210_gate_clks)); 1163 ARRAY_SIZE(exynos4210_gate_clks));
1164 samsung_clk_register_alias(exynos4210_aliases,
1165 ARRAY_SIZE(exynos4210_aliases));
1066 } else { 1166 } else {
1067 samsung_clk_register_mux(exynos4x12_mux_clks, 1167 samsung_clk_register_mux(exynos4x12_mux_clks,
1068 ARRAY_SIZE(exynos4x12_mux_clks)); 1168 ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1070,14 +1170,19 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so
1070 ARRAY_SIZE(exynos4x12_div_clks)); 1170 ARRAY_SIZE(exynos4x12_div_clks));
1071 samsung_clk_register_gate(exynos4x12_gate_clks, 1171 samsung_clk_register_gate(exynos4x12_gate_clks,
1072 ARRAY_SIZE(exynos4x12_gate_clks)); 1172 ARRAY_SIZE(exynos4x12_gate_clks));
1173 samsung_clk_register_alias(exynos4x12_aliases,
1174 ARRAY_SIZE(exynos4x12_aliases));
1073 } 1175 }
1074 1176
1177 samsung_clk_register_alias(exynos4_aliases,
1178 ARRAY_SIZE(exynos4_aliases));
1179
1075 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1180 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1076 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1181 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1077 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1182 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1078 _get_rate("sclk_apll"), _get_rate("mout_mpll"), 1183 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1079 _get_rate("sclk_epll"), _get_rate("sclk_vpll"), 1184 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1080 _get_rate("armclk")); 1185 _get_rate("arm_clk"));
1081} 1186}
1082 1187
1083 1188
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 6f767c515ec7..adf32343c9f9 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -17,11 +17,22 @@
17#include <linux/of_address.h> 17#include <linux/of_address.h>
18 18
19#include "clk.h" 19#include "clk.h"
20#include "clk-pll.h"
21 20
21#define APLL_LOCK 0x0
22#define APLL_CON0 0x100
22#define SRC_CPU 0x200 23#define SRC_CPU 0x200
23#define DIV_CPU0 0x500 24#define DIV_CPU0 0x500
25#define MPLL_LOCK 0x4000
26#define MPLL_CON0 0x4100
24#define SRC_CORE1 0x4204 27#define SRC_CORE1 0x4204
28#define CPLL_LOCK 0x10020
29#define EPLL_LOCK 0x10030
30#define VPLL_LOCK 0x10040
31#define GPLL_LOCK 0x10050
32#define CPLL_CON0 0x10120
33#define EPLL_CON0 0x10130
34#define VPLL_CON0 0x10140
35#define GPLL_CON0 0x10150
25#define SRC_TOP0 0x10210 36#define SRC_TOP0 0x10210
26#define SRC_TOP2 0x10218 37#define SRC_TOP2 0x10218
27#define SRC_GSCL 0x10220 38#define SRC_GSCL 0x10220
@@ -59,9 +70,18 @@
59#define GATE_IP_FSYS 0x10944 70#define GATE_IP_FSYS 0x10944
60#define GATE_IP_PERIC 0x10950 71#define GATE_IP_PERIC 0x10950
61#define GATE_IP_PERIS 0x10960 72#define GATE_IP_PERIS 0x10960
73#define BPLL_LOCK 0x20010
74#define BPLL_CON0 0x20110
62#define SRC_CDREX 0x20200 75#define SRC_CDREX 0x20200
63#define PLL_DIV2_SEL 0x20a24 76#define PLL_DIV2_SEL 0x20a24
64#define GATE_IP_DISP1 0x10928 77#define GATE_IP_DISP1 0x10928
78#define GATE_IP_ACP 0x10000
79
80/* list of PLLs to be registered */
81enum exynos5250_plls {
82 apll, mpll, cpll, epll, vpll, gpll, bpll,
83 nr_plls /* number of PLLs */
84};
65 85
66/* 86/*
67 * Let each supported clock get a unique id. This id is used to lookup the clock 87 * Let each supported clock get a unique id. This id is used to lookup the clock
@@ -79,7 +99,8 @@ enum exynos5250_clks {
79 none, 99 none,
80 100
81 /* core clocks */ 101 /* core clocks */
82 fin_pll, 102 fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
103 fout_epll, fout_vpll,
83 104
84 /* gate for special clocks (sclk) */ 105 /* gate for special clocks (sclk) */
85 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb, 106 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
@@ -87,7 +108,7 @@ enum exynos5250_clks {
87 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3, 108 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
88 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm, 109 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
89 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, 110 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
90 div_i2s1, div_i2s2, 111 div_i2s1, div_i2s2, sclk_hdmiphy,
91 112
92 /* gate clocks */ 113 /* gate clocks */
93 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0, 114 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -99,7 +120,10 @@ enum exynos5250_clks {
99 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, 120 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
100 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, 121 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
101 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, 122 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
102 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, 123 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
124
125 /* mux clocks */
126 mout_hdmi = 1024,
103 127
104 nr_clks, 128 nr_clks,
105}; 129};
@@ -108,7 +132,7 @@ enum exynos5250_clks {
108 * list of controller registers to be saved and restored during a 132 * list of controller registers to be saved and restored during a
109 * suspend/resume cycle. 133 * suspend/resume cycle.
110 */ 134 */
111static __initdata unsigned long exynos5250_clk_regs[] = { 135static unsigned long exynos5250_clk_regs[] __initdata = {
112 SRC_CPU, 136 SRC_CPU,
113 DIV_CPU0, 137 DIV_CPU0,
114 SRC_CORE1, 138 SRC_CORE1,
@@ -152,6 +176,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
152 SRC_CDREX, 176 SRC_CDREX,
153 PLL_DIV2_SEL, 177 PLL_DIV2_SEL,
154 GATE_IP_DISP1, 178 GATE_IP_DISP1,
179 GATE_IP_ACP,
155}; 180};
156 181
157/* list of all parent clock list */ 182/* list of all parent clock list */
@@ -191,31 +216,34 @@ PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
191 "spdif_extclk" }; 216 "spdif_extclk" };
192 217
193/* fixed rate clocks generated outside the soc */ 218/* fixed rate clocks generated outside the soc */
194struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 219static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
195 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 220 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
196}; 221};
197 222
198/* fixed rate clocks generated inside the soc */ 223/* fixed rate clocks generated inside the soc */
199struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 224static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
200 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 225 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
201 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 226 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
202 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 227 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
203 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 228 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
204}; 229};
205 230
206struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 231static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
207 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 232 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
208 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 233 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
209}; 234};
210 235
211struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 236static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
237 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
238};
239
240static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
212 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), 241 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
213 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 242 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
214 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 243 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
215 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 244 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
216 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 245 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
217 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 246 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
218 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
219 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 247 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
220 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), 248 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
221 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 249 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
@@ -232,7 +260,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
232 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 260 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
233 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 261 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
234 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 262 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
235 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 263 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
236 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 264 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
237 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 265 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
238 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 266 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
@@ -254,7 +282,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
254 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 282 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
255}; 283};
256 284
257struct samsung_div_clock exynos5250_div_clks[] __initdata = { 285static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
258 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 286 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
259 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 287 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
260 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3), 288 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
@@ -314,7 +342,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
314 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 342 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
315}; 343};
316 344
317struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 345static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
318 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), 346 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
319 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), 347 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
320 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0), 348 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
@@ -461,20 +489,60 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
461 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0), 489 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
462 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0), 490 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
463 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0), 491 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
464 GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0), 492 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
465 GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0), 493 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
494 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
495};
496
497static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
498 /* sorted in descending order */
499 /* PLL_36XX_RATE(rate, m, p, s, k) */
500 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
501 /* Not in UM, but need for eDP on snow */
502 PLL_36XX_RATE(70500000, 94, 2, 4, 0),
503 { },
504};
505
506static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
507 /* sorted in descending order */
508 /* PLL_36XX_RATE(rate, m, p, s, k) */
509 PLL_36XX_RATE(192000000, 64, 2, 2, 0),
510 PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
511 PLL_36XX_RATE(180000000, 90, 3, 2, 0),
512 PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
513 PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
514 PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
515 PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
516 PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
517 { },
518};
519
520static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
521 [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
522 APLL_CON0, "fout_apll", NULL),
523 [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
524 MPLL_CON0, "fout_mpll", NULL),
525 [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
526 BPLL_CON0, NULL),
527 [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK,
528 GPLL_CON0, NULL),
529 [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
530 CPLL_CON0, NULL),
531 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
532 EPLL_CON0, NULL),
533 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc",
534 VPLL_LOCK, VPLL_CON0, NULL),
466}; 535};
467 536
468static __initdata struct of_device_id ext_clk_match[] = { 537static struct of_device_id ext_clk_match[] __initdata = {
469 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 538 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
470 { }, 539 { },
471}; 540};
472 541
473/* register exynox5250 clocks */ 542/* register exynox5250 clocks */
474void __init exynos5250_clk_init(struct device_node *np) 543static void __init exynos5250_clk_init(struct device_node *np)
475{ 544{
476 void __iomem *reg_base; 545 void __iomem *reg_base;
477 struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
478 546
479 if (np) { 547 if (np) {
480 reg_base = of_iomap(np, 0); 548 reg_base = of_iomap(np, 0);
@@ -490,22 +558,17 @@ void __init exynos5250_clk_init(struct device_node *np)
490 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 558 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
491 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 559 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
492 ext_clk_match); 560 ext_clk_match);
561 samsung_clk_register_mux(exynos5250_pll_pmux_clks,
562 ARRAY_SIZE(exynos5250_pll_pmux_clks));
563
564 if (_get_rate("fin_pll") == 24 * MHZ)
565 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
493 566
494 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", 567 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
495 reg_base + 0x100); 568 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
496 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
497 reg_base + 0x4100);
498 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
499 reg_base + 0x20110);
500 gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
501 reg_base + 0x10150);
502 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
503 reg_base + 0x10120);
504 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
505 reg_base + 0x10130);
506 vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
507 reg_base + 0x10140);
508 569
570 samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
571 reg_base);
509 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, 572 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
510 ARRAY_SIZE(exynos5250_fixed_rate_clks)); 573 ARRAY_SIZE(exynos5250_fixed_rate_clks));
511 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks, 574 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 68a96cbd4936..48c4a9350b91 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -17,13 +17,30 @@
17#include <linux/of_address.h> 17#include <linux/of_address.h>
18 18
19#include "clk.h" 19#include "clk.h"
20#include "clk-pll.h"
21 20
21#define APLL_LOCK 0x0
22#define APLL_CON0 0x100
22#define SRC_CPU 0x200 23#define SRC_CPU 0x200
23#define DIV_CPU0 0x500 24#define DIV_CPU0 0x500
24#define DIV_CPU1 0x504 25#define DIV_CPU1 0x504
25#define GATE_BUS_CPU 0x700 26#define GATE_BUS_CPU 0x700
26#define GATE_SCLK_CPU 0x800 27#define GATE_SCLK_CPU 0x800
28#define CPLL_LOCK 0x10020
29#define DPLL_LOCK 0x10030
30#define EPLL_LOCK 0x10040
31#define RPLL_LOCK 0x10050
32#define IPLL_LOCK 0x10060
33#define SPLL_LOCK 0x10070
34#define VPLL_LOCK 0x10070
35#define MPLL_LOCK 0x10090
36#define CPLL_CON0 0x10120
37#define DPLL_CON0 0x10128
38#define EPLL_CON0 0x10130
39#define RPLL_CON0 0x10140
40#define IPLL_CON0 0x10150
41#define SPLL_CON0 0x10160
42#define VPLL_CON0 0x10170
43#define MPLL_CON0 0x10180
27#define SRC_TOP0 0x10200 44#define SRC_TOP0 0x10200
28#define SRC_TOP1 0x10204 45#define SRC_TOP1 0x10204
29#define SRC_TOP2 0x10208 46#define SRC_TOP2 0x10208
@@ -75,15 +92,27 @@
75#define GATE_TOP_SCLK_MAU 0x1083c 92#define GATE_TOP_SCLK_MAU 0x1083c
76#define GATE_TOP_SCLK_FSYS 0x10840 93#define GATE_TOP_SCLK_FSYS 0x10840
77#define GATE_TOP_SCLK_PERIC 0x10850 94#define GATE_TOP_SCLK_PERIC 0x10850
95#define BPLL_LOCK 0x20010
96#define BPLL_CON0 0x20110
78#define SRC_CDREX 0x20200 97#define SRC_CDREX 0x20200
98#define KPLL_LOCK 0x28000
99#define KPLL_CON0 0x28100
79#define SRC_KFC 0x28200 100#define SRC_KFC 0x28200
80#define DIV_KFC0 0x28500 101#define DIV_KFC0 0x28500
81 102
103/* list of PLLs */
104enum exynos5420_plls {
105 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
106 bpll, kpll,
107 nr_plls /* number of PLLs */
108};
109
82enum exynos5420_clks { 110enum exynos5420_clks {
83 none, 111 none,
84 112
85 /* core clocks */ 113 /* core clocks */
86 fin_pll, 114 fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
115 fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
87 116
88 /* gate for special clocks (sclk) */ 117 /* gate for special clocks (sclk) */
89 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0, 118 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
@@ -91,7 +120,7 @@ enum exynos5420_clks {
91 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel, 120 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
92 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0, 121 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
93 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro, 122 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
94 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, 123 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
95 124
96 /* gate clocks */ 125 /* gate clocks */
97 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3, 126 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
@@ -109,7 +138,13 @@ enum exynos5420_clks {
109 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, 138 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
110 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0, 139 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
111 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, 140 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
112 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, 141 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
142
143 /* mux clocks */
144 mout_hdmi = 640,
145
146 /* divider clocks */
147 dout_pixel = 768,
113 148
114 nr_clks, 149 nr_clks,
115}; 150};
@@ -118,7 +153,7 @@ enum exynos5420_clks {
118 * list of controller registers to be saved and restored during a 153 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle. 154 * suspend/resume cycle.
120 */ 155 */
121static __initdata unsigned long exynos5420_clk_regs[] = { 156static unsigned long exynos5420_clk_regs[] __initdata = {
122 SRC_CPU, 157 SRC_CPU,
123 DIV_CPU0, 158 DIV_CPU0,
124 DIV_CPU1, 159 DIV_CPU1,
@@ -257,29 +292,29 @@ PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
257 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 292 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
258PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 293PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
259 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 294 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
260PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" }; 295PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" };
261PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 296PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
262 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 297 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
263 298
264/* fixed rate clocks generated outside the soc */ 299/* fixed rate clocks generated outside the soc */
265struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
266 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 301 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
267}; 302};
268 303
269/* fixed rate clocks generated inside the soc */ 304/* fixed rate clocks generated inside the soc */
270struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 305static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
271 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 306 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
272 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 307 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
273 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 308 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
274 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 309 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
275 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 310 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
276}; 311};
277 312
278struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
279 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 314 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
280}; 315};
281 316
282struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
283 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 318 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
284 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 319 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
285 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), 320 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
@@ -371,7 +406,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
371 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 406 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
372 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 407 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
373 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 408 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
374 MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 409 MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
375 410
376 /* MAU Block */ 411 /* MAU Block */
377 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 412 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
@@ -399,7 +434,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
399 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 434 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
400}; 435};
401 436
402struct samsung_div_clock exynos5420_div_clks[] __initdata = { 437static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
403 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 438 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
404 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 439 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
405 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3), 440 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
@@ -431,7 +466,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = {
431 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 466 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
432 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 467 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
433 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 468 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
434 DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 469 DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
435 470
436 /* Audio Block */ 471 /* Audio Block */
437 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 472 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -479,7 +514,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = {
479 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 514 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
480}; 515};
481 516
482struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
483 /* TODO: Re-verify the CG bits for all the gate clocks */ 518 /* TODO: Re-verify the CG bits for all the gate clocks */
484 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), 519 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
485 520
@@ -696,19 +731,43 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
696 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), 731 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
697 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), 732 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
698 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), 733 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
734 GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
699}; 735};
700 736
701static __initdata struct of_device_id ext_clk_match[] = { 737static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
738 [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
739 APLL_CON0, NULL),
740 [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
741 MPLL_CON0, NULL),
742 [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK,
743 DPLL_CON0, NULL),
744 [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
745 EPLL_CON0, NULL),
746 [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK,
747 RPLL_CON0, NULL),
748 [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK,
749 IPLL_CON0, NULL),
750 [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK,
751 SPLL_CON0, NULL),
752 [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK,
753 VPLL_CON0, NULL),
754 [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
755 MPLL_CON0, NULL),
756 [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
757 BPLL_CON0, NULL),
758 [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK,
759 KPLL_CON0, NULL),
760};
761
762static struct of_device_id ext_clk_match[] __initdata = {
702 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 763 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
703 { }, 764 { },
704}; 765};
705 766
706/* register exynos5420 clocks */ 767/* register exynos5420 clocks */
707void __init exynos5420_clk_init(struct device_node *np) 768static void __init exynos5420_clk_init(struct device_node *np)
708{ 769{
709 void __iomem *reg_base; 770 void __iomem *reg_base;
710 struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
711 struct clk *rpll, *spll, *vpll;
712 771
713 if (np) { 772 if (np) {
714 reg_base = of_iomap(np, 0); 773 reg_base = of_iomap(np, 0);
@@ -724,30 +783,8 @@ void __init exynos5420_clk_init(struct device_node *np)
724 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 783 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
725 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 784 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
726 ext_clk_match); 785 ext_clk_match);
727 786 samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
728 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", 787 reg_base);
729 reg_base + 0x100);
730 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
731 reg_base + 0x20110);
732 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
733 reg_base + 0x10120);
734 dpll = samsung_clk_register_pll35xx("fout_dpll", "fin_pll",
735 reg_base + 0x10128);
736 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
737 reg_base + 0x10130);
738 ipll = samsung_clk_register_pll35xx("fout_ipll", "fin_pll",
739 reg_base + 0x10150);
740 kpll = samsung_clk_register_pll35xx("fout_kpll", "fin_pll",
741 reg_base + 0x28100);
742 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
743 reg_base + 0x10180);
744 rpll = samsung_clk_register_pll36xx("fout_rpll", "fin_pll",
745 reg_base + 0x10140);
746 spll = samsung_clk_register_pll35xx("fout_spll", "fin_pll",
747 reg_base + 0x10160);
748 vpll = samsung_clk_register_pll35xx("fout_vpll", "fin_pll",
749 reg_base + 0x10170);
750
751 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, 788 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
752 ARRAY_SIZE(exynos5420_fixed_rate_clks)); 789 ARRAY_SIZE(exynos5420_fixed_rate_clks));
753 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, 790 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index 7d5434167a96..f8658945bfd2 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -41,12 +41,12 @@ PNAME(mout_armclk_p) = { "cplla", "cpllb" };
41PNAME(mout_spi_p) = { "div125", "div200" }; 41PNAME(mout_spi_p) = { "div125", "div200" };
42 42
43/* fixed rate clocks generated outside the soc */ 43/* fixed rate clocks generated outside the soc */
44struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { 44static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
45 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0), 45 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
46}; 46};
47 47
48/* fixed rate clocks */ 48/* fixed rate clocks */
49struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { 49static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
50 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000), 50 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
51 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), 51 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
52 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), 52 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
@@ -55,26 +55,26 @@ struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
55}; 55};
56 56
57/* fixed factor clocks */ 57/* fixed factor clocks */
58struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { 58static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
59 FFACTOR(none, "div250", "ppll", 1, 4, 0), 59 FFACTOR(none, "div250", "ppll", 1, 4, 0),
60 FFACTOR(none, "div200", "ppll", 1, 5, 0), 60 FFACTOR(none, "div200", "ppll", 1, 5, 0),
61 FFACTOR(none, "div125", "div250", 1, 2, 0), 61 FFACTOR(none, "div125", "div250", 1, 2, 0),
62}; 62};
63 63
64/* mux clocks */ 64/* mux clocks */
65struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { 65static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
66 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), 66 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
67 MUX_A(arm_clk, "arm_clk", mout_armclk_p, 67 MUX_A(arm_clk, "arm_clk", mout_armclk_p,
68 CPU_CLK_STATUS, 0, 1, "armclk"), 68 CPU_CLK_STATUS, 0, 1, "armclk"),
69}; 69};
70 70
71/* divider clocks */ 71/* divider clocks */
72struct samsung_div_clock exynos5440_div_clks[] __initdata = { 72static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
73 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), 73 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
74}; 74};
75 75
76/* gate clocks */ 76/* gate clocks */
77struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { 77static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
78 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), 78 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
79 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), 79 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
80 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), 80 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
@@ -97,13 +97,13 @@ struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
97 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 97 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
98}; 98};
99 99
100static __initdata struct of_device_id ext_clk_match[] = { 100static struct of_device_id ext_clk_match[] __initdata = {
101 { .compatible = "samsung,clock-xtal", .data = (void *)0, }, 101 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
102 {}, 102 {},
103}; 103};
104 104
105/* register exynos5440 clocks */ 105/* register exynos5440 clocks */
106void __init exynos5440_clk_init(struct device_node *np) 106static void __init exynos5440_clk_init(struct device_node *np)
107{ 107{
108 void __iomem *reg_base; 108 void __iomem *reg_base;
109 109
@@ -132,7 +132,7 @@ void __init exynos5440_clk_init(struct device_node *np)
132 samsung_clk_register_gate(exynos5440_gate_clks, 132 samsung_clk_register_gate(exynos5440_gate_clks,
133 ARRAY_SIZE(exynos5440_gate_clks)); 133 ARRAY_SIZE(exynos5440_gate_clks));
134 134
135 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk")); 135 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
136 pr_info("exynos5440 clock initialization complete\n"); 136 pr_info("exynos5440 clock initialization complete\n");
137} 137}
138CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init); 138CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 362f12dcd944..529e11dc2c6b 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,31 +10,73 @@
10*/ 10*/
11 11
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/hrtimer.h>
13#include "clk.h" 14#include "clk.h"
14#include "clk-pll.h" 15#include "clk-pll.h"
15 16
17#define PLL_TIMEOUT_MS 10
18
19struct samsung_clk_pll {
20 struct clk_hw hw;
21 void __iomem *lock_reg;
22 void __iomem *con_reg;
23 enum samsung_pll_type type;
24 unsigned int rate_count;
25 const struct samsung_pll_rate_table *rate_table;
26};
27
28#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
29
30static const struct samsung_pll_rate_table *samsung_get_pll_settings(
31 struct samsung_clk_pll *pll, unsigned long rate)
32{
33 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
34 int i;
35
36 for (i = 0; i < pll->rate_count; i++) {
37 if (rate == rate_table[i].rate)
38 return &rate_table[i];
39 }
40
41 return NULL;
42}
43
44static long samsung_pll_round_rate(struct clk_hw *hw,
45 unsigned long drate, unsigned long *prate)
46{
47 struct samsung_clk_pll *pll = to_clk_pll(hw);
48 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
49 int i;
50
51 /* Assumming rate_table is in descending order */
52 for (i = 0; i < pll->rate_count; i++) {
53 if (drate >= rate_table[i].rate)
54 return rate_table[i].rate;
55 }
56
57 /* return minimum supported value */
58 return rate_table[i - 1].rate;
59}
60
16/* 61/*
17 * PLL35xx Clock Type 62 * PLL35xx Clock Type
18 */ 63 */
64/* Maximum lock time can be 270 * PDIV cycles */
65#define PLL35XX_LOCK_FACTOR (270)
19 66
20#define PLL35XX_MDIV_MASK (0x3FF) 67#define PLL35XX_MDIV_MASK (0x3FF)
21#define PLL35XX_PDIV_MASK (0x3F) 68#define PLL35XX_PDIV_MASK (0x3F)
22#define PLL35XX_SDIV_MASK (0x7) 69#define PLL35XX_SDIV_MASK (0x7)
70#define PLL35XX_LOCK_STAT_MASK (0x1)
23#define PLL35XX_MDIV_SHIFT (16) 71#define PLL35XX_MDIV_SHIFT (16)
24#define PLL35XX_PDIV_SHIFT (8) 72#define PLL35XX_PDIV_SHIFT (8)
25#define PLL35XX_SDIV_SHIFT (0) 73#define PLL35XX_SDIV_SHIFT (0)
26 74#define PLL35XX_LOCK_STAT_SHIFT (29)
27struct samsung_clk_pll35xx {
28 struct clk_hw hw;
29 const void __iomem *con_reg;
30};
31
32#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
33 75
34static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, 76static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate) 77 unsigned long parent_rate)
36{ 78{
37 struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw); 79 struct samsung_clk_pll *pll = to_clk_pll(hw);
38 u32 mdiv, pdiv, sdiv, pll_con; 80 u32 mdiv, pdiv, sdiv, pll_con;
39 u64 fvco = parent_rate; 81 u64 fvco = parent_rate;
40 82
@@ -49,48 +91,80 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
49 return (unsigned long)fvco; 91 return (unsigned long)fvco;
50} 92}
51 93
52static const struct clk_ops samsung_pll35xx_clk_ops = { 94static inline bool samsung_pll35xx_mp_change(
53 .recalc_rate = samsung_pll35xx_recalc_rate, 95 const struct samsung_pll_rate_table *rate, u32 pll_con)
54};
55
56struct clk * __init samsung_clk_register_pll35xx(const char *name,
57 const char *pname, const void __iomem *con_reg)
58{ 96{
59 struct samsung_clk_pll35xx *pll; 97 u32 old_mdiv, old_pdiv;
60 struct clk *clk;
61 struct clk_init_data init;
62 98
63 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 99 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
64 if (!pll) { 100 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
65 pr_err("%s: could not allocate pll clk %s\n", __func__, name); 101
66 return NULL; 102 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
103}
104
105static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
106 unsigned long prate)
107{
108 struct samsung_clk_pll *pll = to_clk_pll(hw);
109 const struct samsung_pll_rate_table *rate;
110 u32 tmp;
111
112 /* Get required rate settings from table */
113 rate = samsung_get_pll_settings(pll, drate);
114 if (!rate) {
115 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
116 drate, __clk_get_name(hw->clk));
117 return -EINVAL;
67 } 118 }
68 119
69 init.name = name; 120 tmp = __raw_readl(pll->con_reg);
70 init.ops = &samsung_pll35xx_clk_ops;
71 init.flags = CLK_GET_RATE_NOCACHE;
72 init.parent_names = &pname;
73 init.num_parents = 1;
74 121
75 pll->hw.init = &init; 122 if (!(samsung_pll35xx_mp_change(rate, tmp))) {
76 pll->con_reg = con_reg; 123 /* If only s change, change just s value only*/
124 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
125 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
126 __raw_writel(tmp, pll->con_reg);
77 127
78 clk = clk_register(NULL, &pll->hw); 128 return 0;
79 if (IS_ERR(clk)) {
80 pr_err("%s: failed to register pll clock %s\n", __func__,
81 name);
82 kfree(pll);
83 } 129 }
84 130
85 if (clk_register_clkdev(clk, name, NULL)) 131 /* Set PLL lock time. */
86 pr_err("%s: failed to register lookup for %s", __func__, name); 132 __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR,
87 133 pll->lock_reg);
88 return clk; 134
135 /* Change PLL PMS values */
136 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
137 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
138 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
139 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
140 (rate->pdiv << PLL35XX_PDIV_SHIFT) |
141 (rate->sdiv << PLL35XX_SDIV_SHIFT);
142 __raw_writel(tmp, pll->con_reg);
143
144 /* wait_lock_time */
145 do {
146 cpu_relax();
147 tmp = __raw_readl(pll->con_reg);
148 } while (!(tmp & (PLL35XX_LOCK_STAT_MASK
149 << PLL35XX_LOCK_STAT_SHIFT)));
150 return 0;
89} 151}
90 152
153static const struct clk_ops samsung_pll35xx_clk_ops = {
154 .recalc_rate = samsung_pll35xx_recalc_rate,
155 .round_rate = samsung_pll_round_rate,
156 .set_rate = samsung_pll35xx_set_rate,
157};
158
159static const struct clk_ops samsung_pll35xx_clk_min_ops = {
160 .recalc_rate = samsung_pll35xx_recalc_rate,
161};
162
91/* 163/*
92 * PLL36xx Clock Type 164 * PLL36xx Clock Type
93 */ 165 */
166/* Maximum lock time can be 3000 * PDIV cycles */
167#define PLL36XX_LOCK_FACTOR (3000)
94 168
95#define PLL36XX_KDIV_MASK (0xFFFF) 169#define PLL36XX_KDIV_MASK (0xFFFF)
96#define PLL36XX_MDIV_MASK (0x1FF) 170#define PLL36XX_MDIV_MASK (0x1FF)
@@ -99,18 +173,13 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name,
99#define PLL36XX_MDIV_SHIFT (16) 173#define PLL36XX_MDIV_SHIFT (16)
100#define PLL36XX_PDIV_SHIFT (8) 174#define PLL36XX_PDIV_SHIFT (8)
101#define PLL36XX_SDIV_SHIFT (0) 175#define PLL36XX_SDIV_SHIFT (0)
102 176#define PLL36XX_KDIV_SHIFT (0)
103struct samsung_clk_pll36xx { 177#define PLL36XX_LOCK_STAT_SHIFT (29)
104 struct clk_hw hw;
105 const void __iomem *con_reg;
106};
107
108#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
109 178
110static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 179static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate) 180 unsigned long parent_rate)
112{ 181{
113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw); 182 struct samsung_clk_pll *pll = to_clk_pll(hw);
114 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 183 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
115 s16 kdiv; 184 s16 kdiv;
116 u64 fvco = parent_rate; 185 u64 fvco = parent_rate;
@@ -129,68 +198,102 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
129 return (unsigned long)fvco; 198 return (unsigned long)fvco;
130} 199}
131 200
132static const struct clk_ops samsung_pll36xx_clk_ops = { 201static inline bool samsung_pll36xx_mpk_change(
133 .recalc_rate = samsung_pll36xx_recalc_rate, 202 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
134};
135
136struct clk * __init samsung_clk_register_pll36xx(const char *name,
137 const char *pname, const void __iomem *con_reg)
138{ 203{
139 struct samsung_clk_pll36xx *pll; 204 u32 old_mdiv, old_pdiv, old_kdiv;
140 struct clk *clk;
141 struct clk_init_data init;
142 205
143 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 206 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
144 if (!pll) { 207 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
145 pr_err("%s: could not allocate pll clk %s\n", __func__, name); 208 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
146 return NULL; 209
210 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
211 rate->kdiv != old_kdiv);
212}
213
214static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
215 unsigned long parent_rate)
216{
217 struct samsung_clk_pll *pll = to_clk_pll(hw);
218 u32 tmp, pll_con0, pll_con1;
219 const struct samsung_pll_rate_table *rate;
220
221 rate = samsung_get_pll_settings(pll, drate);
222 if (!rate) {
223 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
224 drate, __clk_get_name(hw->clk));
225 return -EINVAL;
147 } 226 }
148 227
149 init.name = name; 228 pll_con0 = __raw_readl(pll->con_reg);
150 init.ops = &samsung_pll36xx_clk_ops; 229 pll_con1 = __raw_readl(pll->con_reg + 4);
151 init.flags = CLK_GET_RATE_NOCACHE;
152 init.parent_names = &pname;
153 init.num_parents = 1;
154 230
155 pll->hw.init = &init; 231 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
156 pll->con_reg = con_reg; 232 /* If only s change, change just s value only*/
233 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
234 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
235 __raw_writel(pll_con0, pll->con_reg);
157 236
158 clk = clk_register(NULL, &pll->hw); 237 return 0;
159 if (IS_ERR(clk)) {
160 pr_err("%s: failed to register pll clock %s\n", __func__,
161 name);
162 kfree(pll);
163 } 238 }
164 239
165 if (clk_register_clkdev(clk, name, NULL)) 240 /* Set PLL lock time. */
166 pr_err("%s: failed to register lookup for %s", __func__, name); 241 __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
167 242
168 return clk; 243 /* Change PLL PMS values */
244 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
245 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
246 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
247 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
248 (rate->pdiv << PLL36XX_PDIV_SHIFT) |
249 (rate->sdiv << PLL36XX_SDIV_SHIFT);
250 __raw_writel(pll_con0, pll->con_reg);
251
252 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
253 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
254 __raw_writel(pll_con1, pll->con_reg + 4);
255
256 /* wait_lock_time */
257 do {
258 cpu_relax();
259 tmp = __raw_readl(pll->con_reg);
260 } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
261
262 return 0;
169} 263}
170 264
265static const struct clk_ops samsung_pll36xx_clk_ops = {
266 .recalc_rate = samsung_pll36xx_recalc_rate,
267 .set_rate = samsung_pll36xx_set_rate,
268 .round_rate = samsung_pll_round_rate,
269};
270
271static const struct clk_ops samsung_pll36xx_clk_min_ops = {
272 .recalc_rate = samsung_pll36xx_recalc_rate,
273};
274
171/* 275/*
172 * PLL45xx Clock Type 276 * PLL45xx Clock Type
173 */ 277 */
278#define PLL4502_LOCK_FACTOR 400
279#define PLL4508_LOCK_FACTOR 240
174 280
175#define PLL45XX_MDIV_MASK (0x3FF) 281#define PLL45XX_MDIV_MASK (0x3FF)
176#define PLL45XX_PDIV_MASK (0x3F) 282#define PLL45XX_PDIV_MASK (0x3F)
177#define PLL45XX_SDIV_MASK (0x7) 283#define PLL45XX_SDIV_MASK (0x7)
284#define PLL45XX_AFC_MASK (0x1F)
178#define PLL45XX_MDIV_SHIFT (16) 285#define PLL45XX_MDIV_SHIFT (16)
179#define PLL45XX_PDIV_SHIFT (8) 286#define PLL45XX_PDIV_SHIFT (8)
180#define PLL45XX_SDIV_SHIFT (0) 287#define PLL45XX_SDIV_SHIFT (0)
288#define PLL45XX_AFC_SHIFT (0)
181 289
182struct samsung_clk_pll45xx { 290#define PLL45XX_ENABLE BIT(31)
183 struct clk_hw hw; 291#define PLL45XX_LOCKED BIT(29)
184 enum pll45xx_type type;
185 const void __iomem *con_reg;
186};
187
188#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
189 292
190static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, 293static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
191 unsigned long parent_rate) 294 unsigned long parent_rate)
192{ 295{
193 struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw); 296 struct samsung_clk_pll *pll = to_clk_pll(hw);
194 u32 mdiv, pdiv, sdiv, pll_con; 297 u32 mdiv, pdiv, sdiv, pll_con;
195 u64 fvco = parent_rate; 298 u64 fvco = parent_rate;
196 299
@@ -208,54 +311,113 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
208 return (unsigned long)fvco; 311 return (unsigned long)fvco;
209} 312}
210 313
211static const struct clk_ops samsung_pll45xx_clk_ops = { 314static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
212 .recalc_rate = samsung_pll45xx_recalc_rate, 315 const struct samsung_pll_rate_table *rate)
213};
214
215struct clk * __init samsung_clk_register_pll45xx(const char *name,
216 const char *pname, const void __iomem *con_reg,
217 enum pll45xx_type type)
218{ 316{
219 struct samsung_clk_pll45xx *pll; 317 u32 old_mdiv, old_pdiv, old_afc;
220 struct clk *clk;
221 struct clk_init_data init;
222 318
223 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 319 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
224 if (!pll) { 320 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
225 pr_err("%s: could not allocate pll clk %s\n", __func__, name); 321 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
226 return NULL; 322
323 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
324 || old_afc != rate->afc);
325}
326
327static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
328 unsigned long prate)
329{
330 struct samsung_clk_pll *pll = to_clk_pll(hw);
331 const struct samsung_pll_rate_table *rate;
332 u32 con0, con1;
333 ktime_t start;
334
335 /* Get required rate settings from table */
336 rate = samsung_get_pll_settings(pll, drate);
337 if (!rate) {
338 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
339 drate, __clk_get_name(hw->clk));
340 return -EINVAL;
227 } 341 }
228 342
229 init.name = name; 343 con0 = __raw_readl(pll->con_reg);
230 init.ops = &samsung_pll45xx_clk_ops; 344 con1 = __raw_readl(pll->con_reg + 0x4);
231 init.flags = CLK_GET_RATE_NOCACHE;
232 init.parent_names = &pname;
233 init.num_parents = 1;
234 345
235 pll->hw.init = &init; 346 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
236 pll->con_reg = con_reg; 347 /* If only s change, change just s value only*/
237 pll->type = type; 348 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
349 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
350 __raw_writel(con0, pll->con_reg);
238 351
239 clk = clk_register(NULL, &pll->hw); 352 return 0;
240 if (IS_ERR(clk)) {
241 pr_err("%s: failed to register pll clock %s\n", __func__,
242 name);
243 kfree(pll);
244 } 353 }
245 354
246 if (clk_register_clkdev(clk, name, NULL)) 355 /* Set PLL PMS values. */
247 pr_err("%s: failed to register lookup for %s", __func__, name); 356 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
357 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
358 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
359 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
360 (rate->pdiv << PLL45XX_PDIV_SHIFT) |
361 (rate->sdiv << PLL45XX_SDIV_SHIFT);
362
363 /* Set PLL AFC value. */
364 con1 = __raw_readl(pll->con_reg + 0x4);
365 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
366 con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
367
368 /* Set PLL lock time. */
369 switch (pll->type) {
370 case pll_4502:
371 __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
372 break;
373 case pll_4508:
374 __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
375 break;
376 default:
377 break;
378 };
379
380 /* Set new configuration. */
381 __raw_writel(con1, pll->con_reg + 0x4);
382 __raw_writel(con0, pll->con_reg);
383
384 /* Wait for locking. */
385 start = ktime_get();
386 while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
387 ktime_t delta = ktime_sub(ktime_get(), start);
388
389 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
390 pr_err("%s: could not lock PLL %s\n",
391 __func__, __clk_get_name(hw->clk));
392 return -EFAULT;
393 }
394
395 cpu_relax();
396 }
248 397
249 return clk; 398 return 0;
250} 399}
251 400
401static const struct clk_ops samsung_pll45xx_clk_ops = {
402 .recalc_rate = samsung_pll45xx_recalc_rate,
403 .round_rate = samsung_pll_round_rate,
404 .set_rate = samsung_pll45xx_set_rate,
405};
406
407static const struct clk_ops samsung_pll45xx_clk_min_ops = {
408 .recalc_rate = samsung_pll45xx_recalc_rate,
409};
410
252/* 411/*
253 * PLL46xx Clock Type 412 * PLL46xx Clock Type
254 */ 413 */
414#define PLL46XX_LOCK_FACTOR 3000
255 415
416#define PLL46XX_VSEL_MASK (1)
256#define PLL46XX_MDIV_MASK (0x1FF) 417#define PLL46XX_MDIV_MASK (0x1FF)
257#define PLL46XX_PDIV_MASK (0x3F) 418#define PLL46XX_PDIV_MASK (0x3F)
258#define PLL46XX_SDIV_MASK (0x7) 419#define PLL46XX_SDIV_MASK (0x7)
420#define PLL46XX_VSEL_SHIFT (27)
259#define PLL46XX_MDIV_SHIFT (16) 421#define PLL46XX_MDIV_SHIFT (16)
260#define PLL46XX_PDIV_SHIFT (8) 422#define PLL46XX_PDIV_SHIFT (8)
261#define PLL46XX_SDIV_SHIFT (0) 423#define PLL46XX_SDIV_SHIFT (0)
@@ -263,19 +425,20 @@ struct clk * __init samsung_clk_register_pll45xx(const char *name,
263#define PLL46XX_KDIV_MASK (0xFFFF) 425#define PLL46XX_KDIV_MASK (0xFFFF)
264#define PLL4650C_KDIV_MASK (0xFFF) 426#define PLL4650C_KDIV_MASK (0xFFF)
265#define PLL46XX_KDIV_SHIFT (0) 427#define PLL46XX_KDIV_SHIFT (0)
428#define PLL46XX_MFR_MASK (0x3F)
429#define PLL46XX_MRR_MASK (0x1F)
430#define PLL46XX_KDIV_SHIFT (0)
431#define PLL46XX_MFR_SHIFT (16)
432#define PLL46XX_MRR_SHIFT (24)
266 433
267struct samsung_clk_pll46xx { 434#define PLL46XX_ENABLE BIT(31)
268 struct clk_hw hw; 435#define PLL46XX_LOCKED BIT(29)
269 enum pll46xx_type type; 436#define PLL46XX_VSEL BIT(27)
270 const void __iomem *con_reg;
271};
272
273#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
274 437
275static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, 438static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
276 unsigned long parent_rate) 439 unsigned long parent_rate)
277{ 440{
278 struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw); 441 struct samsung_clk_pll *pll = to_clk_pll(hw);
279 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; 442 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
280 u64 fvco = parent_rate; 443 u64 fvco = parent_rate;
281 444
@@ -295,47 +458,175 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
295 return (unsigned long)fvco; 458 return (unsigned long)fvco;
296} 459}
297 460
461static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
462 const struct samsung_pll_rate_table *rate)
463{
464 u32 old_mdiv, old_pdiv, old_kdiv;
465
466 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
467 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
468 old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
469
470 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
471 || old_kdiv != rate->kdiv);
472}
473
474static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
475 unsigned long prate)
476{
477 struct samsung_clk_pll *pll = to_clk_pll(hw);
478 const struct samsung_pll_rate_table *rate;
479 u32 con0, con1, lock;
480 ktime_t start;
481
482 /* Get required rate settings from table */
483 rate = samsung_get_pll_settings(pll, drate);
484 if (!rate) {
485 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
486 drate, __clk_get_name(hw->clk));
487 return -EINVAL;
488 }
489
490 con0 = __raw_readl(pll->con_reg);
491 con1 = __raw_readl(pll->con_reg + 0x4);
492
493 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
494 /* If only s change, change just s value only*/
495 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
496 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
497 __raw_writel(con0, pll->con_reg);
498
499 return 0;
500 }
501
502 /* Set PLL lock time. */
503 lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
504 if (lock > 0xffff)
505 /* Maximum lock time bitfield is 16-bit. */
506 lock = 0xffff;
507
508 /* Set PLL PMS and VSEL values. */
509 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
510 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
511 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
512 (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
513 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
514 (rate->pdiv << PLL46XX_PDIV_SHIFT) |
515 (rate->sdiv << PLL46XX_SDIV_SHIFT) |
516 (rate->vsel << PLL46XX_VSEL_SHIFT);
517
518 /* Set PLL K, MFR and MRR values. */
519 con1 = __raw_readl(pll->con_reg + 0x4);
520 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
521 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
522 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
523 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
524 (rate->mfr << PLL46XX_MFR_SHIFT) |
525 (rate->mrr << PLL46XX_MRR_SHIFT);
526
527 /* Write configuration to PLL */
528 __raw_writel(lock, pll->lock_reg);
529 __raw_writel(con0, pll->con_reg);
530 __raw_writel(con1, pll->con_reg + 0x4);
531
532 /* Wait for locking. */
533 start = ktime_get();
534 while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) {
535 ktime_t delta = ktime_sub(ktime_get(), start);
536
537 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
538 pr_err("%s: could not lock PLL %s\n",
539 __func__, __clk_get_name(hw->clk));
540 return -EFAULT;
541 }
542
543 cpu_relax();
544 }
545
546 return 0;
547}
548
298static const struct clk_ops samsung_pll46xx_clk_ops = { 549static const struct clk_ops samsung_pll46xx_clk_ops = {
299 .recalc_rate = samsung_pll46xx_recalc_rate, 550 .recalc_rate = samsung_pll46xx_recalc_rate,
551 .round_rate = samsung_pll_round_rate,
552 .set_rate = samsung_pll46xx_set_rate,
553};
554
555static const struct clk_ops samsung_pll46xx_clk_min_ops = {
556 .recalc_rate = samsung_pll46xx_recalc_rate,
300}; 557};
301 558
302struct clk * __init samsung_clk_register_pll46xx(const char *name, 559/*
303 const char *pname, const void __iomem *con_reg, 560 * PLL6552 Clock Type
304 enum pll46xx_type type) 561 */
562
563#define PLL6552_MDIV_MASK 0x3ff
564#define PLL6552_PDIV_MASK 0x3f
565#define PLL6552_SDIV_MASK 0x7
566#define PLL6552_MDIV_SHIFT 16
567#define PLL6552_PDIV_SHIFT 8
568#define PLL6552_SDIV_SHIFT 0
569
570static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
571 unsigned long parent_rate)
305{ 572{
306 struct samsung_clk_pll46xx *pll; 573 struct samsung_clk_pll *pll = to_clk_pll(hw);
307 struct clk *clk; 574 u32 mdiv, pdiv, sdiv, pll_con;
308 struct clk_init_data init; 575 u64 fvco = parent_rate;
309 576
310 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 577 pll_con = __raw_readl(pll->con_reg);
311 if (!pll) { 578 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
312 pr_err("%s: could not allocate pll clk %s\n", __func__, name); 579 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
313 return NULL; 580 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
314 }
315 581
316 init.name = name; 582 fvco *= mdiv;
317 init.ops = &samsung_pll46xx_clk_ops; 583 do_div(fvco, (pdiv << sdiv));
318 init.flags = CLK_GET_RATE_NOCACHE;
319 init.parent_names = &pname;
320 init.num_parents = 1;
321 584
322 pll->hw.init = &init; 585 return (unsigned long)fvco;
323 pll->con_reg = con_reg; 586}
324 pll->type = type;
325 587
326 clk = clk_register(NULL, &pll->hw); 588static const struct clk_ops samsung_pll6552_clk_ops = {
327 if (IS_ERR(clk)) { 589 .recalc_rate = samsung_pll6552_recalc_rate,
328 pr_err("%s: failed to register pll clock %s\n", __func__, 590};
329 name);
330 kfree(pll);
331 }
332 591
333 if (clk_register_clkdev(clk, name, NULL)) 592/*
334 pr_err("%s: failed to register lookup for %s", __func__, name); 593 * PLL6553 Clock Type
594 */
335 595
336 return clk; 596#define PLL6553_MDIV_MASK 0xff
597#define PLL6553_PDIV_MASK 0x3f
598#define PLL6553_SDIV_MASK 0x7
599#define PLL6553_KDIV_MASK 0xffff
600#define PLL6553_MDIV_SHIFT 16
601#define PLL6553_PDIV_SHIFT 8
602#define PLL6553_SDIV_SHIFT 0
603#define PLL6553_KDIV_SHIFT 0
604
605static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
606 unsigned long parent_rate)
607{
608 struct samsung_clk_pll *pll = to_clk_pll(hw);
609 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
610 u64 fvco = parent_rate;
611
612 pll_con0 = __raw_readl(pll->con_reg);
613 pll_con1 = __raw_readl(pll->con_reg + 0x4);
614 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
615 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
616 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
617 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
618
619 fvco *= (mdiv << 16) + kdiv;
620 do_div(fvco, (pdiv << sdiv));
621 fvco >>= 16;
622
623 return (unsigned long)fvco;
337} 624}
338 625
626static const struct clk_ops samsung_pll6553_clk_ops = {
627 .recalc_rate = samsung_pll6553_recalc_rate,
628};
629
339/* 630/*
340 * PLL2550x Clock Type 631 * PLL2550x Clock Type
341 */ 632 */
@@ -418,3 +709,117 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
418 709
419 return clk; 710 return clk;
420} 711}
712
713static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
714 void __iomem *base)
715{
716 struct samsung_clk_pll *pll;
717 struct clk *clk;
718 struct clk_init_data init;
719 int ret, len;
720
721 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
722 if (!pll) {
723 pr_err("%s: could not allocate pll clk %s\n",
724 __func__, pll_clk->name);
725 return;
726 }
727
728 init.name = pll_clk->name;
729 init.flags = pll_clk->flags;
730 init.parent_names = &pll_clk->parent_name;
731 init.num_parents = 1;
732
733 if (pll_clk->rate_table) {
734 /* find count of rates in rate_table */
735 for (len = 0; pll_clk->rate_table[len].rate != 0; )
736 len++;
737
738 pll->rate_count = len;
739 pll->rate_table = kmemdup(pll_clk->rate_table,
740 pll->rate_count *
741 sizeof(struct samsung_pll_rate_table),
742 GFP_KERNEL);
743 WARN(!pll->rate_table,
744 "%s: could not allocate rate table for %s\n",
745 __func__, pll_clk->name);
746 }
747
748 switch (pll_clk->type) {
749 /* clk_ops for 35xx and 2550 are similar */
750 case pll_35xx:
751 case pll_2550:
752 if (!pll->rate_table)
753 init.ops = &samsung_pll35xx_clk_min_ops;
754 else
755 init.ops = &samsung_pll35xx_clk_ops;
756 break;
757 case pll_4500:
758 init.ops = &samsung_pll45xx_clk_min_ops;
759 break;
760 case pll_4502:
761 case pll_4508:
762 if (!pll->rate_table)
763 init.ops = &samsung_pll45xx_clk_min_ops;
764 else
765 init.ops = &samsung_pll45xx_clk_ops;
766 break;
767 /* clk_ops for 36xx and 2650 are similar */
768 case pll_36xx:
769 case pll_2650:
770 if (!pll->rate_table)
771 init.ops = &samsung_pll36xx_clk_min_ops;
772 else
773 init.ops = &samsung_pll36xx_clk_ops;
774 break;
775 case pll_6552:
776 init.ops = &samsung_pll6552_clk_ops;
777 break;
778 case pll_6553:
779 init.ops = &samsung_pll6553_clk_ops;
780 break;
781 case pll_4600:
782 case pll_4650:
783 case pll_4650c:
784 if (!pll->rate_table)
785 init.ops = &samsung_pll46xx_clk_min_ops;
786 else
787 init.ops = &samsung_pll46xx_clk_ops;
788 break;
789 default:
790 pr_warn("%s: Unknown pll type for pll clk %s\n",
791 __func__, pll_clk->name);
792 }
793
794 pll->hw.init = &init;
795 pll->type = pll_clk->type;
796 pll->lock_reg = base + pll_clk->lock_offset;
797 pll->con_reg = base + pll_clk->con_offset;
798
799 clk = clk_register(NULL, &pll->hw);
800 if (IS_ERR(clk)) {
801 pr_err("%s: failed to register pll clock %s : %ld\n",
802 __func__, pll_clk->name, PTR_ERR(clk));
803 kfree(pll);
804 return;
805 }
806
807 samsung_clk_add_lookup(clk, pll_clk->id);
808
809 if (!pll_clk->alias)
810 return;
811
812 ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name);
813 if (ret)
814 pr_err("%s: failed to register lookup for %s : %d",
815 __func__, pll_clk->name, ret);
816}
817
818void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
819 unsigned int nr_pll, void __iomem *base)
820{
821 int cnt;
822
823 for (cnt = 0; cnt < nr_pll; cnt++)
824 _samsung_clk_register_pll(&pll_list[cnt], base);
825}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index f33786e9a78b..6c39030080fb 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -12,28 +12,83 @@
12#ifndef __SAMSUNG_CLK_PLL_H 12#ifndef __SAMSUNG_CLK_PLL_H
13#define __SAMSUNG_CLK_PLL_H 13#define __SAMSUNG_CLK_PLL_H
14 14
15enum pll45xx_type { 15enum samsung_pll_type {
16 pll_35xx,
17 pll_36xx,
18 pll_2550,
19 pll_2650,
16 pll_4500, 20 pll_4500,
17 pll_4502, 21 pll_4502,
18 pll_4508 22 pll_4508,
19};
20
21enum pll46xx_type {
22 pll_4600, 23 pll_4600,
23 pll_4650, 24 pll_4650,
24 pll_4650c, 25 pll_4650c,
26 pll_6552,
27 pll_6553,
28};
29
30#define PLL_35XX_RATE(_rate, _m, _p, _s) \
31 { \
32 .rate = (_rate), \
33 .mdiv = (_m), \
34 .pdiv = (_p), \
35 .sdiv = (_s), \
36 }
37
38#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
39 { \
40 .rate = (_rate), \
41 .mdiv = (_m), \
42 .pdiv = (_p), \
43 .sdiv = (_s), \
44 .kdiv = (_k), \
45 }
46
47#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \
48 { \
49 .rate = (_rate), \
50 .mdiv = (_m), \
51 .pdiv = (_p), \
52 .sdiv = (_s), \
53 .afc = (_afc), \
54 }
55
56#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \
57 { \
58 .rate = (_rate), \
59 .mdiv = (_m), \
60 .pdiv = (_p), \
61 .sdiv = (_s), \
62 .kdiv = (_k), \
63 .vsel = (_vsel), \
64 }
65
66#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
67 { \
68 .rate = (_rate), \
69 .mdiv = (_m), \
70 .pdiv = (_p), \
71 .sdiv = (_s), \
72 .kdiv = (_k), \
73 .mfr = (_mfr), \
74 .mrr = (_mrr), \
75 .vsel = (_vsel), \
76 }
77
78/* NOTE: Rate table should be kept sorted in descending order. */
79
80struct samsung_pll_rate_table {
81 unsigned int rate;
82 unsigned int pdiv;
83 unsigned int mdiv;
84 unsigned int sdiv;
85 unsigned int kdiv;
86 unsigned int afc;
87 unsigned int mfr;
88 unsigned int mrr;
89 unsigned int vsel;
25}; 90};
26 91
27extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
28 const char *pname, const void __iomem *con_reg);
29extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
30 const char *pname, const void __iomem *con_reg);
31extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
32 const char *pname, const void __iomem *con_reg,
33 enum pll45xx_type type);
34extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
35 const char *pname, const void __iomem *con_reg,
36 enum pll46xx_type type);
37extern struct clk * __init samsung_clk_register_pll2550x(const char *name, 92extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
38 const char *pname, const void __iomem *reg_base, 93 const char *pname, const void __iomem *reg_base,
39 const unsigned long offset); 94 const unsigned long offset);
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
new file mode 100644
index 000000000000..7d2c84265947
--- /dev/null
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -0,0 +1,473 @@
1/*
2 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for all S3C64xx SoCs.
9*/
10
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22/* S3C64xx clock controller register offsets. */
23#define APLL_LOCK 0x000
24#define MPLL_LOCK 0x004
25#define EPLL_LOCK 0x008
26#define APLL_CON 0x00c
27#define MPLL_CON 0x010
28#define EPLL_CON0 0x014
29#define EPLL_CON1 0x018
30#define CLK_SRC 0x01c
31#define CLK_DIV0 0x020
32#define CLK_DIV1 0x024
33#define CLK_DIV2 0x028
34#define HCLK_GATE 0x030
35#define PCLK_GATE 0x034
36#define SCLK_GATE 0x038
37#define MEM0_GATE 0x03c
38#define CLK_SRC2 0x10c
39#define OTHERS 0x900
40
41/* Helper macros to define clock arrays. */
42#define FIXED_RATE_CLOCKS(name) \
43 static struct samsung_fixed_rate_clock name[]
44#define MUX_CLOCKS(name) \
45 static struct samsung_mux_clock name[]
46#define DIV_CLOCKS(name) \
47 static struct samsung_div_clock name[]
48#define GATE_CLOCKS(name) \
49 static struct samsung_gate_clock name[]
50
51/* Helper macros for gate types present on S3C64xx. */
52#define GATE_BUS(_id, cname, pname, o, b) \
53 GATE(_id, cname, pname, o, b, 0, 0)
54#define GATE_SCLK(_id, cname, pname, o, b) \
55 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
56#define GATE_ON(_id, cname, pname, o, b) \
57 GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
58
59/* list of PLLs to be registered */
60enum s3c64xx_plls {
61 apll, mpll, epll,
62};
63
64/*
65 * List of controller registers to be saved and restored during
66 * a suspend/resume cycle.
67 */
68static unsigned long s3c64xx_clk_regs[] __initdata = {
69 APLL_LOCK,
70 MPLL_LOCK,
71 EPLL_LOCK,
72 APLL_CON,
73 MPLL_CON,
74 EPLL_CON0,
75 EPLL_CON1,
76 CLK_SRC,
77 CLK_DIV0,
78 CLK_DIV1,
79 CLK_DIV2,
80 HCLK_GATE,
81 PCLK_GATE,
82 SCLK_GATE,
83};
84
85static unsigned long s3c6410_clk_regs[] __initdata = {
86 CLK_SRC2,
87 MEM0_GATE,
88};
89
90/* List of parent clocks common for all S3C64xx SoCs. */
91PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
92PNAME(uart_p) = { "mout_epll", "dout_mpll" };
93PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
94 "pcmcdclk0", "none", "none", "none" };
95PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
96 "pcmcdclk0", "none", "none", "none" };
97PNAME(mfc_p) = { "hclkx2", "mout_epll" };
98PNAME(apll_p) = { "fin_pll", "fout_apll" };
99PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
100PNAME(epll_p) = { "fin_pll", "fout_epll" };
101PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
102
103/* S3C6400-specific parent clocks. */
104PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
105PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
106PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
107
108/* S3C6410-specific parent clocks. */
109PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
110PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
111PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
112PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
113PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
114 "pcmcdclk1", "none", "none", "none" };
115
116/* Fixed rate clocks generated outside the SoC. */
117FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
118 FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0),
119 FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0),
120};
121
122/* Fixed rate clocks generated inside the SoC. */
123FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
124 FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000),
125 FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000),
126};
127
128/* List of clock muxes present on all S3C64xx SoCs. */
129MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
130 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
131 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
132 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
133 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
134 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
135 MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
136 MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
137 MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
138 MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
139 MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
140 MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
141 MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
142 MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
143};
144
145/* List of clock muxes present on S3C6400. */
146MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
147 MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
148 MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
149 MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
150 MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
151};
152
153/* List of clock muxes present on S3C6410. */
154MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
155 MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
156 MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
157 MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
158 MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
159 MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
160 MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
161 MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
162};
163
164/* List of clock dividers present on all S3C64xx SoCs. */
165DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
166 DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
167 DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
168 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
169 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
170 DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
171 DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
172 DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
173 DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
174 DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
175 DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
176 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
177 DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
178 DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
179 DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
180 DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
181 DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
182 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
183 DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
184 DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
185 DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
186};
187
188/* List of clock dividers present on S3C6400. */
189DIV_CLOCKS(s3c6400_div_clks) __initdata = {
190 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
191};
192
193/* List of clock dividers present on S3C6410. */
194DIV_CLOCKS(s3c6410_div_clks) __initdata = {
195 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
196 DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
197 DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
198};
199
200/* List of clock gates present on all S3C64xx SoCs. */
201GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
202 GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
203 GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
204 GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
205 GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
206 GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
207 GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
208 GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
209 GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
210 GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
211 GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
212 GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
213 GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
214 GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
215 GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
216 GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
217 GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
218 GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
219 GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
220 GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
221 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
222 GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
223 GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
224 GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
225 GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
226 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
227 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
228 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
229 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
230 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
231 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
232 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
233 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
234 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
235 GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
236 GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
237 GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
238 GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
239 GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
240 GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
241 GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
242 GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
243 GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
244 GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
245 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
246 GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
247 GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
248 GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
249 GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
250 GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
251 GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
252 GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
253 GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
254 GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
255 GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
256 GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
257 GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
258 GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
259 GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
260 GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
261 GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
262 GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
263 GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
264 GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
265 GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
266 GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
267 GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
268 GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
269 GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
270 GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
271 GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
272 GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
273 GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
274 GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
275 GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
276 GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
277 GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
278};
279
280/* List of clock gates present on S3C6400. */
281GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
282 GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
283 GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
284};
285
286/* List of clock gates present on S3C6410. */
287GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
288 GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
289 GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
290 GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
291 GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
292 GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
293 GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
294 GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
295 GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
296 GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
297 GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
298 GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
299 GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
300 GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
301 GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
302};
303
304/* List of PLL clocks. */
305static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
306 [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
307 APLL_LOCK, APLL_CON, NULL),
308 [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
309 MPLL_LOCK, MPLL_CON, NULL),
310 [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
311 EPLL_LOCK, EPLL_CON0, NULL),
312};
313
314/* Aliases for common s3c64xx clocks. */
315static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
316 ALIAS(FOUT_APLL, NULL, "fout_apll"),
317 ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
318 ALIAS(FOUT_EPLL, NULL, "fout_epll"),
319 ALIAS(MOUT_EPLL, NULL, "mout_epll"),
320 ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
321 ALIAS(HCLKX2, NULL, "hclk2"),
322 ALIAS(HCLK, NULL, "hclk"),
323 ALIAS(PCLK, NULL, "pclk"),
324 ALIAS(PCLK, NULL, "clk_uart_baud2"),
325 ALIAS(ARMCLK, NULL, "armclk"),
326 ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
327 ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
328 ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
329 ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
330 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
331 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
332 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
333 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
334 ALIAS(HCLK_DMA1, NULL, "dma1"),
335 ALIAS(HCLK_DMA0, NULL, "dma0"),
336 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
337 ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
338 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
339 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
340 ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
341 ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
342 ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
343 ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
344 ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
345 ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
346 ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
347 ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
348 ALIAS(PCLK_PWM, NULL, "timers"),
349 ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
350 ALIAS(PCLK_WDT, NULL, "watchdog"),
351 ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
352 ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
353 ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
354 ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
355 ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
356 ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
357 ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
358 ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
359 ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi-bus"),
360 ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi-bus"),
361 ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
362 ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
363 ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
364 ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
365 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
366 ALIAS(SCLK_CAM, "s3c-camif", "camera"),
367};
368
369/* Aliases for s3c6400-specific clocks. */
370static struct samsung_clock_alias s3c6400_clock_aliases[] = {
371 /* Nothing to place here yet. */
372};
373
374/* Aliases for s3c6410-specific clocks. */
375static struct samsung_clock_alias s3c6410_clock_aliases[] = {
376 ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
377 ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
378 ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
379 ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
380 ALIAS(MEM0_SROM, NULL, "srom"),
381};
382
383static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f,
384 unsigned long xusbxti_f)
385{
386 s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
387 s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
388 samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks,
389 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
390}
391
392/* Register s3c64xx clocks. */
393void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
394 unsigned long xusbxti_f, bool is_s3c6400,
395 void __iomem *reg_base)
396{
397 unsigned long *soc_regs = NULL;
398 unsigned long nr_soc_regs = 0;
399
400 if (np) {
401 reg_base = of_iomap(np, 0);
402 if (!reg_base)
403 panic("%s: failed to map registers\n", __func__);
404 }
405
406 if (!is_s3c6400) {
407 soc_regs = s3c6410_clk_regs;
408 nr_soc_regs = ARRAY_SIZE(s3c6410_clk_regs);
409 }
410
411 samsung_clk_init(np, reg_base, NR_CLKS, s3c64xx_clk_regs,
412 ARRAY_SIZE(s3c64xx_clk_regs), soc_regs, nr_soc_regs);
413
414 /* Register external clocks. */
415 if (!np)
416 s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f);
417
418 /* Register PLLs. */
419 samsung_clk_register_pll(s3c64xx_pll_clks,
420 ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
421
422 /* Register common internal clocks. */
423 samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks,
424 ARRAY_SIZE(s3c64xx_fixed_rate_clks));
425 samsung_clk_register_mux(s3c64xx_mux_clks,
426 ARRAY_SIZE(s3c64xx_mux_clks));
427 samsung_clk_register_div(s3c64xx_div_clks,
428 ARRAY_SIZE(s3c64xx_div_clks));
429 samsung_clk_register_gate(s3c64xx_gate_clks,
430 ARRAY_SIZE(s3c64xx_gate_clks));
431
432 /* Register SoC-specific clocks. */
433 if (is_s3c6400) {
434 samsung_clk_register_mux(s3c6400_mux_clks,
435 ARRAY_SIZE(s3c6400_mux_clks));
436 samsung_clk_register_div(s3c6400_div_clks,
437 ARRAY_SIZE(s3c6400_div_clks));
438 samsung_clk_register_gate(s3c6400_gate_clks,
439 ARRAY_SIZE(s3c6400_gate_clks));
440 samsung_clk_register_alias(s3c6400_clock_aliases,
441 ARRAY_SIZE(s3c6400_clock_aliases));
442 } else {
443 samsung_clk_register_mux(s3c6410_mux_clks,
444 ARRAY_SIZE(s3c6410_mux_clks));
445 samsung_clk_register_div(s3c6410_div_clks,
446 ARRAY_SIZE(s3c6410_div_clks));
447 samsung_clk_register_gate(s3c6410_gate_clks,
448 ARRAY_SIZE(s3c6410_gate_clks));
449 samsung_clk_register_alias(s3c6410_clock_aliases,
450 ARRAY_SIZE(s3c6410_clock_aliases));
451 }
452
453 samsung_clk_register_alias(s3c64xx_clock_aliases,
454 ARRAY_SIZE(s3c64xx_clock_aliases));
455
456 pr_info("%s clocks: apll = %lu, mpll = %lu\n"
457 "\tepll = %lu, arm_clk = %lu\n",
458 is_s3c6400 ? "S3C6400" : "S3C6410",
459 _get_rate("fout_apll"), _get_rate("fout_mpll"),
460 _get_rate("fout_epll"), _get_rate("armclk"));
461}
462
463static void __init s3c6400_clk_init(struct device_node *np)
464{
465 s3c64xx_clk_init(np, 0, 0, true, NULL);
466}
467CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
468
469static void __init s3c6410_clk_init(struct device_node *np)
470{
471 s3c64xx_clk_init(np, 0, 0, false, NULL);
472}
473CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index cd3c40ab50f3..f503f32e2f80 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -307,14 +307,12 @@ void __init samsung_clk_of_register_fixed_ext(
307unsigned long _get_rate(const char *clk_name) 307unsigned long _get_rate(const char *clk_name)
308{ 308{
309 struct clk *clk; 309 struct clk *clk;
310 unsigned long rate;
311 310
312 clk = clk_get(NULL, clk_name); 311 clk = __clk_lookup(clk_name);
313 if (IS_ERR(clk)) { 312 if (!clk) {
314 pr_err("%s: could not find clock %s\n", __func__, clk_name); 313 pr_err("%s: could not find clock %s\n", __func__, clk_name);
315 return 0; 314 return 0;
316 } 315 }
317 rate = clk_get_rate(clk); 316
318 clk_put(clk); 317 return clk_get_rate(clk);
319 return rate;
320} 318}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 2f7dba20ced8..31b4174e7a5b 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -19,6 +19,7 @@
19#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include "clk-pll.h"
22 23
23/** 24/**
24 * struct samsung_clock_alias: information about mux clock 25 * struct samsung_clock_alias: information about mux clock
@@ -39,6 +40,8 @@ struct samsung_clock_alias {
39 .alias = a, \ 40 .alias = a, \
40 } 41 }
41 42
43#define MHZ (1000 * 1000)
44
42/** 45/**
43 * struct samsung_fixed_rate_clock: information about fixed-rate clock 46 * struct samsung_fixed_rate_clock: information about fixed-rate clock
44 * @id: platform specific id of the clock. 47 * @id: platform specific id of the clock.
@@ -127,7 +130,7 @@ struct samsung_mux_clock {
127 .name = cname, \ 130 .name = cname, \
128 .parent_names = pnames, \ 131 .parent_names = pnames, \
129 .num_parents = ARRAY_SIZE(pnames), \ 132 .num_parents = ARRAY_SIZE(pnames), \
130 .flags = f, \ 133 .flags = (f) | CLK_SET_RATE_NO_REPARENT, \
131 .offset = o, \ 134 .offset = o, \
132 .shift = s, \ 135 .shift = s, \
133 .width = w, \ 136 .width = w, \
@@ -261,6 +264,54 @@ struct samsung_clk_reg_dump {
261 u32 value; 264 u32 value;
262}; 265};
263 266
267/**
268 * struct samsung_pll_clock: information about pll clock
269 * @id: platform specific id of the clock.
270 * @dev_name: name of the device to which this clock belongs.
271 * @name: name of this pll clock.
272 * @parent_name: name of the parent clock.
273 * @flags: optional flags for basic clock.
274 * @con_offset: offset of the register for configuring the PLL.
275 * @lock_offset: offset of the register for locking the PLL.
276 * @type: Type of PLL to be registered.
277 * @alias: optional clock alias name to be assigned to this clock.
278 */
279struct samsung_pll_clock {
280 unsigned int id;
281 const char *dev_name;
282 const char *name;
283 const char *parent_name;
284 unsigned long flags;
285 int con_offset;
286 int lock_offset;
287 enum samsung_pll_type type;
288 const struct samsung_pll_rate_table *rate_table;
289 const char *alias;
290};
291
292#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \
293 _rtable, _alias) \
294 { \
295 .id = _id, \
296 .type = _typ, \
297 .dev_name = _dname, \
298 .name = _name, \
299 .parent_name = _pname, \
300 .flags = CLK_GET_RATE_NOCACHE, \
301 .con_offset = _con, \
302 .lock_offset = _lock, \
303 .rate_table = _rtable, \
304 .alias = _alias, \
305 }
306
307#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
308 __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
309 _lock, _con, _rtable, _name)
310
311#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
312 __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
313 _lock, _con, _rtable, _alias)
314
264extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, 315extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
265 unsigned long nr_clks, unsigned long *rdump, 316 unsigned long nr_clks, unsigned long *rdump,
266 unsigned long nr_rdump, unsigned long *soc_rdump, 317 unsigned long nr_rdump, unsigned long *soc_rdump,
@@ -284,6 +335,8 @@ extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
284 unsigned int nr_clk); 335 unsigned int nr_clk);
285extern void __init samsung_clk_register_gate( 336extern void __init samsung_clk_register_gate(
286 struct samsung_gate_clock *clk_list, unsigned int nr_clk); 337 struct samsung_gate_clock *clk_list, unsigned int nr_clk);
338extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
339 unsigned int nr_clk, void __iomem *base);
287 340
288extern unsigned long _get_rate(const char *clk_name); 341extern unsigned long _get_rate(const char *clk_name);
289 342
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index aedbbe12f321..65894f7687ed 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -416,9 +416,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
416 /* clock derived from 24 or 25 MHz osc clk */ 416 /* clock derived from 24 or 25 MHz osc clk */
417 /* vco-pll */ 417 /* vco-pll */
418 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 418 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
419 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 419 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
420 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 420 SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
421 &_lock); 421 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
422 clk_register_clkdev(clk, "vco1_mclk", NULL); 422 clk_register_clkdev(clk, "vco1_mclk", NULL);
423 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 423 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
424 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 424 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
@@ -427,9 +427,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
427 clk_register_clkdev(clk1, "pll1_clk", NULL); 427 clk_register_clkdev(clk1, "pll1_clk", NULL);
428 428
429 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 429 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
430 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 430 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
431 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 431 SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
432 &_lock); 432 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
433 clk_register_clkdev(clk, "vco2_mclk", NULL); 433 clk_register_clkdev(clk, "vco2_mclk", NULL);
434 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 434 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
435 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 435 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
@@ -438,9 +438,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
438 clk_register_clkdev(clk1, "pll2_clk", NULL); 438 clk_register_clkdev(clk1, "pll2_clk", NULL);
439 439
440 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 440 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
441 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 441 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
442 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 442 SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
443 &_lock); 443 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
444 clk_register_clkdev(clk, "vco3_mclk", NULL); 444 clk_register_clkdev(clk, "vco3_mclk", NULL);
445 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 445 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
446 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 446 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
@@ -515,9 +515,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
515 515
516 /* gpt clocks */ 516 /* gpt clocks */
517 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 517 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
518 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 518 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
519 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 519 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
520 &_lock); 520 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
521 clk_register_clkdev(clk, "gpt0_mclk", NULL); 521 clk_register_clkdev(clk, "gpt0_mclk", NULL);
522 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 522 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
523 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 523 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
@@ -525,9 +525,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
525 clk_register_clkdev(clk, NULL, "gpt0"); 525 clk_register_clkdev(clk, NULL, "gpt0");
526 526
527 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 527 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
528 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 528 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
529 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 529 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
530 &_lock); 530 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
531 clk_register_clkdev(clk, "gpt1_mclk", NULL); 531 clk_register_clkdev(clk, "gpt1_mclk", NULL);
532 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 532 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
533 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 533 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
@@ -535,9 +535,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
535 clk_register_clkdev(clk, NULL, "gpt1"); 535 clk_register_clkdev(clk, NULL, "gpt1");
536 536
537 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 537 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
538 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 538 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
539 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 539 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
540 &_lock); 540 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
541 clk_register_clkdev(clk, "gpt2_mclk", NULL); 541 clk_register_clkdev(clk, "gpt2_mclk", NULL);
542 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 542 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
543 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 543 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
@@ -545,9 +545,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
545 clk_register_clkdev(clk, NULL, "gpt2"); 545 clk_register_clkdev(clk, NULL, "gpt2");
546 546
547 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 547 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
548 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 548 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
549 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 549 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
550 &_lock); 550 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
551 clk_register_clkdev(clk, "gpt3_mclk", NULL); 551 clk_register_clkdev(clk, "gpt3_mclk", NULL);
552 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 552 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
553 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 553 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
@@ -562,7 +562,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
562 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 562 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
563 563
564 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 564 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
565 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 565 ARRAY_SIZE(uart0_parents),
566 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
566 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, 567 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
567 SPEAR1310_UART_CLK_MASK, 0, &_lock); 568 SPEAR1310_UART_CLK_MASK, 0, &_lock);
568 clk_register_clkdev(clk, "uart0_mclk", NULL); 569 clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -602,7 +603,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
602 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 603 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
603 604
604 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 605 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
605 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 606 ARRAY_SIZE(c3_parents),
607 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
606 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, 608 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
607 SPEAR1310_C3_CLK_MASK, 0, &_lock); 609 SPEAR1310_C3_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "c3_mclk", NULL); 610 clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -614,8 +616,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
614 616
615 /* gmac */ 617 /* gmac */
616 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 618 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
617 ARRAY_SIZE(gmac_phy_input_parents), 0, 619 ARRAY_SIZE(gmac_phy_input_parents),
618 SPEAR1310_GMAC_CLK_CFG, 620 CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
619 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 621 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
620 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 622 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
621 clk_register_clkdev(clk, "phy_input_mclk", NULL); 623 clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -627,15 +629,16 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
627 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 629 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
628 630
629 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 631 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
630 ARRAY_SIZE(gmac_phy_parents), 0, 632 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
631 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 633 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
632 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 634 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
633 clk_register_clkdev(clk, "stmmacphy.0", NULL); 635 clk_register_clkdev(clk, "stmmacphy.0", NULL);
634 636
635 /* clcd */ 637 /* clcd */
636 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 638 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
637 ARRAY_SIZE(clcd_synth_parents), 0, 639 ARRAY_SIZE(clcd_synth_parents),
638 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, 640 CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
641 SPEAR1310_CLCD_SYNT_CLK_SHIFT,
639 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 642 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
640 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 643 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
641 644
@@ -645,7 +648,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
645 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 648 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
646 649
647 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 650 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
648 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 651 ARRAY_SIZE(clcd_pixel_parents),
652 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
649 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 653 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
650 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 654 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
651 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 655 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -657,9 +661,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
657 661
658 /* i2s */ 662 /* i2s */
659 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 663 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
660 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG, 664 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
661 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 665 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
662 0, &_lock); 666 SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
663 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 667 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
664 668
665 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 669 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
@@ -668,7 +672,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
668 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 672 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
669 673
670 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 674 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
671 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 675 ARRAY_SIZE(i2s_ref_parents),
676 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
672 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, 677 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
673 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); 678 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
674 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 679 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -806,13 +811,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
806 811
807 /* RAS clks */ 812 /* RAS clks */
808 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 813 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
809 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG, 814 ARRAY_SIZE(gen_synth0_1_parents),
815 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
810 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 816 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
811 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 817 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
812 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 818 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
813 819
814 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 820 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
815 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG, 821 ARRAY_SIZE(gen_synth2_3_parents),
822 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
816 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 823 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
817 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 824 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
818 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 825 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
@@ -929,8 +936,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
929 936
930 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", 937 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
931 smii_rgmii_phy_parents, 938 smii_rgmii_phy_parents,
932 ARRAY_SIZE(smii_rgmii_phy_parents), 0, 939 ARRAY_SIZE(smii_rgmii_phy_parents),
933 SPEAR1310_RAS_CTRL_REG1, 940 CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
934 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 941 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
935 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 942 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
936 clk_register_clkdev(clk, "stmmacphy.1", NULL); 943 clk_register_clkdev(clk, "stmmacphy.1", NULL);
@@ -938,15 +945,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
938 clk_register_clkdev(clk, "stmmacphy.4", NULL); 945 clk_register_clkdev(clk, "stmmacphy.4", NULL);
939 946
940 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 947 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
941 ARRAY_SIZE(rmii_phy_parents), 0, 948 ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
942 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 949 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
943 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 950 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
944 clk_register_clkdev(clk, "stmmacphy.3", NULL); 951 clk_register_clkdev(clk, "stmmacphy.3", NULL);
945 952
946 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 953 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
947 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 954 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
948 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 955 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
949 0, &_lock); 956 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
950 clk_register_clkdev(clk, "uart1_mclk", NULL); 957 clk_register_clkdev(clk, "uart1_mclk", NULL);
951 958
952 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 959 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -955,9 +962,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
955 clk_register_clkdev(clk, NULL, "5c800000.serial"); 962 clk_register_clkdev(clk, NULL, "5c800000.serial");
956 963
957 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, 964 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
958 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 965 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
959 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 966 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
960 0, &_lock); 967 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
961 clk_register_clkdev(clk, "uart2_mclk", NULL); 968 clk_register_clkdev(clk, "uart2_mclk", NULL);
962 969
963 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, 970 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
@@ -966,9 +973,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
966 clk_register_clkdev(clk, NULL, "5c900000.serial"); 973 clk_register_clkdev(clk, NULL, "5c900000.serial");
967 974
968 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, 975 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
969 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 976 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
970 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 977 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
971 0, &_lock); 978 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
972 clk_register_clkdev(clk, "uart3_mclk", NULL); 979 clk_register_clkdev(clk, "uart3_mclk", NULL);
973 980
974 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, 981 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
@@ -977,9 +984,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
977 clk_register_clkdev(clk, NULL, "5ca00000.serial"); 984 clk_register_clkdev(clk, NULL, "5ca00000.serial");
978 985
979 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, 986 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
980 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 987 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
981 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 988 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
982 0, &_lock); 989 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
983 clk_register_clkdev(clk, "uart4_mclk", NULL); 990 clk_register_clkdev(clk, "uart4_mclk", NULL);
984 991
985 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, 992 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
@@ -988,9 +995,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
988 clk_register_clkdev(clk, NULL, "5cb00000.serial"); 995 clk_register_clkdev(clk, NULL, "5cb00000.serial");
989 996
990 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, 997 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
991 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 998 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
992 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 999 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
993 0, &_lock); 1000 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
994 clk_register_clkdev(clk, "uart5_mclk", NULL); 1001 clk_register_clkdev(clk, "uart5_mclk", NULL);
995 1002
996 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, 1003 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
@@ -999,9 +1006,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
999 clk_register_clkdev(clk, NULL, "5cc00000.serial"); 1006 clk_register_clkdev(clk, NULL, "5cc00000.serial");
1000 1007
1001 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, 1008 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1002 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1009 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1003 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1010 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
1004 &_lock); 1011 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1005 clk_register_clkdev(clk, "i2c1_mclk", NULL); 1012 clk_register_clkdev(clk, "i2c1_mclk", NULL);
1006 1013
1007 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, 1014 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
@@ -1010,9 +1017,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1010 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 1017 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1011 1018
1012 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, 1019 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1013 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1020 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1014 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1021 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
1015 &_lock); 1022 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1016 clk_register_clkdev(clk, "i2c2_mclk", NULL); 1023 clk_register_clkdev(clk, "i2c2_mclk", NULL);
1017 1024
1018 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, 1025 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
@@ -1021,9 +1028,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1021 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 1028 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1022 1029
1023 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, 1030 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1024 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1031 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1025 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1032 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
1026 &_lock); 1033 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1027 clk_register_clkdev(clk, "i2c3_mclk", NULL); 1034 clk_register_clkdev(clk, "i2c3_mclk", NULL);
1028 1035
1029 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, 1036 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
@@ -1032,9 +1039,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1032 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 1039 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1033 1040
1034 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, 1041 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1035 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1042 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1036 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1043 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
1037 &_lock); 1044 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1038 clk_register_clkdev(clk, "i2c4_mclk", NULL); 1045 clk_register_clkdev(clk, "i2c4_mclk", NULL);
1039 1046
1040 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, 1047 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
@@ -1043,9 +1050,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1043 clk_register_clkdev(clk, NULL, "5d000000.i2c"); 1050 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1044 1051
1045 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, 1052 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1046 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1053 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1047 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1054 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
1048 &_lock); 1055 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1049 clk_register_clkdev(clk, "i2c5_mclk", NULL); 1056 clk_register_clkdev(clk, "i2c5_mclk", NULL);
1050 1057
1051 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, 1058 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
@@ -1054,9 +1061,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1054 clk_register_clkdev(clk, NULL, "5d100000.i2c"); 1061 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1055 1062
1056 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, 1063 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1057 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1064 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1058 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1065 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
1059 &_lock); 1066 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1060 clk_register_clkdev(clk, "i2c6_mclk", NULL); 1067 clk_register_clkdev(clk, "i2c6_mclk", NULL);
1061 1068
1062 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, 1069 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
@@ -1065,9 +1072,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1065 clk_register_clkdev(clk, NULL, "5d200000.i2c"); 1072 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1066 1073
1067 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, 1074 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1068 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1075 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1069 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1076 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
1070 &_lock); 1077 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1071 clk_register_clkdev(clk, "i2c7_mclk", NULL); 1078 clk_register_clkdev(clk, "i2c7_mclk", NULL);
1072 1079
1073 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, 1080 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
@@ -1076,9 +1083,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1076 clk_register_clkdev(clk, NULL, "5d300000.i2c"); 1083 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1077 1084
1078 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, 1085 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1079 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1086 ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
1080 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, 1087 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
1081 &_lock); 1088 SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
1082 clk_register_clkdev(clk, "ssp1_mclk", NULL); 1089 clk_register_clkdev(clk, "ssp1_mclk", NULL);
1083 1090
1084 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, 1091 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
@@ -1087,9 +1094,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1087 clk_register_clkdev(clk, NULL, "5d400000.spi"); 1094 clk_register_clkdev(clk, NULL, "5d400000.spi");
1088 1095
1089 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, 1096 clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1090 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1097 ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
1091 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, 1098 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
1092 &_lock); 1099 SPEAR1310_PCI_CLK_MASK, 0, &_lock);
1093 clk_register_clkdev(clk, "pci_mclk", NULL); 1100 clk_register_clkdev(clk, "pci_mclk", NULL);
1094 1101
1095 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, 1102 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
@@ -1098,9 +1105,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1098 clk_register_clkdev(clk, NULL, "pci"); 1105 clk_register_clkdev(clk, NULL, "pci");
1099 1106
1100 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, 1107 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1101 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1108 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1102 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1109 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
1103 &_lock); 1110 SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1104 clk_register_clkdev(clk, "tdm1_mclk", NULL); 1111 clk_register_clkdev(clk, "tdm1_mclk", NULL);
1105 1112
1106 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, 1113 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
@@ -1109,9 +1116,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1109 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 1116 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1110 1117
1111 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, 1118 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1112 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1119 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1113 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1120 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
1114 &_lock); 1121 SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1115 clk_register_clkdev(clk, "tdm2_mclk", NULL); 1122 clk_register_clkdev(clk, "tdm2_mclk", NULL);
1116 1123
1117 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, 1124 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 9d0b3949db30..fe835c1845fe 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -473,9 +473,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
473 /* clock derived from 24 or 25 MHz osc clk */ 473 /* clock derived from 24 or 25 MHz osc clk */
474 /* vco-pll */ 474 /* vco-pll */
475 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 475 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
476 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 476 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
477 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 477 SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
478 &_lock); 478 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
479 clk_register_clkdev(clk, "vco1_mclk", NULL); 479 clk_register_clkdev(clk, "vco1_mclk", NULL);
480 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, 480 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
481 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl, 481 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
@@ -484,9 +484,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
484 clk_register_clkdev(clk1, "pll1_clk", NULL); 484 clk_register_clkdev(clk1, "pll1_clk", NULL);
485 485
486 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 486 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
487 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 487 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
488 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 488 SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
489 &_lock); 489 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
490 clk_register_clkdev(clk, "vco2_mclk", NULL); 490 clk_register_clkdev(clk, "vco2_mclk", NULL);
491 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, 491 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
492 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl, 492 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
@@ -495,9 +495,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
495 clk_register_clkdev(clk1, "pll2_clk", NULL); 495 clk_register_clkdev(clk1, "pll2_clk", NULL);
496 496
497 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 497 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
498 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 498 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
499 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 499 SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
500 &_lock); 500 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
501 clk_register_clkdev(clk, "vco3_mclk", NULL); 501 clk_register_clkdev(clk, "vco3_mclk", NULL);
502 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, 502 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
503 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl, 503 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
@@ -561,8 +561,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
561 clk_register_clkdev(clk, "amba_syn_clk", NULL); 561 clk_register_clkdev(clk, "amba_syn_clk", NULL);
562 562
563 clk = clk_register_mux(NULL, "sys_mclk", sys_parents, 563 clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
564 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL, 564 ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
565 SPEAR1340_SCLK_SRC_SEL_SHIFT, 565 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
566 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); 566 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
567 clk_register_clkdev(clk, "sys_mclk", NULL); 567 clk_register_clkdev(clk, "sys_mclk", NULL);
568 568
@@ -583,8 +583,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
583 clk_register_clkdev(clk, NULL, "smp_twd"); 583 clk_register_clkdev(clk, NULL, "smp_twd");
584 584
585 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, 585 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
586 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL, 586 ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
587 SPEAR1340_HCLK_SRC_SEL_SHIFT, 587 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
588 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock); 588 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
589 clk_register_clkdev(clk, "ahb_clk", NULL); 589 clk_register_clkdev(clk, "ahb_clk", NULL);
590 590
@@ -594,9 +594,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
594 594
595 /* gpt clocks */ 595 /* gpt clocks */
596 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 596 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
597 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 597 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
598 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 598 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
599 &_lock); 599 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
600 clk_register_clkdev(clk, "gpt0_mclk", NULL); 600 clk_register_clkdev(clk, "gpt0_mclk", NULL);
601 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 601 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
602 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, 602 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
@@ -604,9 +604,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
604 clk_register_clkdev(clk, NULL, "gpt0"); 604 clk_register_clkdev(clk, NULL, "gpt0");
605 605
606 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 606 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
607 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 607 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
608 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 608 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
609 &_lock); 609 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
610 clk_register_clkdev(clk, "gpt1_mclk", NULL); 610 clk_register_clkdev(clk, "gpt1_mclk", NULL);
611 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 611 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
612 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, 612 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
@@ -614,9 +614,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
614 clk_register_clkdev(clk, NULL, "gpt1"); 614 clk_register_clkdev(clk, NULL, "gpt1");
615 615
616 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 616 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
617 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 617 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
618 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 618 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
619 &_lock); 619 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, "gpt2_mclk", NULL); 620 clk_register_clkdev(clk, "gpt2_mclk", NULL);
621 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 621 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
622 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, 622 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
@@ -624,9 +624,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
624 clk_register_clkdev(clk, NULL, "gpt2"); 624 clk_register_clkdev(clk, NULL, "gpt2");
625 625
626 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 626 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
627 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 627 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
628 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 628 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
629 &_lock); 629 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
630 clk_register_clkdev(clk, "gpt3_mclk", NULL); 630 clk_register_clkdev(clk, "gpt3_mclk", NULL);
631 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 631 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
632 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, 632 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
@@ -641,7 +641,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
641 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); 641 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
642 642
643 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 643 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
644 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 644 ARRAY_SIZE(uart0_parents),
645 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
645 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT, 646 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
646 SPEAR1340_UART_CLK_MASK, 0, &_lock); 647 SPEAR1340_UART_CLK_MASK, 0, &_lock);
647 clk_register_clkdev(clk, "uart0_mclk", NULL); 648 clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -658,9 +659,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
658 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL); 659 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
659 660
660 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, 661 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
661 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG, 662 ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
662 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, 663 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
663 &_lock); 664 SPEAR1340_UART_CLK_MASK, 0, &_lock);
664 clk_register_clkdev(clk, "uart1_mclk", NULL); 665 clk_register_clkdev(clk, "uart1_mclk", NULL);
665 666
666 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 667 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -698,7 +699,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
698 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 699 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
699 700
700 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 701 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
701 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 702 ARRAY_SIZE(c3_parents),
703 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
702 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT, 704 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
703 SPEAR1340_C3_CLK_MASK, 0, &_lock); 705 SPEAR1340_C3_CLK_MASK, 0, &_lock);
704 clk_register_clkdev(clk, "c3_mclk", NULL); 706 clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -710,8 +712,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
710 712
711 /* gmac */ 713 /* gmac */
712 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 714 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
713 ARRAY_SIZE(gmac_phy_input_parents), 0, 715 ARRAY_SIZE(gmac_phy_input_parents),
714 SPEAR1340_GMAC_CLK_CFG, 716 CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
715 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT, 717 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
716 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 718 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
717 clk_register_clkdev(clk, "phy_input_mclk", NULL); 719 clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -723,15 +725,16 @@ void __init spear1340_clk_init(void __iomem *misc_base)
723 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 725 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
724 726
725 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 727 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
726 ARRAY_SIZE(gmac_phy_parents), 0, 728 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
727 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, 729 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
728 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); 730 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
729 clk_register_clkdev(clk, "stmmacphy.0", NULL); 731 clk_register_clkdev(clk, "stmmacphy.0", NULL);
730 732
731 /* clcd */ 733 /* clcd */
732 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 734 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
733 ARRAY_SIZE(clcd_synth_parents), 0, 735 ARRAY_SIZE(clcd_synth_parents),
734 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT, 736 CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
737 SPEAR1340_CLCD_SYNT_CLK_SHIFT,
735 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); 738 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
736 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 739 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
737 740
@@ -741,7 +744,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
741 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 744 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
742 745
743 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 746 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
744 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 747 ARRAY_SIZE(clcd_pixel_parents),
748 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
745 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, 749 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
746 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); 750 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
747 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 751 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -753,9 +757,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
753 757
754 /* i2s */ 758 /* i2s */
755 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 759 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
756 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG, 760 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
757 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK, 761 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
758 0, &_lock); 762 SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
759 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 763 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
760 764
761 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 765 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
@@ -765,7 +769,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
765 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 769 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
766 770
767 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 771 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
768 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 772 ARRAY_SIZE(i2s_ref_parents),
773 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
769 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT, 774 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
770 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); 775 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
771 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 776 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -891,13 +896,15 @@ void __init spear1340_clk_init(void __iomem *misc_base)
891 896
892 /* RAS clks */ 897 /* RAS clks */
893 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 898 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
894 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG, 899 ARRAY_SIZE(gen_synth0_1_parents),
900 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
895 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, 901 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
896 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); 903 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
898 904
899 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 905 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
900 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG, 906 ARRAY_SIZE(gen_synth2_3_parents),
907 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
901 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, 908 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 909 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
903 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); 910 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
@@ -938,7 +945,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
938 clk_register_clkdev(clk, NULL, "spear_cec.1"); 945 clk_register_clkdev(clk, NULL, "spear_cec.1");
939 946
940 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, 947 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
941 ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT, 948 ARRAY_SIZE(spdif_out_parents),
949 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
942 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, 950 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
943 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 951 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
944 clk_register_clkdev(clk, "spdif_out_mclk", NULL); 952 clk_register_clkdev(clk, "spdif_out_mclk", NULL);
@@ -949,7 +957,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
949 clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); 957 clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
950 958
951 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, 959 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
952 ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT, 960 ARRAY_SIZE(spdif_in_parents),
961 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
953 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, 962 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
954 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 963 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
955 clk_register_clkdev(clk, "spdif_in_mclk", NULL); 964 clk_register_clkdev(clk, "spdif_in_mclk", NULL);
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 080c3c5e33f6..c2d204315546 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -294,7 +294,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
294 clk_register_clkdev(clk, NULL, "a9400000.i2s"); 294 clk_register_clkdev(clk, NULL, "a9400000.i2s");
295 295
296 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, 296 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
297 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 297 ARRAY_SIZE(i2s_ref_parents),
298 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
298 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT, 299 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
299 I2S_REF_PCLK_MASK, 0, &_lock); 300 I2S_REF_PCLK_MASK, 0, &_lock);
300 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 301 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
@@ -313,57 +314,66 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
313 clk_register_clkdev(clk, "hclk", "ab000000.eth"); 314 clk_register_clkdev(clk, "hclk", "ab000000.eth");
314 315
315 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, 316 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
316 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 317 ARRAY_SIZE(uartx_parents),
318 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
317 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT, 319 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
318 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 320 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
319 clk_register_clkdev(clk, NULL, "a9300000.serial"); 321 clk_register_clkdev(clk, NULL, "a9300000.serial");
320 322
321 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, 323 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
322 ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT, 324 ARRAY_SIZE(sdhci_parents),
325 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
323 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 326 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
324 0, &_lock); 327 0, &_lock);
325 clk_register_clkdev(clk, NULL, "70000000.sdhci"); 328 clk_register_clkdev(clk, NULL, "70000000.sdhci");
326 329
327 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, 330 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
328 ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG, 331 ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
329 SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock); 332 SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
333 0, &_lock);
330 clk_register_clkdev(clk, NULL, "smii_pclk"); 334 clk_register_clkdev(clk, NULL, "smii_pclk");
331 335
332 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); 336 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
333 clk_register_clkdev(clk, NULL, "smii"); 337 clk_register_clkdev(clk, NULL, "smii");
334 338
335 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, 339 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
336 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 340 ARRAY_SIZE(uartx_parents),
341 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
337 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, 342 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
338 0, &_lock); 343 0, &_lock);
339 clk_register_clkdev(clk, NULL, "a3000000.serial"); 344 clk_register_clkdev(clk, NULL, "a3000000.serial");
340 345
341 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 346 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
342 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 347 ARRAY_SIZE(uartx_parents),
348 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
343 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, 349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
344 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
345 clk_register_clkdev(clk, NULL, "a4000000.serial"); 351 clk_register_clkdev(clk, NULL, "a4000000.serial");
346 352
347 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 353 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
348 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 354 ARRAY_SIZE(uartx_parents),
355 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT, 356 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 357 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
351 clk_register_clkdev(clk, NULL, "a9100000.serial"); 358 clk_register_clkdev(clk, NULL, "a9100000.serial");
352 359
353 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, 360 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
354 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 361 ARRAY_SIZE(uartx_parents),
362 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
355 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT, 363 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
356 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 364 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
357 clk_register_clkdev(clk, NULL, "a9200000.serial"); 365 clk_register_clkdev(clk, NULL, "a9200000.serial");
358 366
359 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, 367 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
360 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 368 ARRAY_SIZE(uartx_parents),
369 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
361 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT, 370 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
362 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 371 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
363 clk_register_clkdev(clk, NULL, "60000000.serial"); 372 clk_register_clkdev(clk, NULL, "60000000.serial");
364 373
365 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, 374 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
366 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 375 ARRAY_SIZE(uartx_parents),
376 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
367 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT, 377 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
368 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 378 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
369 clk_register_clkdev(clk, NULL, "60100000.serial"); 379 clk_register_clkdev(clk, NULL, "60100000.serial");
@@ -427,7 +437,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
427 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 437 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
428 438
429 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 439 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
430 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 440 ARRAY_SIZE(uart0_parents),
441 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
431 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, 442 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
432 &_lock); 443 &_lock);
433 clk_register_clkdev(clk, "uart0_mclk", NULL); 444 clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -444,7 +455,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
444 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 455 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
445 456
446 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 457 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
447 ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT, 458 ARRAY_SIZE(firda_parents),
459 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
448 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, 460 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
449 &_lock); 461 &_lock);
450 clk_register_clkdev(clk, "firda_mclk", NULL); 462 clk_register_clkdev(clk, "firda_mclk", NULL);
@@ -458,14 +470,16 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
458 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, 470 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
459 ARRAY_SIZE(gpt_rtbl), &_lock); 471 ARRAY_SIZE(gpt_rtbl), &_lock);
460 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, 472 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
461 ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT, 473 ARRAY_SIZE(gpt0_parents),
474 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
462 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 475 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
463 clk_register_clkdev(clk, NULL, "gpt0"); 476 clk_register_clkdev(clk, NULL, "gpt0");
464 477
465 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, 478 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
466 ARRAY_SIZE(gpt_rtbl), &_lock); 479 ARRAY_SIZE(gpt_rtbl), &_lock);
467 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, 480 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
468 ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT, 481 ARRAY_SIZE(gpt1_parents),
482 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
469 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 483 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
470 clk_register_clkdev(clk, "gpt1_mclk", NULL); 484 clk_register_clkdev(clk, "gpt1_mclk", NULL);
471 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 485 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
@@ -476,7 +490,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
476 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, 490 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
477 ARRAY_SIZE(gpt_rtbl), &_lock); 491 ARRAY_SIZE(gpt_rtbl), &_lock);
478 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 492 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
479 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT, 493 ARRAY_SIZE(gpt2_parents),
494 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
480 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 495 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
481 clk_register_clkdev(clk, "gpt2_mclk", NULL); 496 clk_register_clkdev(clk, "gpt2_mclk", NULL);
482 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 497 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
@@ -498,9 +513,9 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
498 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); 513 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
499 514
500 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, 515 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
501 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG, 516 ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
502 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, 517 CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
503 &_lock); 518 GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
504 clk_register_clkdev(clk, "gen2_3_par_clk", NULL); 519 clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
505 520
506 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", 521 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
@@ -540,8 +555,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
540 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 555 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
541 556
542 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 557 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
543 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, 558 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
544 MCTR_CLK_MASK, 0, &_lock); 559 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
545 clk_register_clkdev(clk, "ddr_clk", NULL); 560 clk_register_clkdev(clk, "ddr_clk", NULL);
546 561
547 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 562 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index 9406f2426d64..4f649c9cb094 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -169,8 +169,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
169 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 169 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
170 170
171 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, 171 clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
172 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, 172 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
173 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 173 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
174 &_lock);
174 clk_register_clkdev(clk, "uart_mclk", NULL); 175 clk_register_clkdev(clk, "uart_mclk", NULL);
175 176
176 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, 177 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
@@ -188,8 +189,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
188 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 189 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
189 190
190 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 191 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
191 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 192 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
192 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 193 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
194 &_lock);
193 clk_register_clkdev(clk, "firda_mclk", NULL); 195 clk_register_clkdev(clk, "firda_mclk", NULL);
194 196
195 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 197 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
@@ -203,8 +205,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
203 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); 205 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
204 206
205 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, 207 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
206 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, 208 ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
207 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); 209 PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
210 &_lock);
208 clk_register_clkdev(clk, "clcd_mclk", NULL); 211 clk_register_clkdev(clk, "clcd_mclk", NULL);
209 212
210 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, 213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
@@ -217,13 +220,13 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
217 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); 220 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
218 221
219 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, 222 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
220 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 223 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
221 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 224 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
222 clk_register_clkdev(clk, NULL, "gpt0"); 225 clk_register_clkdev(clk, NULL, "gpt0");
223 226
224 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, 227 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
225 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 228 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
226 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 229 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
227 clk_register_clkdev(clk, "gpt1_mclk", NULL); 230 clk_register_clkdev(clk, "gpt1_mclk", NULL);
228 231
229 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
@@ -235,8 +238,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
235 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); 238 clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
236 239
237 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 240 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
238 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 241 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
239 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 242 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
240 clk_register_clkdev(clk, "gpt2_mclk", NULL); 243 clk_register_clkdev(clk, "gpt2_mclk", NULL);
241 244
242 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
@@ -248,8 +251,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
248 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); 251 clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
249 252
250 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, 253 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
251 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, 254 ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
252 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 255 PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
253 clk_register_clkdev(clk, "gpt3_mclk", NULL); 256 clk_register_clkdev(clk, "gpt3_mclk", NULL);
254 257
255 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
@@ -277,8 +280,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
277 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 280 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
278 281
279 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 282 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
280 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, 283 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
281 MCTR_CLK_MASK, 0, &_lock); 284 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
282 clk_register_clkdev(clk, "ddr_clk", NULL); 285 clk_register_clkdev(clk, "ddr_clk", NULL);
283 286
284 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 287 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 412912bbba53..34ee69f4d50c 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -25,12 +25,12 @@
25static DEFINE_SPINLOCK(clk_lock); 25static DEFINE_SPINLOCK(clk_lock);
26 26
27/** 27/**
28 * sunxi_osc_clk_setup() - Setup function for gatable oscillator 28 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
29 */ 29 */
30 30
31#define SUNXI_OSC24M_GATE 0 31#define SUNXI_OSC24M_GATE 0
32 32
33static void __init sunxi_osc_clk_setup(struct device_node *node) 33static void __init sun4i_osc_clk_setup(struct device_node *node)
34{ 34{
35 struct clk *clk; 35 struct clk *clk;
36 struct clk_fixed_rate *fixed; 36 struct clk_fixed_rate *fixed;
@@ -64,22 +64,23 @@ static void __init sunxi_osc_clk_setup(struct device_node *node)
64 &gate->hw, &clk_gate_ops, 64 &gate->hw, &clk_gate_ops,
65 CLK_IS_ROOT); 65 CLK_IS_ROOT);
66 66
67 if (clk) { 67 if (!IS_ERR(clk)) {
68 of_clk_add_provider(node, of_clk_src_simple_get, clk); 68 of_clk_add_provider(node, of_clk_src_simple_get, clk);
69 clk_register_clkdev(clk, clk_name, NULL); 69 clk_register_clkdev(clk, clk_name, NULL);
70 } 70 }
71} 71}
72CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
72 73
73 74
74 75
75/** 76/**
76 * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1 77 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
77 * PLL1 rate is calculated as follows 78 * PLL1 rate is calculated as follows
78 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); 79 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
79 * parent_rate is always 24Mhz 80 * parent_rate is always 24Mhz
80 */ 81 */
81 82
82static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, 83static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
83 u8 *n, u8 *k, u8 *m, u8 *p) 84 u8 *n, u8 *k, u8 *m, u8 *p)
84{ 85{
85 u8 div; 86 u8 div;
@@ -124,15 +125,97 @@ static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
124 *n = div / 4; 125 *n = div / 4;
125} 126}
126 127
128/**
129 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
130 * PLL1 rate is calculated as follows
131 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
132 * parent_rate should always be 24MHz
133 */
134static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
135 u8 *n, u8 *k, u8 *m, u8 *p)
136{
137 /*
138 * We can operate only on MHz, this will make our life easier
139 * later.
140 */
141 u32 freq_mhz = *freq / 1000000;
142 u32 parent_freq_mhz = parent_rate / 1000000;
143
144 /*
145 * Round down the frequency to the closest multiple of either
146 * 6 or 16
147 */
148 u32 round_freq_6 = round_down(freq_mhz, 6);
149 u32 round_freq_16 = round_down(freq_mhz, 16);
150
151 if (round_freq_6 > round_freq_16)
152 freq_mhz = round_freq_6;
153 else
154 freq_mhz = round_freq_16;
155
156 *freq = freq_mhz * 1000000;
127 157
158 /*
159 * If the factors pointer are null, we were just called to
160 * round down the frequency.
161 * Exit.
162 */
163 if (n == NULL)
164 return;
165
166 /* If the frequency is a multiple of 32 MHz, k is always 3 */
167 if (!(freq_mhz % 32))
168 *k = 3;
169 /* If the frequency is a multiple of 9 MHz, k is always 2 */
170 else if (!(freq_mhz % 9))
171 *k = 2;
172 /* If the frequency is a multiple of 8 MHz, k is always 1 */
173 else if (!(freq_mhz % 8))
174 *k = 1;
175 /* Otherwise, we don't use the k factor */
176 else
177 *k = 0;
178
179 /*
180 * If the frequency is a multiple of 2 but not a multiple of
181 * 3, m is 3. This is the first time we use 6 here, yet we
182 * will use it on several other places.
183 * We use this number because it's the lowest frequency we can
184 * generate (with n = 0, k = 0, m = 3), so every other frequency
185 * somehow relates to this frequency.
186 */
187 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
188 *m = 2;
189 /*
190 * If the frequency is a multiple of 6MHz, but the factor is
191 * odd, m will be 3
192 */
193 else if ((freq_mhz / 6) & 1)
194 *m = 3;
195 /* Otherwise, we end up with m = 1 */
196 else
197 *m = 1;
198
199 /* Calculate n thanks to the above factors we already got */
200 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
201
202 /*
203 * If n end up being outbound, and that we can still decrease
204 * m, do it.
205 */
206 if ((*n + 1) > 31 && (*m + 1) > 1) {
207 *n = (*n + 1) / 2 - 1;
208 *m = (*m + 1) / 2 - 1;
209 }
210}
128 211
129/** 212/**
130 * sunxi_get_apb1_factors() - calculates m, p factors for APB1 213 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
131 * APB1 rate is calculated as follows 214 * APB1 rate is calculated as follows
132 * rate = (parent_rate >> p) / (m + 1); 215 * rate = (parent_rate >> p) / (m + 1);
133 */ 216 */
134 217
135static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate, 218static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
136 u8 *n, u8 *k, u8 *m, u8 *p) 219 u8 *n, u8 *k, u8 *m, u8 *p)
137{ 220{
138 u8 calcm, calcp; 221 u8 calcm, calcp;
@@ -178,7 +261,7 @@ struct factors_data {
178 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); 261 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
179}; 262};
180 263
181static struct clk_factors_config pll1_config = { 264static struct clk_factors_config sun4i_pll1_config = {
182 .nshift = 8, 265 .nshift = 8,
183 .nwidth = 5, 266 .nwidth = 5,
184 .kshift = 4, 267 .kshift = 4,
@@ -189,21 +272,35 @@ static struct clk_factors_config pll1_config = {
189 .pwidth = 2, 272 .pwidth = 2,
190}; 273};
191 274
192static struct clk_factors_config apb1_config = { 275static struct clk_factors_config sun6i_a31_pll1_config = {
276 .nshift = 8,
277 .nwidth = 5,
278 .kshift = 4,
279 .kwidth = 2,
280 .mshift = 0,
281 .mwidth = 2,
282};
283
284static struct clk_factors_config sun4i_apb1_config = {
193 .mshift = 0, 285 .mshift = 0,
194 .mwidth = 5, 286 .mwidth = 5,
195 .pshift = 16, 287 .pshift = 16,
196 .pwidth = 2, 288 .pwidth = 2,
197}; 289};
198 290
199static const __initconst struct factors_data pll1_data = { 291static const struct factors_data sun4i_pll1_data __initconst = {
200 .table = &pll1_config, 292 .table = &sun4i_pll1_config,
201 .getter = sunxi_get_pll1_factors, 293 .getter = sun4i_get_pll1_factors,
202}; 294};
203 295
204static const __initconst struct factors_data apb1_data = { 296static const struct factors_data sun6i_a31_pll1_data __initconst = {
205 .table = &apb1_config, 297 .table = &sun6i_a31_pll1_config,
206 .getter = sunxi_get_apb1_factors, 298 .getter = sun6i_a31_get_pll1_factors,
299};
300
301static const struct factors_data sun4i_apb1_data __initconst = {
302 .table = &sun4i_apb1_config,
303 .getter = sun4i_get_apb1_factors,
207}; 304};
208 305
209static void __init sunxi_factors_clk_setup(struct device_node *node, 306static void __init sunxi_factors_clk_setup(struct device_node *node,
@@ -221,7 +318,7 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
221 clk = clk_register_factors(NULL, clk_name, parent, 0, reg, 318 clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
222 data->table, data->getter, &clk_lock); 319 data->table, data->getter, &clk_lock);
223 320
224 if (clk) { 321 if (!IS_ERR(clk)) {
225 of_clk_add_provider(node, of_clk_src_simple_get, clk); 322 of_clk_add_provider(node, of_clk_src_simple_get, clk);
226 clk_register_clkdev(clk, clk_name, NULL); 323 clk_register_clkdev(clk, clk_name, NULL);
227 } 324 }
@@ -239,11 +336,15 @@ struct mux_data {
239 u8 shift; 336 u8 shift;
240}; 337};
241 338
242static const __initconst struct mux_data cpu_mux_data = { 339static const struct mux_data sun4i_cpu_mux_data __initconst = {
243 .shift = 16, 340 .shift = 16,
244}; 341};
245 342
246static const __initconst struct mux_data apb1_mux_data = { 343static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
344 .shift = 12,
345};
346
347static const struct mux_data sun4i_apb1_mux_data __initconst = {
247 .shift = 24, 348 .shift = 24,
248}; 349};
249 350
@@ -261,7 +362,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
261 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 362 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
262 i++; 363 i++;
263 364
264 clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg, 365 clk = clk_register_mux(NULL, clk_name, parents, i,
366 CLK_SET_RATE_NO_REPARENT, reg,
265 data->shift, SUNXI_MUX_GATE_WIDTH, 367 data->shift, SUNXI_MUX_GATE_WIDTH,
266 0, &clk_lock); 368 0, &clk_lock);
267 369
@@ -277,26 +379,34 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
277 * sunxi_divider_clk_setup() - Setup function for simple divider clocks 379 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
278 */ 380 */
279 381
280#define SUNXI_DIVISOR_WIDTH 2
281
282struct div_data { 382struct div_data {
283 u8 shift; 383 u8 shift;
284 u8 pow; 384 u8 pow;
385 u8 width;
285}; 386};
286 387
287static const __initconst struct div_data axi_data = { 388static const struct div_data sun4i_axi_data __initconst = {
288 .shift = 0, 389 .shift = 0,
289 .pow = 0, 390 .pow = 0,
391 .width = 2,
290}; 392};
291 393
292static const __initconst struct div_data ahb_data = { 394static const struct div_data sun4i_ahb_data __initconst = {
293 .shift = 4, 395 .shift = 4,
294 .pow = 1, 396 .pow = 1,
397 .width = 2,
295}; 398};
296 399
297static const __initconst struct div_data apb0_data = { 400static const struct div_data sun4i_apb0_data __initconst = {
298 .shift = 8, 401 .shift = 8,
299 .pow = 1, 402 .pow = 1,
403 .width = 2,
404};
405
406static const struct div_data sun6i_a31_apb2_div_data __initconst = {
407 .shift = 0,
408 .pow = 0,
409 .width = 4,
300}; 410};
301 411
302static void __init sunxi_divider_clk_setup(struct device_node *node, 412static void __init sunxi_divider_clk_setup(struct device_node *node,
@@ -312,7 +422,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
312 clk_parent = of_clk_get_parent_name(node, 0); 422 clk_parent = of_clk_get_parent_name(node, 0);
313 423
314 clk = clk_register_divider(NULL, clk_name, clk_parent, 0, 424 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
315 reg, data->shift, SUNXI_DIVISOR_WIDTH, 425 reg, data->shift, data->width,
316 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, 426 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
317 &clk_lock); 427 &clk_lock);
318 if (clk) { 428 if (clk) {
@@ -333,34 +443,70 @@ struct gates_data {
333 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); 443 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
334}; 444};
335 445
336static const __initconst struct gates_data sun4i_axi_gates_data = { 446static const struct gates_data sun4i_axi_gates_data __initconst = {
337 .mask = {1}, 447 .mask = {1},
338}; 448};
339 449
340static const __initconst struct gates_data sun4i_ahb_gates_data = { 450static const struct gates_data sun4i_ahb_gates_data __initconst = {
341 .mask = {0x7F77FFF, 0x14FB3F}, 451 .mask = {0x7F77FFF, 0x14FB3F},
342}; 452};
343 453
344static const __initconst struct gates_data sun5i_a13_ahb_gates_data = { 454static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
455 .mask = {0x147667e7, 0x185915},
456};
457
458static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
345 .mask = {0x107067e7, 0x185111}, 459 .mask = {0x107067e7, 0x185111},
346}; 460};
347 461
348static const __initconst struct gates_data sun4i_apb0_gates_data = { 462static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
463 .mask = {0xEDFE7F62, 0x794F931},
464};
465
466static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
467 .mask = { 0x12f77fff, 0x16ff3f },
468};
469
470static const struct gates_data sun4i_apb0_gates_data __initconst = {
349 .mask = {0x4EF}, 471 .mask = {0x4EF},
350}; 472};
351 473
352static const __initconst struct gates_data sun5i_a13_apb0_gates_data = { 474static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
475 .mask = {0x469},
476};
477
478static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
353 .mask = {0x61}, 479 .mask = {0x61},
354}; 480};
355 481
356static const __initconst struct gates_data sun4i_apb1_gates_data = { 482static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
483 .mask = { 0x4ff },
484};
485
486static const struct gates_data sun4i_apb1_gates_data __initconst = {
357 .mask = {0xFF00F7}, 487 .mask = {0xFF00F7},
358}; 488};
359 489
360static const __initconst struct gates_data sun5i_a13_apb1_gates_data = { 490static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
491 .mask = {0xf0007},
492};
493
494static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
361 .mask = {0xa0007}, 495 .mask = {0xa0007},
362}; 496};
363 497
498static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
499 .mask = {0x3031},
500};
501
502static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
503 .mask = {0x3F000F},
504};
505
506static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
507 .mask = { 0xff80ff },
508};
509
364static void __init sunxi_gates_clk_setup(struct device_node *node, 510static void __init sunxi_gates_clk_setup(struct device_node *node,
365 struct gates_data *data) 511 struct gates_data *data)
366{ 512{
@@ -410,43 +556,49 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
410 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 556 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
411} 557}
412 558
413/* Matches for of_clk_init */
414static const __initconst struct of_device_id clk_match[] = {
415 {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
416 {}
417};
418
419/* Matches for factors clocks */ 559/* Matches for factors clocks */
420static const __initconst struct of_device_id clk_factors_match[] = { 560static const struct of_device_id clk_factors_match[] __initconst = {
421 {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,}, 561 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
422 {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,}, 562 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
563 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
423 {} 564 {}
424}; 565};
425 566
426/* Matches for divider clocks */ 567/* Matches for divider clocks */
427static const __initconst struct of_device_id clk_div_match[] = { 568static const struct of_device_id clk_div_match[] __initconst = {
428 {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,}, 569 {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
429 {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,}, 570 {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
430 {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,}, 571 {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
572 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
431 {} 573 {}
432}; 574};
433 575
434/* Matches for mux clocks */ 576/* Matches for mux clocks */
435static const __initconst struct of_device_id clk_mux_match[] = { 577static const struct of_device_id clk_mux_match[] __initconst = {
436 {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,}, 578 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
437 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,}, 579 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
580 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
438 {} 581 {}
439}; 582};
440 583
441/* Matches for gate clocks */ 584/* Matches for gate clocks */
442static const __initconst struct of_device_id clk_gates_match[] = { 585static const struct of_device_id clk_gates_match[] __initconst = {
443 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, 586 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
444 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, 587 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
588 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
445 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, 589 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
590 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
591 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
446 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, 592 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
593 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
447 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, 594 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
595 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
448 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, 596 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
597 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
449 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, 598 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
599 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
600 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
601 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
450 {} 602 {}
451}; 603};
452 604
@@ -467,8 +619,8 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
467 619
468void __init sunxi_init_clocks(void) 620void __init sunxi_init_clocks(void)
469{ 621{
470 /* Register all the simple sunxi clocks on DT */ 622 /* Register all the simple and basic clocks on DT */
471 of_clk_init(clk_match); 623 of_clk_init(NULL);
472 624
473 /* Register factor clocks */ 625 /* Register factor clocks */
474 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); 626 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 806d80366c54..9467da7dee49 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1566,7 +1566,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1566 1566
1567 /* audio0 */ 1567 /* audio0 */
1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1569 ARRAY_SIZE(mux_audio_sync_clk), 0, 1569 ARRAY_SIZE(mux_audio_sync_clk),
1570 CLK_SET_RATE_NO_REPARENT,
1570 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1571 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1571 NULL); 1572 NULL);
1572 clks[audio0_mux] = clk; 1573 clks[audio0_mux] = clk;
@@ -1578,7 +1579,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1578 1579
1579 /* audio1 */ 1580 /* audio1 */
1580 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1581 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1581 ARRAY_SIZE(mux_audio_sync_clk), 0, 1582 ARRAY_SIZE(mux_audio_sync_clk),
1583 CLK_SET_RATE_NO_REPARENT,
1582 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1584 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1583 NULL); 1585 NULL);
1584 clks[audio1_mux] = clk; 1586 clks[audio1_mux] = clk;
@@ -1590,7 +1592,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1590 1592
1591 /* audio2 */ 1593 /* audio2 */
1592 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1594 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1593 ARRAY_SIZE(mux_audio_sync_clk), 0, 1595 ARRAY_SIZE(mux_audio_sync_clk),
1596 CLK_SET_RATE_NO_REPARENT,
1594 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1597 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1595 NULL); 1598 NULL);
1596 clks[audio2_mux] = clk; 1599 clks[audio2_mux] = clk;
@@ -1602,7 +1605,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1602 1605
1603 /* audio3 */ 1606 /* audio3 */
1604 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1607 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1605 ARRAY_SIZE(mux_audio_sync_clk), 0, 1608 ARRAY_SIZE(mux_audio_sync_clk),
1609 CLK_SET_RATE_NO_REPARENT,
1606 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1610 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1607 NULL); 1611 NULL);
1608 clks[audio3_mux] = clk; 1612 clks[audio3_mux] = clk;
@@ -1614,7 +1618,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1614 1618
1615 /* audio4 */ 1619 /* audio4 */
1616 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1620 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1617 ARRAY_SIZE(mux_audio_sync_clk), 0, 1621 ARRAY_SIZE(mux_audio_sync_clk),
1622 CLK_SET_RATE_NO_REPARENT,
1618 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1623 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1619 NULL); 1624 NULL);
1620 clks[audio4_mux] = clk; 1625 clks[audio4_mux] = clk;
@@ -1626,7 +1631,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1626 1631
1627 /* spdif */ 1632 /* spdif */
1628 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1633 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1629 ARRAY_SIZE(mux_audio_sync_clk), 0, 1634 ARRAY_SIZE(mux_audio_sync_clk),
1635 CLK_SET_RATE_NO_REPARENT,
1630 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1636 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1631 NULL); 1637 NULL);
1632 clks[spdif_mux] = clk; 1638 clks[spdif_mux] = clk;
@@ -1721,7 +1727,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1721 1727
1722 /* clk_out_1 */ 1728 /* clk_out_1 */
1723 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1729 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1724 ARRAY_SIZE(clk_out1_parents), 0, 1730 ARRAY_SIZE(clk_out1_parents),
1731 CLK_SET_RATE_NO_REPARENT,
1725 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1732 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1726 &clk_out_lock); 1733 &clk_out_lock);
1727 clks[clk_out_1_mux] = clk; 1734 clks[clk_out_1_mux] = clk;
@@ -1733,7 +1740,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1733 1740
1734 /* clk_out_2 */ 1741 /* clk_out_2 */
1735 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1742 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1736 ARRAY_SIZE(clk_out2_parents), 0, 1743 ARRAY_SIZE(clk_out2_parents),
1744 CLK_SET_RATE_NO_REPARENT,
1737 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1745 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1738 &clk_out_lock); 1746 &clk_out_lock);
1739 clks[clk_out_2_mux] = clk; 1747 clks[clk_out_2_mux] = clk;
@@ -1745,7 +1753,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1745 1753
1746 /* clk_out_3 */ 1754 /* clk_out_3 */
1747 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1755 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1748 ARRAY_SIZE(clk_out3_parents), 0, 1756 ARRAY_SIZE(clk_out3_parents),
1757 CLK_SET_RATE_NO_REPARENT,
1749 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1758 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1750 &clk_out_lock); 1759 &clk_out_lock);
1751 clks[clk_out_3_mux] = clk; 1760 clks[clk_out_3_mux] = clk;
@@ -2063,7 +2072,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2063 2072
2064 /* dsia */ 2073 /* dsia */
2065 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2074 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2066 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2075 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2076 CLK_SET_RATE_NO_REPARENT,
2067 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2077 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2068 clks[dsia_mux] = clk; 2078 clks[dsia_mux] = clk;
2069 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2079 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
@@ -2073,7 +2083,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2073 2083
2074 /* dsib */ 2084 /* dsib */
2075 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2085 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2076 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2086 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2087 CLK_SET_RATE_NO_REPARENT,
2077 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2088 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2078 clks[dsib_mux] = clk; 2089 clks[dsib_mux] = clk;
2079 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2090 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
@@ -2110,7 +2121,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2110 2121
2111 /* emc */ 2122 /* emc */
2112 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2123 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2113 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2124 ARRAY_SIZE(mux_pllmcp_clkm),
2125 CLK_SET_RATE_NO_REPARENT,
2114 clk_base + CLK_SOURCE_EMC, 2126 clk_base + CLK_SOURCE_EMC,
2115 29, 3, 0, NULL); 2127 29, 3, 0, NULL);
2116 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2128 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
@@ -2194,7 +2206,7 @@ static const struct of_device_id pmc_match[] __initconst = {
2194 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 2206 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
2195 * breaks 2207 * breaks
2196 */ 2208 */
2197static __initdata struct tegra_clk_init_table init_table[] = { 2209static struct tegra_clk_init_table init_table[] __initdata = {
2198 {uarta, pll_p, 408000000, 0}, 2210 {uarta, pll_p, 408000000, 0},
2199 {uartb, pll_p, 408000000, 0}, 2211 {uartb, pll_p, 408000000, 0},
2200 {uartc, pll_p, 408000000, 0}, 2212 {uartc, pll_p, 408000000, 0},
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 759ca47be753..056f649d0d89 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -778,7 +778,8 @@ static void __init tegra20_audio_clk_init(void)
778 778
779 /* audio */ 779 /* audio */
780 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 780 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
781 ARRAY_SIZE(audio_parents), 0, 781 ARRAY_SIZE(audio_parents),
782 CLK_SET_RATE_NO_REPARENT,
782 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 783 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
783 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 784 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
784 clk_base + AUDIO_SYNC_CLK, 4, 785 clk_base + AUDIO_SYNC_CLK, 4,
@@ -941,7 +942,8 @@ static void __init tegra20_periph_clk_init(void)
941 942
942 /* emc */ 943 /* emc */
943 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 944 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
944 ARRAY_SIZE(mux_pllmcp_clkm), 0, 945 ARRAY_SIZE(mux_pllmcp_clkm),
946 CLK_SET_RATE_NO_REPARENT,
945 clk_base + CLK_SOURCE_EMC, 947 clk_base + CLK_SOURCE_EMC,
946 30, 2, 0, NULL); 948 30, 2, 0, NULL);
947 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 949 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
@@ -1223,7 +1225,7 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1223#endif 1225#endif
1224}; 1226};
1225 1227
1226static __initdata struct tegra_clk_init_table init_table[] = { 1228static struct tegra_clk_init_table init_table[] __initdata = {
1227 {pll_p, clk_max, 216000000, 1}, 1229 {pll_p, clk_max, 216000000, 1},
1228 {pll_p_out1, clk_max, 28800000, 1}, 1230 {pll_p_out1, clk_max, 28800000, 1},
1229 {pll_p_out2, clk_max, 48000000, 1}, 1231 {pll_p_out2, clk_max, 48000000, 1},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e2c6ca0431d6..dbe7c8003c5c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void)
971 /* PLLU */ 971 /* PLLU */
972 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 972 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
973 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 973 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
974 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 974 TEGRA_PLL_SET_LFCON,
975 pll_u_freq_table, 975 pll_u_freq_table,
976 NULL); 976 NULL);
977 clk_register_clkdev(clk, "pll_u", NULL); 977 clk_register_clkdev(clk, "pll_u", NULL);
@@ -1026,7 +1026,8 @@ static void __init tegra30_pll_init(void)
1026 1026
1027 /* PLLE */ 1027 /* PLLE */
1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1029 ARRAY_SIZE(pll_e_parents), 0, 1029 ARRAY_SIZE(pll_e_parents),
1030 CLK_SET_RATE_NO_REPARENT,
1030 clk_base + PLLE_AUX, 2, 1, 0, NULL); 1031 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1031 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 1032 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1032 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 1033 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
@@ -1086,7 +1087,8 @@ static void __init tegra30_audio_clk_init(void)
1086 1087
1087 /* audio0 */ 1088 /* audio0 */
1088 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1089 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1089 ARRAY_SIZE(mux_audio_sync_clk), 0, 1090 ARRAY_SIZE(mux_audio_sync_clk),
1091 CLK_SET_RATE_NO_REPARENT,
1090 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1092 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1091 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1093 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1092 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1094 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
@@ -1096,7 +1098,8 @@ static void __init tegra30_audio_clk_init(void)
1096 1098
1097 /* audio1 */ 1099 /* audio1 */
1098 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1100 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1099 ARRAY_SIZE(mux_audio_sync_clk), 0, 1101 ARRAY_SIZE(mux_audio_sync_clk),
1102 CLK_SET_RATE_NO_REPARENT,
1100 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1103 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1101 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1104 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1102 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1105 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
@@ -1106,7 +1109,8 @@ static void __init tegra30_audio_clk_init(void)
1106 1109
1107 /* audio2 */ 1110 /* audio2 */
1108 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1111 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1109 ARRAY_SIZE(mux_audio_sync_clk), 0, 1112 ARRAY_SIZE(mux_audio_sync_clk),
1113 CLK_SET_RATE_NO_REPARENT,
1110 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1114 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1111 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1115 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1112 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1116 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
@@ -1116,7 +1120,8 @@ static void __init tegra30_audio_clk_init(void)
1116 1120
1117 /* audio3 */ 1121 /* audio3 */
1118 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1122 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1119 ARRAY_SIZE(mux_audio_sync_clk), 0, 1123 ARRAY_SIZE(mux_audio_sync_clk),
1124 CLK_SET_RATE_NO_REPARENT,
1120 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1125 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1121 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1126 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1122 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1127 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
@@ -1126,7 +1131,8 @@ static void __init tegra30_audio_clk_init(void)
1126 1131
1127 /* audio4 */ 1132 /* audio4 */
1128 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1133 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1129 ARRAY_SIZE(mux_audio_sync_clk), 0, 1134 ARRAY_SIZE(mux_audio_sync_clk),
1135 CLK_SET_RATE_NO_REPARENT,
1130 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1136 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1131 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1137 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1132 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1138 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
@@ -1136,7 +1142,8 @@ static void __init tegra30_audio_clk_init(void)
1136 1142
1137 /* spdif */ 1143 /* spdif */
1138 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1144 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1139 ARRAY_SIZE(mux_audio_sync_clk), 0, 1145 ARRAY_SIZE(mux_audio_sync_clk),
1146 CLK_SET_RATE_NO_REPARENT,
1140 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1147 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1141 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1148 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1142 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1149 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
@@ -1229,7 +1236,8 @@ static void __init tegra30_pmc_clk_init(void)
1229 1236
1230 /* clk_out_1 */ 1237 /* clk_out_1 */
1231 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1238 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1232 ARRAY_SIZE(clk_out1_parents), 0, 1239 ARRAY_SIZE(clk_out1_parents),
1240 CLK_SET_RATE_NO_REPARENT,
1233 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1241 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1234 &clk_out_lock); 1242 &clk_out_lock);
1235 clks[clk_out_1_mux] = clk; 1243 clks[clk_out_1_mux] = clk;
@@ -1241,7 +1249,8 @@ static void __init tegra30_pmc_clk_init(void)
1241 1249
1242 /* clk_out_2 */ 1250 /* clk_out_2 */
1243 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1251 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1244 ARRAY_SIZE(clk_out2_parents), 0, 1252 ARRAY_SIZE(clk_out2_parents),
1253 CLK_SET_RATE_NO_REPARENT,
1245 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1254 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1246 &clk_out_lock); 1255 &clk_out_lock);
1247 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1256 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1252,7 +1261,8 @@ static void __init tegra30_pmc_clk_init(void)
1252 1261
1253 /* clk_out_3 */ 1262 /* clk_out_3 */
1254 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1263 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1255 ARRAY_SIZE(clk_out3_parents), 0, 1264 ARRAY_SIZE(clk_out3_parents),
1265 CLK_SET_RATE_NO_REPARENT,
1256 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1266 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1257 &clk_out_lock); 1267 &clk_out_lock);
1258 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1268 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
@@ -1679,7 +1689,8 @@ static void __init tegra30_periph_clk_init(void)
1679 1689
1680 /* emc */ 1690 /* emc */
1681 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1691 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1682 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1692 ARRAY_SIZE(mux_pllmcp_clkm),
1693 CLK_SET_RATE_NO_REPARENT,
1683 clk_base + CLK_SOURCE_EMC, 1694 clk_base + CLK_SOURCE_EMC,
1684 30, 2, 0, NULL); 1695 30, 2, 0, NULL);
1685 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1696 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
@@ -1901,7 +1912,7 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1901#endif 1912#endif
1902}; 1913};
1903 1914
1904static __initdata struct tegra_clk_init_table init_table[] = { 1915static struct tegra_clk_init_table init_table[] __initdata = {
1905 {uarta, pll_p, 408000000, 0}, 1916 {uarta, pll_p, 408000000, 0},
1906 {uartb, pll_p, 408000000, 0}, 1917 {uartb, pll_p, 408000000, 0},
1907 {uartc, pll_p, 408000000, 0}, 1918 {uartc, pll_p, 408000000, 0},
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
index a4a728d05092..2d5e1b4820e0 100644
--- a/drivers/clk/versatile/clk-vexpress.c
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -37,8 +37,8 @@ static void __init vexpress_sp810_init(void __iomem *base)
37 snprintf(name, ARRAY_SIZE(name), "timerclken%d", i); 37 snprintf(name, ARRAY_SIZE(name), "timerclken%d", i);
38 38
39 vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name, 39 vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name,
40 parents, 2, 0, base + SCCTRL, 40 parents, 2, CLK_SET_RATE_NO_REPARENT,
41 SCCTRL_TIMERENnSEL_SHIFT(i), 1, 41 base + SCCTRL, SCCTRL_TIMERENnSEL_SHIFT(i), 1,
42 0, &vexpress_sp810_lock); 42 0, &vexpress_sp810_lock);
43 43
44 if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i]))) 44 if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i])))
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 089d3e30e221..cc40fe64f2dc 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -125,8 +125,9 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
125 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 125 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
126 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 126 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
127 127
128 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 128 clk = clk_register_mux(NULL, mux_name, parents, 4,
129 fclk_ctrl_reg, 4, 2, 0, fclk_lock); 129 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
130 fclk_lock);
130 131
131 clk = clk_register_divider(NULL, div0_name, mux_name, 132 clk = clk_register_divider(NULL, div0_name, mux_name,
132 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 133 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
@@ -168,8 +169,8 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
168 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 169 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
169 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 170 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
170 171
171 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 172 clk = clk_register_mux(NULL, mux_name, parents, 4,
172 clk_ctrl, 4, 2, 0, lock); 173 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
173 174
174 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 175 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
175 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 176 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
@@ -236,25 +237,26 @@ static void __init zynq_clk_setup(struct device_node *np)
236 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 237 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
237 SLCR_PLL_STATUS, 0, &armpll_lock); 238 SLCR_PLL_STATUS, 0, &armpll_lock);
238 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 239 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
239 armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0, 240 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
240 &armpll_lock); 241 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
241 242
242 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 243 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
243 SLCR_PLL_STATUS, 1, &ddrpll_lock); 244 SLCR_PLL_STATUS, 1, &ddrpll_lock);
244 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 245 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
245 ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0, 246 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
246 &ddrpll_lock); 247 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
247 248
248 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 249 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
249 SLCR_PLL_STATUS, 2, &iopll_lock); 250 SLCR_PLL_STATUS, 2, &iopll_lock);
250 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 251 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
251 iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0, 252 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
252 &iopll_lock); 253 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
253 254
254 /* CPU clocks */ 255 /* CPU clocks */
255 tmp = readl(SLCR_621_TRUE) & 1; 256 tmp = readl(SLCR_621_TRUE) & 1;
256 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0, 257 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
257 SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); 258 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
259 &armclk_lock);
258 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 260 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
259 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 261 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
260 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 262 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
@@ -293,8 +295,9 @@ static void __init zynq_clk_setup(struct device_node *np)
293 swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 295 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
294 } 296 }
295 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 297 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
296 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, 298 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
297 SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock); 299 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
300 &swdtclk_lock);
298 301
299 /* DDR clocks */ 302 /* DDR clocks */
300 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 303 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@ -356,8 +359,9 @@ static void __init zynq_clk_setup(struct device_node *np)
356 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 359 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
357 idx); 360 idx);
358 } 361 }
359 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0, 362 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
360 SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); 363 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
364 &gem0clk_lock);
361 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 365 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
362 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 366 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
363 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 367 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
@@ -366,7 +370,8 @@ static void __init zynq_clk_setup(struct device_node *np)
366 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 370 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
367 &gem0clk_lock); 371 &gem0clk_lock);
368 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 372 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
369 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0, 373 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
374 SLCR_GEM0_CLK_CTRL, 6, 1, 0,
370 &gem0clk_lock); 375 &gem0clk_lock);
371 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 376 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
372 "gem0_emio_mux", CLK_SET_RATE_PARENT, 377 "gem0_emio_mux", CLK_SET_RATE_PARENT,
@@ -379,8 +384,9 @@ static void __init zynq_clk_setup(struct device_node *np)
379 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 384 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
380 idx); 385 idx);
381 } 386 }
382 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0, 387 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
383 SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); 388 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
389 &gem1clk_lock);
384 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 390 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
385 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 391 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
386 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 392 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
@@ -389,7 +395,8 @@ static void __init zynq_clk_setup(struct device_node *np)
389 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 395 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
390 &gem1clk_lock); 396 &gem1clk_lock);
391 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 397 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
392 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0, 398 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
399 SLCR_GEM1_CLK_CTRL, 6, 1, 0,
393 &gem1clk_lock); 400 &gem1clk_lock);
394 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 401 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
395 "gem1_emio_mux", CLK_SET_RATE_PARENT, 402 "gem1_emio_mux", CLK_SET_RATE_PARENT,
@@ -409,8 +416,9 @@ static void __init zynq_clk_setup(struct device_node *np)
409 can_mio_mux_parents[i] = dummy_nm; 416 can_mio_mux_parents[i] = dummy_nm;
410 } 417 }
411 kfree(clk_name); 418 kfree(clk_name);
412 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0, 419 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
413 SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); 420 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
421 &canclk_lock);
414 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 422 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
415 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 423 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
416 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 424 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
@@ -425,17 +433,21 @@ static void __init zynq_clk_setup(struct device_node *np)
425 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 433 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
426 &canclk_lock); 434 &canclk_lock);
427 clk = clk_register_mux(NULL, "can0_mio_mux", 435 clk = clk_register_mux(NULL, "can0_mio_mux",
428 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 436 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
429 SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); 437 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
438 &canmioclk_lock);
430 clk = clk_register_mux(NULL, "can1_mio_mux", 439 clk = clk_register_mux(NULL, "can1_mio_mux",
431 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 440 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
432 SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); 441 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
442 0, &canmioclk_lock);
433 clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 443 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
434 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 444 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
435 SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); 445 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
446 &canmioclk_lock);
436 clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 447 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
437 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 448 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
438 SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); 449 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
450 0, &canmioclk_lock);
439 451
440 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 452 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
441 int idx = of_property_match_string(np, "clock-names", 453 int idx = of_property_match_string(np, "clock-names",
@@ -444,13 +456,15 @@ static void __init zynq_clk_setup(struct device_node *np)
444 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 456 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
445 idx); 457 idx);
446 } 458 }
447 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0, 459 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
448 SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); 460 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
461 &dbgclk_lock);
449 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 462 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
450 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 463 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
451 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 464 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
452 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0, 465 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
453 SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); 466 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
467 &dbgclk_lock);
454 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 468 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
455 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 469 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
456 0, 0, &dbgclk_lock); 470 0, 0, &dbgclk_lock);
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 47e307c25a7b..3226f54fa595 100644
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -50,6 +50,9 @@ struct zynq_pll {
50#define PLLCTRL_RESET_MASK 1 50#define PLLCTRL_RESET_MASK 1
51#define PLLCTRL_RESET_SHIFT 0 51#define PLLCTRL_RESET_SHIFT 0
52 52
53#define PLL_FBDIV_MIN 13
54#define PLL_FBDIV_MAX 66
55
53/** 56/**
54 * zynq_pll_round_rate() - Round a clock frequency 57 * zynq_pll_round_rate() - Round a clock frequency
55 * @hw: Handle between common and hardware-specific interfaces 58 * @hw: Handle between common and hardware-specific interfaces
@@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
63 u32 fbdiv; 66 u32 fbdiv;
64 67
65 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); 68 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
66 if (fbdiv < 13) 69 if (fbdiv < PLL_FBDIV_MIN)
67 fbdiv = 13; 70 fbdiv = PLL_FBDIV_MIN;
68 else if (fbdiv > 66) 71 else if (fbdiv > PLL_FBDIV_MAX)
69 fbdiv = 66; 72 fbdiv = PLL_FBDIV_MAX;
70 73
71 return *prate * fbdiv; 74 return *prate * fbdiv;
72} 75}
@@ -182,7 +185,13 @@ static const struct clk_ops zynq_pll_ops = {
182 185
183/** 186/**
184 * clk_register_zynq_pll() - Register PLL with the clock framework 187 * clk_register_zynq_pll() - Register PLL with the clock framework
185 * @np Pointer to the DT device node 188 * @name PLL name
189 * @parent Parent clock name
190 * @pll_ctrl Pointer to PLL control register
191 * @pll_status Pointer to PLL status register
192 * @lock_index Bit index to this PLL's lock status bit in @pll_status
193 * @lock Register lock
194 * Returns handle to the registered clock.
186 */ 195 */
187struct clk *clk_register_zynq_pll(const char *name, const char *parent, 196struct clk *clk_register_zynq_pll(const char *name, const char *parent,
188 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, 197 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 18:23:09 -0400