diff options
| author | Tomasz Figa <t.figa@samsung.com> | 2014-06-24 09:57:12 -0400 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2014-06-30 08:46:03 -0400 |
| commit | a37c82a3b3c0910019abfd22a97be1fdf11ae3e5 (patch) | |
| tree | 423a3a4913d4b8fced511c69fa510e9ec1653c89 /drivers/clk | |
| parent | 34ece9e610682f34776136cba7b4600ea5d8fd94 (diff) | |
clk: samsung: exynos4: Remove SRC_MASK_ISP gates
ISP special clocks have dedicated gating registers and so MUX SRC_MASK
register should not be used. This patch fixes the problem of
Exynos4x12-based boards freezing on system suspend, because those
mux outputs need not to be masked while suspending.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 4f150c9dd38c..7f4a473a7ad7 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c | |||
| @@ -925,21 +925,13 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { | |||
| 925 | GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, | 925 | GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, |
| 926 | 0, 0), | 926 | 0, 0), |
| 927 | GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), | 927 | GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), |
| 928 | GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp", | 928 | GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp", |
| 929 | E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), | ||
| 930 | GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre", | ||
| 931 | E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), | ||
| 932 | GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre", | ||
| 933 | E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), | ||
| 934 | GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", | ||
| 935 | E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), | ||
| 936 | GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp", | ||
| 937 | E4X12_GATE_IP_ISP, 0, 0, 0), | 929 | E4X12_GATE_IP_ISP, 0, 0, 0), |
| 938 | GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp", | 930 | GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre", |
| 939 | E4X12_GATE_IP_ISP, 1, 0, 0), | 931 | E4X12_GATE_IP_ISP, 1, 0, 0), |
| 940 | GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp", | 932 | GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre", |
| 941 | E4X12_GATE_IP_ISP, 2, 0, 0), | 933 | E4X12_GATE_IP_ISP, 2, 0, 0), |
| 942 | GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp", | 934 | GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp", |
| 943 | E4X12_GATE_IP_ISP, 3, 0, 0), | 935 | E4X12_GATE_IP_ISP, 3, 0, 0), |
| 944 | GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), | 936 | GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), |
| 945 | GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, | 937 | GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, |