diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-01-07 11:47:52 -0500 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-02-19 00:41:01 -0500 |
commit | 995a9190ac9ca85cc15d11d9566017e91c58a118 (patch) | |
tree | 8725d24c919cbbc029a751a7820d6589bda4f104 /drivers/clk | |
parent | 6d0abeca3242a88cab8232e4acd7e2bf088f3bc2 (diff) |
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as
their parent, not the main clock. Fix it.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/shmobile/clk-rcar-gen2.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index a59ec217a124..8c7bcbd727df 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c | |||
@@ -186,7 +186,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, | |||
186 | const char *name) | 186 | const char *name) |
187 | { | 187 | { |
188 | const struct clk_div_table *table = NULL; | 188 | const struct clk_div_table *table = NULL; |
189 | const char *parent_name = "main"; | 189 | const char *parent_name; |
190 | unsigned int shift; | 190 | unsigned int shift; |
191 | unsigned int mult = 1; | 191 | unsigned int mult = 1; |
192 | unsigned int div = 1; | 192 | unsigned int div = 1; |
@@ -201,23 +201,31 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, | |||
201 | * the multiplier value. | 201 | * the multiplier value. |
202 | */ | 202 | */ |
203 | u32 value = clk_readl(cpg->reg + CPG_PLL0CR); | 203 | u32 value = clk_readl(cpg->reg + CPG_PLL0CR); |
204 | parent_name = "main"; | ||
204 | mult = ((value >> 24) & ((1 << 7) - 1)) + 1; | 205 | mult = ((value >> 24) & ((1 << 7) - 1)) + 1; |
205 | } else if (!strcmp(name, "pll1")) { | 206 | } else if (!strcmp(name, "pll1")) { |
207 | parent_name = "main"; | ||
206 | mult = config->pll1_mult / 2; | 208 | mult = config->pll1_mult / 2; |
207 | } else if (!strcmp(name, "pll3")) { | 209 | } else if (!strcmp(name, "pll3")) { |
210 | parent_name = "main"; | ||
208 | mult = config->pll3_mult; | 211 | mult = config->pll3_mult; |
209 | } else if (!strcmp(name, "lb")) { | 212 | } else if (!strcmp(name, "lb")) { |
213 | parent_name = "pll1_div2"; | ||
210 | div = cpg_mode & BIT(18) ? 36 : 24; | 214 | div = cpg_mode & BIT(18) ? 36 : 24; |
211 | } else if (!strcmp(name, "qspi")) { | 215 | } else if (!strcmp(name, "qspi")) { |
216 | parent_name = "pll1_div2"; | ||
212 | div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) | 217 | div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) |
213 | ? 16 : 20; | 218 | ? 16 : 20; |
214 | } else if (!strcmp(name, "sdh")) { | 219 | } else if (!strcmp(name, "sdh")) { |
220 | parent_name = "pll1_div2"; | ||
215 | table = cpg_sdh_div_table; | 221 | table = cpg_sdh_div_table; |
216 | shift = 8; | 222 | shift = 8; |
217 | } else if (!strcmp(name, "sd0")) { | 223 | } else if (!strcmp(name, "sd0")) { |
224 | parent_name = "pll1_div2"; | ||
218 | table = cpg_sd01_div_table; | 225 | table = cpg_sd01_div_table; |
219 | shift = 4; | 226 | shift = 4; |
220 | } else if (!strcmp(name, "sd1")) { | 227 | } else if (!strcmp(name, "sd1")) { |
228 | parent_name = "pll1_div2"; | ||
221 | table = cpg_sd01_div_table; | 229 | table = cpg_sd01_div_table; |
222 | shift = 0; | 230 | shift = 0; |
223 | } else if (!strcmp(name, "z")) { | 231 | } else if (!strcmp(name, "z")) { |