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authorTomasz Figa <t.figa@samsung.com>2013-04-04 00:32:55 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-04-04 02:51:09 -0400
commit7bc1d2da0aa80ff387507e3bcb68bd72abec8a92 (patch)
tree16cb3082e107693387b80f16b5b469cadc8b4218 /drivers/clk
parent6976d27415a10d19a718a2e4f862f5c5cc25fd19 (diff)
clk: exynos4: Move dac and mixer to Exynos4210-specific clocks
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 96f2e746473d..c1e64512c1b8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -483,8 +483,6 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
483 * of the clocks can be removed. 483 * of the clocks can be removed.
484 */ 484 */
485 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 485 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
486 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
487 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
488 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0), 486 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0),
489 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 487 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
490 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 488 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
@@ -681,6 +679,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
681 SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 679 SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
682 GATE(sclk_sata, "sclk_sata", "div_sata", 680 GATE(sclk_sata, "sclk_sata", "div_sata",
683 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 681 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
682 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
683 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
684 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), 684 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
685 GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"), 685 GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"),
686 GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"), 686 GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"),