Merge tag 'clk-hisi-for-v3.16' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilicon

enable hix5hd2 clock

5 files changed, 142 insertions, 5 deletions

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f8a28735c96..3e6e577c01db 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/
 obj-$(CONFIG_ARCH_BCM_MOBILE)           += bcm/
 obj-$(CONFIG_ARCH_HI3xxx)               += hisilicon/
 obj-$(CONFIG_ARCH_HIP04)                += hisilicon/
+obj-$(CONFIG_ARCH_HIX5HD2)              += hisilicon/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)       += keystone/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)                  += mmp/
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 40b33c6a8257..038c02f4d0e7 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -6,3 +6,4 @@ obj-y	+= clk.o clkgate-separated.o
 
 obj-$(CONFIG_ARCH_HI3xxx)       += clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)        += clk-hip04.o
+obj-$(CONFIG_ARCH_HIX5HD2)      += clk-hix5hd2.o
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
new file mode 100644
index 000000000000..e5fcfb4e32ef
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/of_address.h>
+#include <dt-bindings/clock/hix5hd2-clock.h>
+#include "clk.h"
+
+static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
+        { HIX5HD2_FIXED_1200M, "1200m", NULL, CLK_IS_ROOT, 1200000000, },
+        { HIX5HD2_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
+        { HIX5HD2_FIXED_48M, "48m", NULL, CLK_IS_ROOT, 48000000, },
+        { HIX5HD2_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
+        { HIX5HD2_FIXED_600M, "600m", NULL, CLK_IS_ROOT, 600000000, },
+        { HIX5HD2_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
+        { HIX5HD2_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
+        { HIX5HD2_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
+        { HIX5HD2_FIXED_100M, "100m", NULL, CLK_IS_ROOT, 100000000, },
+        { HIX5HD2_FIXED_40M, "40m", NULL, CLK_IS_ROOT, 40000000, },
+        { HIX5HD2_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
+        { HIX5HD2_FIXED_1728M, "1728m", NULL, CLK_IS_ROOT, 1728000000, },
+        { HIX5HD2_FIXED_28P8M, "28p8m", NULL, CLK_IS_ROOT, 28000000, },
+        { HIX5HD2_FIXED_432M, "432m", NULL, CLK_IS_ROOT, 432000000, },
+        { HIX5HD2_FIXED_345P6M, "345p6m", NULL, CLK_IS_ROOT, 345000000, },
+        { HIX5HD2_FIXED_288M, "288m", NULL, CLK_IS_ROOT, 288000000, },
+        { HIX5HD2_FIXED_60M,    "60m", NULL, CLK_IS_ROOT, 60000000, },
+        { HIX5HD2_FIXED_750M, "750m", NULL, CLK_IS_ROOT, 750000000, },
+        { HIX5HD2_FIXED_500M, "500m", NULL, CLK_IS_ROOT, 500000000, },
+        { HIX5HD2_FIXED_54M,    "54m", NULL, CLK_IS_ROOT, 54000000, },
+        { HIX5HD2_FIXED_27M, "27m", NULL, CLK_IS_ROOT, 27000000, },
+        { HIX5HD2_FIXED_1500M, "1500m", NULL, CLK_IS_ROOT, 1500000000, },
+        { HIX5HD2_FIXED_375M, "375m", NULL, CLK_IS_ROOT, 375000000, },
+        { HIX5HD2_FIXED_187M, "187m", NULL, CLK_IS_ROOT, 187000000, },
+        { HIX5HD2_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
+        { HIX5HD2_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
+        { HIX5HD2_FIXED_2P02M, "2m", NULL, CLK_IS_ROOT, 2000000, },
+        { HIX5HD2_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
+        { HIX5HD2_FIXED_25M, "25m", NULL, CLK_IS_ROOT, 25000000, },
+        { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, },
+};
+
+static const char *sfc_mux_p[] __initconst = {
+                "24m", "150m", "200m", "100m", "75m", };
+static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
+
+static const char *sdio1_mux_p[] __initconst = {
+                "75m", "100m", "50m", "15m", };
+static u32 sdio1_mux_table[] = {0, 1, 2, 3};
+
+static const char *fephy_mux_p[] __initconst = { "25m", "125m"};
+static u32 fephy_mux_table[] = {0, 1};
+
+
+static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
+        { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
+                CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
+        { HIX5HD2_MMC_MUX, "mmc_mux", sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p),
+                CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio1_mux_table, },
+        { HIX5HD2_FEPHY_MUX, "fephy_mux",
+                fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
+                CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
+};
+
+static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
+        /*sfc*/
+        { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
+                CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
+        { HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc",
+                CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
+        /*sdio1*/
+        { HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m",
+                CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
+        { HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
+                CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
+        { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
+                CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
+};
+
+static void __init hix5hd2_clk_init(struct device_node *np)
+{
+        struct hisi_clock_data *clk_data;
+
+        clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
+        if (!clk_data)
+                return;
+
+        hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
+                                     ARRAY_SIZE(hix5hd2_fixed_rate_clks),
+                                     clk_data);
+        hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
+                                        clk_data);
+        hisi_clk_register_gate(hix5hd2_gate_clks,
+                        ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
+}
+
+CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 276f672e7b1a..a078e84f7b05 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -127,11 +127,14 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
         int i;
 
         for (i = 0; i < nums; i++) {
-                clk = clk_register_mux(NULL, clks[i].name, clks[i].parent_names,
-                                       clks[i].num_parents, clks[i].flags,
-                                       base + clks[i].offset, clks[i].shift,
-                                       clks[i].width, clks[i].mux_flags,
-                                       &hisi_clk_lock);
+                u32 mask = BIT(clks[i].width) - 1;
+
+                clk = clk_register_mux_table(NULL, clks[i].name,
+                                        clks[i].parent_names,
+                                        clks[i].num_parents, clks[i].flags,
+                                        base + clks[i].offset, clks[i].shift,
+                                        mask, clks[i].mux_flags,
+                                        clks[i].table, &hisi_clk_lock);
                 if (IS_ERR(clk)) {
                         pr_err("%s: failed to register clock %s\n",
                                __func__, clks[i].name);
@@ -174,6 +177,34 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
         }
 }
 
+void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
+                                       int nums, struct hisi_clock_data *data)
+{
+        struct clk *clk;
+        void __iomem *base = data->base;
+        int i;
+
+        for (i = 0; i < nums; i++) {
+                clk = clk_register_gate(NULL, clks[i].name,
+                                                clks[i].parent_name,
+                                                clks[i].flags,
+                                                base + clks[i].offset,
+                                                clks[i].bit_idx,
+                                                clks[i].gate_flags,
+                                                &hisi_clk_lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+
+                if (clks[i].alias)
+                        clk_register_clkdev(clk, clks[i].alias, NULL);
+
+                data->clk_data.clks[clks[i].id] = clk;
+        }
+}
+
 void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
                                        int nums, struct hisi_clock_data *data)
 {
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
index 43fa5da88f02..31083ffc0650 100644
--- a/drivers/clk/hisilicon/clk.h
+++ b/drivers/clk/hisilicon/clk.h
@@ -62,6 +62,7 @@ struct hisi_mux_clock {
         u8                      shift;
         u8                      width;
         u8                      mux_flags;
+        u32                     *table;
         const char              *alias;
 };
 
@@ -103,6 +104,8 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
                                 struct hisi_clock_data *);
 void __init hisi_clk_register_divider(struct hisi_divider_clock *,
                                 int, struct hisi_clock_data *);
+void __init hisi_clk_register_gate(struct hisi_gate_clock *,
+                                        int, struct hisi_clock_data *);
 void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
                                         int, struct hisi_clock_data *);
 #endif  /* __HISI_CLK_H */