diff options
author | Naveen Krishna Ch <naveenkrishna.ch@gmail.com> | 2014-10-21 01:43:52 -0400 |
---|---|---|
committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2014-10-31 05:45:51 -0400 |
commit | 6d0c8c723f0b886f58263c089831fd2bee0b3b57 (patch) | |
tree | ab824227dc59d57fa769b2fe07fca91ac391f097 /drivers/clk | |
parent | 57a2b485fa512be47b479077b5f89e1bfe536709 (diff) |
clk: samsung: exynos7: add clocks for MMC block
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/samsung/clk-exynos7.c | 224 |
1 files changed, 224 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index c700f654289e..f5e43fab1951 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c | |||
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct device_node *np) | |||
267 | CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", | 267 | CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", |
268 | exynos7_clk_top0_init); | 268 | exynos7_clk_top0_init); |
269 | 269 | ||
270 | /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ | ||
271 | #define MUX_SEL_TOP10 0x0200 | ||
272 | #define MUX_SEL_TOP11 0x0204 | ||
273 | #define MUX_SEL_TOP13 0x020C | ||
274 | #define MUX_SEL_TOP1_FSYS0 0x0224 | ||
275 | #define MUX_SEL_TOP1_FSYS1 0x0228 | ||
276 | #define DIV_TOP13 0x060C | ||
277 | #define DIV_TOP1_FSYS0 0x0624 | ||
278 | #define DIV_TOP1_FSYS1 0x0628 | ||
279 | #define ENABLE_ACLK_TOP13 0x080C | ||
280 | #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 | ||
281 | #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 | ||
282 | |||
283 | /* List of parent clocks for Muxes in CMU_TOP1 */ | ||
284 | PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; | ||
285 | PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; | ||
286 | PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; | ||
287 | PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; | ||
288 | |||
289 | PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", | ||
290 | "ffac_top1_bus0_pll_div2"}; | ||
291 | PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", | ||
292 | "ffac_top1_bus1_pll_div2"}; | ||
293 | PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", | ||
294 | "ffac_top1_cc_pll_div2"}; | ||
295 | PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", | ||
296 | "ffac_top1_mfc_pll_div2"}; | ||
297 | |||
298 | PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", | ||
299 | "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", | ||
300 | "mout_top1_half_mfc_pll"}; | ||
301 | |||
302 | static unsigned long top1_clk_regs[] __initdata = { | ||
303 | MUX_SEL_TOP10, | ||
304 | MUX_SEL_TOP11, | ||
305 | MUX_SEL_TOP13, | ||
306 | MUX_SEL_TOP1_FSYS0, | ||
307 | MUX_SEL_TOP1_FSYS1, | ||
308 | DIV_TOP13, | ||
309 | DIV_TOP1_FSYS0, | ||
310 | DIV_TOP1_FSYS1, | ||
311 | ENABLE_ACLK_TOP13, | ||
312 | ENABLE_SCLK_TOP1_FSYS0, | ||
313 | ENABLE_SCLK_TOP1_FSYS1, | ||
314 | }; | ||
315 | |||
316 | static struct samsung_mux_clock top1_mux_clks[] __initdata = { | ||
317 | MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), | ||
318 | MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), | ||
319 | MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, | ||
320 | MUX_SEL_TOP10, 12, 1), | ||
321 | MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, | ||
322 | MUX_SEL_TOP10, 16, 1), | ||
323 | |||
324 | MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, | ||
325 | MUX_SEL_TOP11, 4, 1), | ||
326 | MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, | ||
327 | MUX_SEL_TOP11, 8, 1), | ||
328 | MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, | ||
329 | MUX_SEL_TOP11, 12, 1), | ||
330 | MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, | ||
331 | MUX_SEL_TOP11, 16, 1), | ||
332 | |||
333 | MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), | ||
334 | MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), | ||
335 | |||
336 | MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2), | ||
337 | |||
338 | MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2), | ||
339 | MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2), | ||
340 | }; | ||
341 | |||
342 | static struct samsung_div_clock top1_div_clks[] __initdata = { | ||
343 | DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", | ||
344 | DIV_TOP13, 24, 4), | ||
345 | DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", | ||
346 | DIV_TOP13, 28, 4), | ||
347 | |||
348 | DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", | ||
349 | DIV_TOP1_FSYS0, 24, 4), | ||
350 | |||
351 | DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", | ||
352 | DIV_TOP1_FSYS1, 24, 4), | ||
353 | DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", | ||
354 | DIV_TOP1_FSYS1, 28, 4), | ||
355 | }; | ||
356 | |||
357 | static struct samsung_gate_clock top1_gate_clks[] __initdata = { | ||
358 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", | ||
359 | ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0), | ||
360 | |||
361 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", | ||
362 | ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0), | ||
363 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", | ||
364 | ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0), | ||
365 | }; | ||
366 | |||
367 | static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { | ||
368 | FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), | ||
369 | FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), | ||
370 | FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), | ||
371 | FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), | ||
372 | }; | ||
373 | |||
374 | static struct samsung_cmu_info top1_cmu_info __initdata = { | ||
375 | .mux_clks = top1_mux_clks, | ||
376 | .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), | ||
377 | .div_clks = top1_div_clks, | ||
378 | .nr_div_clks = ARRAY_SIZE(top1_div_clks), | ||
379 | .gate_clks = top1_gate_clks, | ||
380 | .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), | ||
381 | .fixed_factor_clks = top1_fixed_factor_clks, | ||
382 | .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), | ||
383 | .nr_clk_ids = TOP1_NR_CLK, | ||
384 | .clk_regs = top1_clk_regs, | ||
385 | .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), | ||
386 | }; | ||
387 | |||
388 | static void __init exynos7_clk_top1_init(struct device_node *np) | ||
389 | { | ||
390 | samsung_cmu_register_one(np, &top1_cmu_info); | ||
391 | } | ||
392 | |||
393 | CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", | ||
394 | exynos7_clk_top1_init); | ||
395 | |||
270 | /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ | 396 | /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ |
271 | #define MUX_SEL_PERIC0 0x0200 | 397 | #define MUX_SEL_PERIC0 0x0200 |
272 | #define ENABLE_PCLK_PERIC0 0x0900 | 398 | #define ENABLE_PCLK_PERIC0 0x0900 |
@@ -447,3 +573,101 @@ static void __init exynos7_clk_peris_init(struct device_node *np) | |||
447 | 573 | ||
448 | CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", | 574 | CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", |
449 | exynos7_clk_peris_init); | 575 | exynos7_clk_peris_init); |
576 | |||
577 | /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ | ||
578 | #define MUX_SEL_FSYS00 0x0200 | ||
579 | #define MUX_SEL_FSYS01 0x0204 | ||
580 | #define ENABLE_ACLK_FSYS01 0x0804 | ||
581 | |||
582 | /* | ||
583 | * List of parent clocks for Muxes in CMU_FSYS0 | ||
584 | */ | ||
585 | PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; | ||
586 | PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; | ||
587 | |||
588 | static unsigned long fsys0_clk_regs[] __initdata = { | ||
589 | MUX_SEL_FSYS00, | ||
590 | MUX_SEL_FSYS01, | ||
591 | ENABLE_ACLK_FSYS01, | ||
592 | }; | ||
593 | |||
594 | static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { | ||
595 | MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, | ||
596 | MUX_SEL_FSYS00, 24, 1), | ||
597 | |||
598 | MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), | ||
599 | }; | ||
600 | |||
601 | static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { | ||
602 | GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", | ||
603 | ENABLE_ACLK_FSYS01, 31, 0, 0), | ||
604 | }; | ||
605 | |||
606 | static struct samsung_cmu_info fsys0_cmu_info __initdata = { | ||
607 | .mux_clks = fsys0_mux_clks, | ||
608 | .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), | ||
609 | .gate_clks = fsys0_gate_clks, | ||
610 | .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), | ||
611 | .nr_clk_ids = TOP1_NR_CLK, | ||
612 | .clk_regs = fsys0_clk_regs, | ||
613 | .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), | ||
614 | }; | ||
615 | |||
616 | static void __init exynos7_clk_fsys0_init(struct device_node *np) | ||
617 | { | ||
618 | samsung_cmu_register_one(np, &fsys0_cmu_info); | ||
619 | } | ||
620 | |||
621 | CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", | ||
622 | exynos7_clk_fsys0_init); | ||
623 | |||
624 | /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ | ||
625 | #define MUX_SEL_FSYS10 0x0200 | ||
626 | #define MUX_SEL_FSYS11 0x0204 | ||
627 | #define ENABLE_ACLK_FSYS1 0x0800 | ||
628 | |||
629 | /* | ||
630 | * List of parent clocks for Muxes in CMU_FSYS1 | ||
631 | */ | ||
632 | PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; | ||
633 | PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; | ||
634 | PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; | ||
635 | |||
636 | static unsigned long fsys1_clk_regs[] __initdata = { | ||
637 | MUX_SEL_FSYS10, | ||
638 | MUX_SEL_FSYS11, | ||
639 | ENABLE_ACLK_FSYS1, | ||
640 | }; | ||
641 | |||
642 | static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { | ||
643 | MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, | ||
644 | MUX_SEL_FSYS10, 28, 1), | ||
645 | |||
646 | MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), | ||
647 | MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), | ||
648 | }; | ||
649 | |||
650 | static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { | ||
651 | GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", | ||
652 | ENABLE_ACLK_FSYS1, 29, 0, 0), | ||
653 | GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", | ||
654 | ENABLE_ACLK_FSYS1, 30, 0, 0), | ||
655 | }; | ||
656 | |||
657 | static struct samsung_cmu_info fsys1_cmu_info __initdata = { | ||
658 | .mux_clks = fsys1_mux_clks, | ||
659 | .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), | ||
660 | .gate_clks = fsys1_gate_clks, | ||
661 | .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), | ||
662 | .nr_clk_ids = TOP1_NR_CLK, | ||
663 | .clk_regs = fsys1_clk_regs, | ||
664 | .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), | ||
665 | }; | ||
666 | |||
667 | static void __init exynos7_clk_fsys1_init(struct device_node *np) | ||
668 | { | ||
669 | samsung_cmu_register_one(np, &fsys1_cmu_info); | ||
670 | } | ||
671 | |||
672 | CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", | ||
673 | exynos7_clk_fsys1_init); | ||