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authorShiraz Hashim <shiraz.hashim@st.com>2012-11-10 01:43:42 -0500
committerMike Turquette <mturquette@linaro.org>2012-11-21 14:45:36 -0500
commit463f9e209ca69d52344479544d1e52c02f2e6918 (patch)
treeba626f44ca41f4e72096013712540a55703427d4 /drivers/clk
parente0b9c2109b4686c343514823469013150d28b4c0 (diff)
CLK: SPEAr13xx: fix parent names of multiple clocks
This patch fixes parent names of multiple clocks. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/spear/spear1310_clock.c2
-rw-r--r--drivers/clk/spear/spear1340_clock.c6
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 2f1cb7165bc7..e84b1fbb5838 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -664,7 +664,7 @@ void __init spear1310_clk_init(void)
664 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 664 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
665 665
666 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", 666 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
667 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG, 667 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
668 &i2s_sclk_masks, i2s_sclk_rtbl, 668 &i2s_sclk_masks, i2s_sclk_rtbl,
669 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 669 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
670 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 670 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 4733d996599e..020431ac163d 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -370,7 +370,7 @@ static struct frac_rate_tbl gen_rtbl[] = {
370/* clock parents */ 370/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", 372static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
373 "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", }; 373 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", }; 374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", 376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
@@ -391,7 +391,7 @@ static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
391 391
392static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 392static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
393 "pll3_clk", }; 393 "pll3_clk", };
394static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 394static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
395 "pll2_clk", }; 395 "pll2_clk", };
396 396
397void __init spear1340_clk_init(void) 397void __init spear1340_clk_init(void)
@@ -956,7 +956,7 @@ void __init spear1340_clk_init(void)
956 &_lock); 956 &_lock);
957 clk_register_clkdev(clk, NULL, "d0500000.cam3"); 957 clk_register_clkdev(clk, NULL, "d0500000.cam3");
958 958
959 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mclk", 0, 959 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
960 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, 960 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
961 &_lock); 961 &_lock);
962 clk_register_clkdev(clk, NULL, "e0180000.pwm"); 962 clk_register_clkdev(clk, NULL, "e0180000.pwm");