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authorUlf Hansson <ulf.hansson@linaro.org>2012-08-27 09:45:50 -0400
committerMike Turquette <mturquette@linaro.org>2012-09-06 18:57:47 -0400
commit3b01f87be21ce6b45ff4bd7b9d044aa9233bcc38 (patch)
treec2c025ca2656cd7aa4fdf56a9d365da2cecec9f8 /drivers/clk
parent672575e1dea4c6fe6b0579b94aa1c3af08a1a812 (diff)
clk: ux500: Adapt PRCMU and PRCC clocks for common clk
First version of common clock implementation of PRCMU clocks and PRCC clocks for ux500 platforms. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ux500/Makefile7
-rw-r--r--drivers/clk/ux500/clk-prcc.c164
-rw-r--r--drivers/clk/ux500/clk-prcmu.c238
-rw-r--r--drivers/clk/ux500/clk.h43
4 files changed, 452 insertions, 0 deletions
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
new file mode 100644
index 000000000000..a3ccd1b4cfcd
--- /dev/null
+++ b/drivers/clk/ux500/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for ux500 clocks
3#
4
5# Clock types
6obj-y += clk-prcc.o
7obj-y += clk-prcmu.o
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
new file mode 100644
index 000000000000..7eee7f768355
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -0,0 +1,164 @@
1/*
2 * PRCC clock implementation for ux500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clk-private.h>
12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <linux/types.h>
16#include <mach/hardware.h>
17
18#include "clk.h"
19
20#define PRCC_PCKEN 0x000
21#define PRCC_PCKDIS 0x004
22#define PRCC_KCKEN 0x008
23#define PRCC_KCKDIS 0x00C
24#define PRCC_PCKSR 0x010
25#define PRCC_KCKSR 0x014
26
27#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
28
29struct clk_prcc {
30 struct clk_hw hw;
31 void __iomem *base;
32 u32 cg_sel;
33 int is_enabled;
34};
35
36/* PRCC clock operations. */
37
38static int clk_prcc_pclk_enable(struct clk_hw *hw)
39{
40 struct clk_prcc *clk = to_clk_prcc(hw);
41
42 writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
43 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel))
44 cpu_relax();
45
46 clk->is_enabled = 1;
47 return 0;
48}
49
50static void clk_prcc_pclk_disable(struct clk_hw *hw)
51{
52 struct clk_prcc *clk = to_clk_prcc(hw);
53
54 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS));
55 clk->is_enabled = 0;
56}
57
58static int clk_prcc_kclk_enable(struct clk_hw *hw)
59{
60 struct clk_prcc *clk = to_clk_prcc(hw);
61
62 writel(clk->cg_sel, (clk->base + PRCC_KCKEN));
63 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel))
64 cpu_relax();
65
66 clk->is_enabled = 1;
67 return 0;
68}
69
70static void clk_prcc_kclk_disable(struct clk_hw *hw)
71{
72 struct clk_prcc *clk = to_clk_prcc(hw);
73
74 writel(clk->cg_sel, (clk->base + PRCC_KCKDIS));
75 clk->is_enabled = 0;
76}
77
78static int clk_prcc_is_enabled(struct clk_hw *hw)
79{
80 struct clk_prcc *clk = to_clk_prcc(hw);
81 return clk->is_enabled;
82}
83
84static struct clk_ops clk_prcc_pclk_ops = {
85 .enable = clk_prcc_pclk_enable,
86 .disable = clk_prcc_pclk_disable,
87 .is_enabled = clk_prcc_is_enabled,
88};
89
90static struct clk_ops clk_prcc_kclk_ops = {
91 .enable = clk_prcc_kclk_enable,
92 .disable = clk_prcc_kclk_disable,
93 .is_enabled = clk_prcc_is_enabled,
94};
95
96static struct clk *clk_reg_prcc(const char *name,
97 const char *parent_name,
98 resource_size_t phy_base,
99 u32 cg_sel,
100 unsigned long flags,
101 struct clk_ops *clk_prcc_ops)
102{
103 struct clk_prcc *clk;
104 struct clk_init_data clk_prcc_init;
105 struct clk *clk_reg;
106
107 if (!name) {
108 pr_err("clk_prcc: %s invalid arguments passed\n", __func__);
109 return ERR_PTR(-EINVAL);
110 }
111
112 clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL);
113 if (!clk) {
114 pr_err("clk_prcc: %s could not allocate clk\n", __func__);
115 return ERR_PTR(-ENOMEM);
116 }
117
118 clk->base = ioremap(phy_base, SZ_4K);
119 if (!clk->base)
120 goto free_clk;
121
122 clk->cg_sel = cg_sel;
123 clk->is_enabled = 1;
124
125 clk_prcc_init.name = name;
126 clk_prcc_init.ops = clk_prcc_ops;
127 clk_prcc_init.flags = flags;
128 clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
129 clk_prcc_init.num_parents = (parent_name ? 1 : 0);
130 clk->hw.init = &clk_prcc_init;
131
132 clk_reg = clk_register(NULL, &clk->hw);
133 if (IS_ERR_OR_NULL(clk_reg))
134 goto unmap_clk;
135
136 return clk_reg;
137
138unmap_clk:
139 iounmap(clk->base);
140free_clk:
141 kfree(clk);
142 pr_err("clk_prcc: %s failed to register clk\n", __func__);
143 return ERR_PTR(-ENOMEM);
144}
145
146struct clk *clk_reg_prcc_pclk(const char *name,
147 const char *parent_name,
148 resource_size_t phy_base,
149 u32 cg_sel,
150 unsigned long flags)
151{
152 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
153 &clk_prcc_pclk_ops);
154}
155
156struct clk *clk_reg_prcc_kclk(const char *name,
157 const char *parent_name,
158 resource_size_t phy_base,
159 u32 cg_sel,
160 unsigned long flags)
161{
162 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
163 &clk_prcc_kclk_ops);
164}
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
new file mode 100644
index 000000000000..1d779ad12169
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -0,0 +1,238 @@
1/*
2 * PRCMU clock implementation for ux500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clk-private.h>
12#include <linux/mfd/dbx500-prcmu.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/err.h>
16#include "clk.h"
17
18#define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
19
20struct clk_prcmu {
21 struct clk_hw hw;
22 u8 cg_sel;
23 int is_enabled;
24};
25
26/* PRCMU clock operations. */
27
28static int clk_prcmu_prepare(struct clk_hw *hw)
29{
30 struct clk_prcmu *clk = to_clk_prcmu(hw);
31 return prcmu_request_clock(clk->cg_sel, true);
32}
33
34static void clk_prcmu_unprepare(struct clk_hw *hw)
35{
36 struct clk_prcmu *clk = to_clk_prcmu(hw);
37 if (prcmu_request_clock(clk->cg_sel, false))
38 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
39 hw->init->name);
40}
41
42static int clk_prcmu_enable(struct clk_hw *hw)
43{
44 struct clk_prcmu *clk = to_clk_prcmu(hw);
45 clk->is_enabled = 1;
46 return 0;
47}
48
49static void clk_prcmu_disable(struct clk_hw *hw)
50{
51 struct clk_prcmu *clk = to_clk_prcmu(hw);
52 clk->is_enabled = 0;
53}
54
55static int clk_prcmu_is_enabled(struct clk_hw *hw)
56{
57 struct clk_prcmu *clk = to_clk_prcmu(hw);
58 return clk->is_enabled;
59}
60
61static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
63{
64 struct clk_prcmu *clk = to_clk_prcmu(hw);
65 return prcmu_clock_rate(clk->cg_sel);
66}
67
68static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
69 unsigned long *parent_rate)
70{
71 struct clk_prcmu *clk = to_clk_prcmu(hw);
72 return prcmu_round_clock_rate(clk->cg_sel, rate);
73}
74
75static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
76 unsigned long parent_rate)
77{
78 struct clk_prcmu *clk = to_clk_prcmu(hw);
79 return prcmu_set_clock_rate(clk->cg_sel, rate);
80}
81
82static int request_ape_opp100(bool enable)
83{
84 static int reqs;
85 int err = 0;
86
87 if (enable) {
88 if (!reqs)
89 err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
90 "clock", 100);
91 if (!err)
92 reqs++;
93 } else {
94 reqs--;
95 if (!reqs)
96 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
97 "clock");
98 }
99 return err;
100}
101
102static int clk_prcmu_opp_prepare(struct clk_hw *hw)
103{
104 int err;
105 struct clk_prcmu *clk = to_clk_prcmu(hw);
106
107 err = request_ape_opp100(true);
108 if (err) {
109 pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n",
110 __func__, hw->init->name);
111 return err;
112 }
113
114 err = prcmu_request_clock(clk->cg_sel, true);
115 if (err)
116 request_ape_opp100(false);
117
118 return err;
119}
120
121static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
122{
123 struct clk_prcmu *clk = to_clk_prcmu(hw);
124
125 if (prcmu_request_clock(clk->cg_sel, false))
126 goto out_error;
127 if (request_ape_opp100(false))
128 goto out_error;
129 return;
130
131out_error:
132 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
133 hw->init->name);
134}
135
136static struct clk_ops clk_prcmu_scalable_ops = {
137 .prepare = clk_prcmu_prepare,
138 .unprepare = clk_prcmu_unprepare,
139 .enable = clk_prcmu_enable,
140 .disable = clk_prcmu_disable,
141 .is_enabled = clk_prcmu_is_enabled,
142 .recalc_rate = clk_prcmu_recalc_rate,
143 .round_rate = clk_prcmu_round_rate,
144 .set_rate = clk_prcmu_set_rate,
145};
146
147static struct clk_ops clk_prcmu_gate_ops = {
148 .prepare = clk_prcmu_prepare,
149 .unprepare = clk_prcmu_unprepare,
150 .enable = clk_prcmu_enable,
151 .disable = clk_prcmu_disable,
152 .is_enabled = clk_prcmu_is_enabled,
153 .recalc_rate = clk_prcmu_recalc_rate,
154};
155
156static struct clk_ops clk_prcmu_opp_gate_ops = {
157 .prepare = clk_prcmu_opp_prepare,
158 .unprepare = clk_prcmu_opp_unprepare,
159 .enable = clk_prcmu_enable,
160 .disable = clk_prcmu_disable,
161 .is_enabled = clk_prcmu_is_enabled,
162 .recalc_rate = clk_prcmu_recalc_rate,
163};
164
165static struct clk *clk_reg_prcmu(const char *name,
166 const char *parent_name,
167 u8 cg_sel,
168 unsigned long rate,
169 unsigned long flags,
170 struct clk_ops *clk_prcmu_ops)
171{
172 struct clk_prcmu *clk;
173 struct clk_init_data clk_prcmu_init;
174 struct clk *clk_reg;
175
176 if (!name) {
177 pr_err("clk_prcmu: %s invalid arguments passed\n", __func__);
178 return ERR_PTR(-EINVAL);
179 }
180
181 clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL);
182 if (!clk) {
183 pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
184 return ERR_PTR(-ENOMEM);
185 }
186
187 clk->cg_sel = cg_sel;
188 clk->is_enabled = 1;
189 /* "rate" can be used for changing the initial frequency */
190 if (rate)
191 prcmu_set_clock_rate(cg_sel, rate);
192
193 clk_prcmu_init.name = name;
194 clk_prcmu_init.ops = clk_prcmu_ops;
195 clk_prcmu_init.flags = flags;
196 clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
197 clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
198 clk->hw.init = &clk_prcmu_init;
199
200 clk_reg = clk_register(NULL, &clk->hw);
201 if (IS_ERR_OR_NULL(clk_reg))
202 goto free_clk;
203
204 return clk_reg;
205
206free_clk:
207 kfree(clk);
208 pr_err("clk_prcmu: %s failed to register clk\n", __func__);
209 return ERR_PTR(-ENOMEM);
210}
211
212struct clk *clk_reg_prcmu_scalable(const char *name,
213 const char *parent_name,
214 u8 cg_sel,
215 unsigned long rate,
216 unsigned long flags)
217{
218 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
219 &clk_prcmu_scalable_ops);
220}
221
222struct clk *clk_reg_prcmu_gate(const char *name,
223 const char *parent_name,
224 u8 cg_sel,
225 unsigned long flags)
226{
227 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
228 &clk_prcmu_gate_ops);
229}
230
231struct clk *clk_reg_prcmu_opp_gate(const char *name,
232 const char *parent_name,
233 u8 cg_sel,
234 unsigned long flags)
235{
236 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
237 &clk_prcmu_opp_gate_ops);
238}
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
new file mode 100644
index 000000000000..32085aa98865
--- /dev/null
+++ b/drivers/clk/ux500/clk.h
@@ -0,0 +1,43 @@
1/*
2 * Clocks for ux500 platforms
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#ifndef __UX500_CLK_H
11#define __UX500_CLK_H
12
13#include <linux/clk.h>
14
15struct clk *clk_reg_prcc_pclk(const char *name,
16 const char *parent_name,
17 unsigned int phy_base,
18 u32 cg_sel,
19 unsigned long flags);
20
21struct clk *clk_reg_prcc_kclk(const char *name,
22 const char *parent_name,
23 unsigned int phy_base,
24 u32 cg_sel,
25 unsigned long flags);
26
27struct clk *clk_reg_prcmu_scalable(const char *name,
28 const char *parent_name,
29 u8 cg_sel,
30 unsigned long rate,
31 unsigned long flags);
32
33struct clk *clk_reg_prcmu_gate(const char *name,
34 const char *parent_name,
35 u8 cg_sel,
36 unsigned long flags);
37
38struct clk *clk_reg_prcmu_opp_gate(const char *name,
39 const char *parent_name,
40 u8 cg_sel,
41 unsigned long flags);
42
43#endif /* __UX500_CLK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 09:21:29 -0400