diff options
author | Ulrich Hecht <ulrich.hecht@gmail.com> | 2014-05-23 09:27:15 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-05-23 16:38:25 -0400 |
commit | 1923ca92a618b6107d3a44b5c9f9360b104dcddb (patch) | |
tree | 06e117aa8d9e4ea2d15c0d9a539be0d81e020863 /drivers/clk | |
parent | 4a7f10d67b7a015036823856d6669b1f75362ba0 (diff) |
clk: shmobile: Add R8A7740-specific clock support
Driver for the R8A7740's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/shmobile/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/shmobile/clk-r8a7740.c | 199 |
2 files changed, 200 insertions, 0 deletions
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile index bdf342daefa5..e0029237827a 100644 --- a/drivers/clk/shmobile/Makefile +++ b/drivers/clk/shmobile/Makefile | |||
@@ -1,5 +1,6 @@ | |||
1 | obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o | 1 | obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o |
2 | obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o | 2 | obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o |
3 | obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o | ||
3 | obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o | 4 | obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o |
4 | obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o | 5 | obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o |
5 | obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o | 6 | obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o |
diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c new file mode 100644 index 000000000000..1e2eaae21e01 --- /dev/null +++ b/drivers/clk/shmobile/clk-r8a7740.c | |||
@@ -0,0 +1,199 @@ | |||
1 | /* | ||
2 | * r8a7740 Core CPG Clocks | ||
3 | * | ||
4 | * Copyright (C) 2014 Ulrich Hecht | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; version 2 of the License. | ||
9 | */ | ||
10 | |||
11 | #include <linux/clk-provider.h> | ||
12 | #include <linux/clkdev.h> | ||
13 | #include <linux/clk/shmobile.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/of.h> | ||
17 | #include <linux/of_address.h> | ||
18 | #include <linux/spinlock.h> | ||
19 | |||
20 | struct r8a7740_cpg { | ||
21 | struct clk_onecell_data data; | ||
22 | spinlock_t lock; | ||
23 | void __iomem *reg; | ||
24 | }; | ||
25 | |||
26 | #define CPG_FRQCRA 0x00 | ||
27 | #define CPG_FRQCRB 0x04 | ||
28 | #define CPG_PLLC2CR 0x2c | ||
29 | #define CPG_USBCKCR 0x8c | ||
30 | #define CPG_FRQCRC 0xe0 | ||
31 | |||
32 | #define CLK_ENABLE_ON_INIT BIT(0) | ||
33 | |||
34 | struct div4_clk { | ||
35 | const char *name; | ||
36 | unsigned int reg; | ||
37 | unsigned int shift; | ||
38 | int flags; | ||
39 | }; | ||
40 | |||
41 | static struct div4_clk div4_clks[] = { | ||
42 | { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT }, | ||
43 | { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT }, | ||
44 | { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT }, | ||
45 | { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT }, | ||
46 | { "hp", CPG_FRQCRB, 4, 0 }, | ||
47 | { "hpp", CPG_FRQCRC, 20, 0 }, | ||
48 | { "usbp", CPG_FRQCRC, 16, 0 }, | ||
49 | { "s", CPG_FRQCRC, 12, 0 }, | ||
50 | { "zb", CPG_FRQCRC, 8, 0 }, | ||
51 | { "m3", CPG_FRQCRC, 4, 0 }, | ||
52 | { "cp", CPG_FRQCRC, 0, 0 }, | ||
53 | { NULL, 0, 0, 0 }, | ||
54 | }; | ||
55 | |||
56 | static const struct clk_div_table div4_div_table[] = { | ||
57 | { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, | ||
58 | { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 }, | ||
59 | { 13, 72 }, { 14, 96 }, { 0, 0 } | ||
60 | }; | ||
61 | |||
62 | static u32 cpg_mode __initdata; | ||
63 | |||
64 | static struct clk * __init | ||
65 | r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, | ||
66 | const char *name) | ||
67 | { | ||
68 | const struct clk_div_table *table = NULL; | ||
69 | const char *parent_name; | ||
70 | unsigned int shift, reg; | ||
71 | unsigned int mult = 1; | ||
72 | unsigned int div = 1; | ||
73 | |||
74 | if (!strcmp(name, "r")) { | ||
75 | switch (cpg_mode & (BIT(2) | BIT(1))) { | ||
76 | case BIT(1) | BIT(2): | ||
77 | /* extal1 */ | ||
78 | parent_name = of_clk_get_parent_name(np, 0); | ||
79 | div = 2048; | ||
80 | break; | ||
81 | case BIT(2): | ||
82 | /* extal1 */ | ||
83 | parent_name = of_clk_get_parent_name(np, 0); | ||
84 | div = 1024; | ||
85 | break; | ||
86 | default: | ||
87 | /* extalr */ | ||
88 | parent_name = of_clk_get_parent_name(np, 2); | ||
89 | break; | ||
90 | } | ||
91 | } else if (!strcmp(name, "system")) { | ||
92 | parent_name = of_clk_get_parent_name(np, 0); | ||
93 | if (cpg_mode & BIT(1)) | ||
94 | div = 2; | ||
95 | } else if (!strcmp(name, "pllc0")) { | ||
96 | /* PLLC0/1 are configurable multiplier clocks. Register them as | ||
97 | * fixed factor clocks for now as there's no generic multiplier | ||
98 | * clock implementation and we currently have no need to change | ||
99 | * the multiplier value. | ||
100 | */ | ||
101 | u32 value = clk_readl(cpg->reg + CPG_FRQCRC); | ||
102 | parent_name = "system"; | ||
103 | mult = ((value >> 24) & 0x7f) + 1; | ||
104 | } else if (!strcmp(name, "pllc1")) { | ||
105 | u32 value = clk_readl(cpg->reg + CPG_FRQCRA); | ||
106 | parent_name = "system"; | ||
107 | mult = ((value >> 24) & 0x7f) + 1; | ||
108 | div = 2; | ||
109 | } else if (!strcmp(name, "pllc2")) { | ||
110 | u32 value = clk_readl(cpg->reg + CPG_PLLC2CR); | ||
111 | parent_name = "system"; | ||
112 | mult = ((value >> 24) & 0x3f) + 1; | ||
113 | } else if (!strcmp(name, "usb24s")) { | ||
114 | u32 value = clk_readl(cpg->reg + CPG_USBCKCR); | ||
115 | if (value & BIT(7)) | ||
116 | /* extal2 */ | ||
117 | parent_name = of_clk_get_parent_name(np, 1); | ||
118 | else | ||
119 | parent_name = "system"; | ||
120 | if (!(value & BIT(6))) | ||
121 | div = 2; | ||
122 | } else { | ||
123 | struct div4_clk *c; | ||
124 | for (c = div4_clks; c->name; c++) { | ||
125 | if (!strcmp(name, c->name)) { | ||
126 | parent_name = "pllc1"; | ||
127 | table = div4_div_table; | ||
128 | reg = c->reg; | ||
129 | shift = c->shift; | ||
130 | break; | ||
131 | } | ||
132 | } | ||
133 | if (!c->name) | ||
134 | return ERR_PTR(-EINVAL); | ||
135 | } | ||
136 | |||
137 | if (!table) { | ||
138 | return clk_register_fixed_factor(NULL, name, parent_name, 0, | ||
139 | mult, div); | ||
140 | } else { | ||
141 | return clk_register_divider_table(NULL, name, parent_name, 0, | ||
142 | cpg->reg + reg, shift, 4, 0, | ||
143 | table, &cpg->lock); | ||
144 | } | ||
145 | } | ||
146 | |||
147 | static void __init r8a7740_cpg_clocks_init(struct device_node *np) | ||
148 | { | ||
149 | struct r8a7740_cpg *cpg; | ||
150 | struct clk **clks; | ||
151 | unsigned int i; | ||
152 | int num_clks; | ||
153 | |||
154 | if (of_property_read_u32(np, "renesas,mode", &cpg_mode)) | ||
155 | pr_warn("%s: missing renesas,mode property\n", __func__); | ||
156 | |||
157 | num_clks = of_property_count_strings(np, "clock-output-names"); | ||
158 | if (num_clks < 0) { | ||
159 | pr_err("%s: failed to count clocks\n", __func__); | ||
160 | return; | ||
161 | } | ||
162 | |||
163 | cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); | ||
164 | clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); | ||
165 | if (cpg == NULL || clks == NULL) { | ||
166 | /* We're leaking memory on purpose, there's no point in cleaning | ||
167 | * up as the system won't boot anyway. | ||
168 | */ | ||
169 | return; | ||
170 | } | ||
171 | |||
172 | spin_lock_init(&cpg->lock); | ||
173 | |||
174 | cpg->data.clks = clks; | ||
175 | cpg->data.clk_num = num_clks; | ||
176 | |||
177 | cpg->reg = of_iomap(np, 0); | ||
178 | if (WARN_ON(cpg->reg == NULL)) | ||
179 | return; | ||
180 | |||
181 | for (i = 0; i < num_clks; ++i) { | ||
182 | const char *name; | ||
183 | struct clk *clk; | ||
184 | |||
185 | of_property_read_string_index(np, "clock-output-names", i, | ||
186 | &name); | ||
187 | |||
188 | clk = r8a7740_cpg_register_clock(np, cpg, name); | ||
189 | if (IS_ERR(clk)) | ||
190 | pr_err("%s: failed to register %s %s clock (%ld)\n", | ||
191 | __func__, np->name, name, PTR_ERR(clk)); | ||
192 | else | ||
193 | cpg->data.clks[i] = clk; | ||
194 | } | ||
195 | |||
196 | of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); | ||
197 | } | ||
198 | CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks", | ||
199 | r8a7740_cpg_clocks_init); | ||