Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework changes from Mike Turquette:
 "The clock framework changes for 3.15 look similar to past pull
  requests.  Mostly clock driver updates, more Device Tree support in
  the form of common functions useful across platforms and a handful of
  features and fixes to the framework core"

* tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: shmobile: fix setting paretn clock rate
  clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
  clk: Fix minor errors in of_clk_init() function comments
  clk: reverse default clk provider initialization order in of_clk_init()
  clk: sirf: update copyright years to 2014
  clk: mmp: try to use closer one when do round rate
  clk: mmp: fix the wrong calculation formula
  clk: mmp: fix wrong mask when calculate denominator
  clk: st: Adds quadfs clock binding
  clk: st: Adds clockgen-vcc and clockgen-mux clock binding
  clk: st: Adds clockgen clock binding
  clk: st: Adds divmux and prediv clock binding
  clk: st: Support for A9 MUX clocks
  clk: st: Support for ClockGenA9/DDR/GPU
  clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
  clk: st: Support for VCC-mux and MUX clocks
  clk: st: Support for PLLs inside ClockGenA(s)
  clk: st: Support for DIVMUX and PreDiv Clocks
  clk: support hardware-specific debugfs entries
  clk: s2mps11: Use of_get_child_by_name
  ...

1 files changed, 9 insertions, 9 deletions

diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 3226f54fa595..cec97596fe65 100644
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
          * makes probably sense to redundantly save fbdiv in the struct
          * zynq_pll to save the IO access.
          */
-        fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+        fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
                         PLLCTRL_FBDIV_SHIFT;
 
         return parent_rate * fbdiv;
@@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw)
 
         spin_lock_irqsave(clk->lock, flags);
 
-        reg = readl(clk->pll_ctrl);
+        reg = clk_readl(clk->pll_ctrl);
 
         spin_unlock_irqrestore(clk->lock, flags);
 
@@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw)
         /* Power up PLL and wait for lock */
         spin_lock_irqsave(clk->lock, flags);
 
-        reg = readl(clk->pll_ctrl);
+        reg = clk_readl(clk->pll_ctrl);
         reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
-        writel(reg, clk->pll_ctrl);
-        while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
+        clk_writel(reg, clk->pll_ctrl);
+        while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
                 ;
 
         spin_unlock_irqrestore(clk->lock, flags);
@@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw)
         /* shut down PLL */
         spin_lock_irqsave(clk->lock, flags);
 
-        reg = readl(clk->pll_ctrl);
+        reg = clk_readl(clk->pll_ctrl);
         reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
-        writel(reg, clk->pll_ctrl);
+        clk_writel(reg, clk->pll_ctrl);
 
         spin_unlock_irqrestore(clk->lock, flags);
 }
@@ -225,9 +225,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent,
 
         spin_lock_irqsave(pll->lock, flags);
 
-        reg = readl(pll->pll_ctrl);
+        reg = clk_readl(pll->pll_ctrl);
         reg &= ~PLLCTRL_BPQUAL_MASK;
-        writel(reg, pll->pll_ctrl);
+        clk_writel(reg, pll->pll_ctrl);
 
         spin_unlock_irqrestore(pll->lock, flags);