Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical fixes from Olof Johansson:
 "Here is a collection of fixes (and some intermixed cleanups) that were
  considered less important and thus not included in the later parts of
  the 3.9-rc cycle.

  It's a bit all over the map, contents wise.  A series of ux500 fixes
  and cleanups, a bunch of various fixes for OMAP and tegra, and some
  for Freescale i.MX and even Qualcomm MSM.

  Note that there's also a patch on this branch to globally turn off
  -Wmaybe-uninitialized when building with -Os.  It's been posted
  several times by Arnd and no dissent was raised, but nobody seemed
  interested to pick it up.  So here it is, as the topmost patch."

* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
  Turn off -Wmaybe-uninitialized when building with -Os
  ARM: orion5x: include linux/cpu.h
  ARM: tegra: call cpu_do_idle from C code
  ARM: u300: fix ages old copy/paste bug
  ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
  ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled
  ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
  ARM: tegra: fix build error when THUMB2_KERNEL enabled
  ARM: msm: Fix uncompess.h tx underrun check
  ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms
  ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
  ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
  ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
  ARM: mach-imx: mach-imx6q: Fix sparse warnings
  ARM: mach-imx: src: Include "common.h
  ARM: mach-imx: gpc: Include "common.h"
  ARM: mach-imx: avic: Staticize *avic_base
  ARM: mach-imx: tzic: Staticize *tzic_base
  ARM: mach-imx: clk: Include "clk.h"
  ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
  ...

1 files changed, 2 insertions, 34 deletions

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index f873dcefe0de..bf194009e20f 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -711,8 +711,8 @@ static void tegra20_pll_init(void)
 }
 
 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-                                      "pll_p_cclk", "pll_p_out4_cclk",
-                                      "pll_p_out3_cclk", "clk_d", "pll_x" };
+                                      "pll_p", "pll_p_out4",
+                                      "pll_p_out3", "clk_d", "pll_x" };
 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
                                       "pll_p_out3", "pll_p_out2", "clk_d",
                                       "clk_32k", "pll_m_out1" };
@@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void)
 {
         struct clk *clk;
 
-        /*
-         * DIV_U71 dividers for CCLK, these dividers are used only
-         * if parent clock is fixed rate.
-         */
-
-        /*
-         * Clock input to cclk divided from pll_p using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_cclk", NULL);
-
-        /*
-         * Clock input to cclk divided from pll_p_out3 using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
-
-        /*
-         * Clock input to cclk divided from pll_p_out4 using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
-
         /* CCLK */
         clk = tegra_clk_register_super_mux("cclk", cclk_parents,
                               ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,