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authorStephen Warren <swarren@nvidia.com>2013-04-04 18:08:13 -0400
committerStephen Warren <swarren@nvidia.com>2013-04-04 18:08:13 -0400
commit43089433b00a086980fc6e9571535477fb749e84 (patch)
tree194817879be6f5cc5e56bc2ab2c3276af146238c /drivers/clk/tegra
parent8aa15d82df291b398d604b527a20310f10c1c706 (diff)
parent533ddeb1e86f506129ee388a6cc13796dcf31311 (diff)
Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into for-3.10/clk
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk.h27
1 files changed, 19 insertions, 8 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 0744731c6229..a09d7dcaf183 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -355,15 +355,16 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
355 struct tegra_clk_periph *periph, void __iomem *clk_base, 355 struct tegra_clk_periph *periph, void __iomem *clk_base,
356 u32 offset); 356 u32 offset);
357 357
358#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \ 358#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
359 _div_shift, _div_width, _div_frac_width, \ 359 _div_shift, _div_width, _div_frac_width, \
360 _div_flags, _clk_num, _enb_refcnt, _regs, \ 360 _div_flags, _clk_num, _enb_refcnt, _regs, \
361 _gate_flags) \ 361 _gate_flags, _table) \
362 { \ 362 { \
363 .mux = { \ 363 .mux = { \
364 .flags = _mux_flags, \ 364 .flags = _mux_flags, \
365 .shift = _mux_shift, \ 365 .shift = _mux_shift, \
366 .width = _mux_width, \ 366 .mask = _mux_mask, \
367 .table = _table, \
367 }, \ 368 }, \
368 .divider = { \ 369 .divider = { \
369 .flags = _div_flags, \ 370 .flags = _div_flags, \
@@ -393,26 +394,36 @@ struct tegra_periph_init_data {
393 const char *dev_id; 394 const char *dev_id;
394}; 395};
395 396
396#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \ 397#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
397 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 398 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
398 _div_width, _div_frac_width, _div_flags, _regs, \ 399 _div_width, _div_frac_width, _div_flags, _regs, \
399 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 400 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
400 { \ 401 { \
401 .name = _name, \ 402 .name = _name, \
402 .clk_id = _clk_id, \ 403 .clk_id = _clk_id, \
403 .parent_names = _parent_names, \ 404 .parent_names = _parent_names, \
404 .num_parents = ARRAY_SIZE(_parent_names), \ 405 .num_parents = ARRAY_SIZE(_parent_names), \
405 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \ 406 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
406 _mux_flags, _div_shift, \ 407 _mux_flags, _div_shift, \
407 _div_width, _div_frac_width, \ 408 _div_width, _div_frac_width, \
408 _div_flags, _clk_num, \ 409 _div_flags, _clk_num, \
409 _enb_refcnt, _regs, \ 410 _enb_refcnt, _regs, \
410 _gate_flags), \ 411 _gate_flags, _table), \
411 .offset = _offset, \ 412 .offset = _offset, \
412 .con_id = _con_id, \ 413 .con_id = _con_id, \
413 .dev_id = _dev_id, \ 414 .dev_id = _dev_id, \
414 } 415 }
415 416
417#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
418 _mux_shift, _mux_width, _mux_flags, _div_shift, \
419 _div_width, _div_frac_width, _div_flags, _regs, \
420 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \
421 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
422 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
423 _div_shift, _div_width, _div_frac_width, _div_flags, \
424 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
425 NULL)
426
416/** 427/**
417 * struct clk_super_mux - super clock 428 * struct clk_super_mux - super clock
418 * 429 *