clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

1 files changed, 10 insertions, 10 deletions

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index f215bf10c9ff..5c7b58b96911 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
 #define PLLE_BASE 0xe8
 #define PLLE_MISC 0xec
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLL_MISC_LOCK_ENABLE 18
 #define PLLDU_MISC_LOCK_ENABLE 22
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
         .misc_reg = PLLC_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .vco_max = 1200000000,
         .base_reg = PLLM_BASE,
         .misc_reg = PLLM_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
         .vco_max = 1400000000,
         .base_reg = PLLP_BASE,
         .misc_reg = PLLP_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
         .vco_max = 1400000000,
         .base_reg = PLLA_BASE,
         .misc_reg = PLLA_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -436,7 +436,7 @@ static struct tegra_clk_pll_params pll_d_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD_BASE,
         .misc_reg = PLLD_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
@@ -456,7 +456,7 @@ static struct tegra_clk_pll_params pll_u_params = {
         .vco_max = 960000000,
         .base_reg = PLLU_BASE,
         .misc_reg = PLLU_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
         .pdiv_tohw = pllu_p,
@@ -471,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .vco_max = 1200000000,
         .base_reg = PLLX_BASE,
         .misc_reg = PLLX_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -485,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
         .vco_max = 0,
         .base_reg = PLLE_BASE,
         .misc_reg = PLLE_MISC,
-        .lock_bit_idx = PLLE_MISC_LOCK,
+        .lock_mask = PLLE_MISC_LOCK,
         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
         .lock_delay = 0,
 };