diff options
author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-10-15 10:19:13 -0400 |
---|---|---|
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 11:46:49 -0500 |
commit | de4f30fd8403cd67449fbb9dc06a3d898fb9f10c (patch) | |
tree | b3de7152b5f04afe69b272c6e45dce33c91fae32 /drivers/clk/tegra/clk-tegra114.c | |
parent | 76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 (diff) |
clk: tegra: move PMC, fixed clocks to common files
Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
-rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 75 |
1 files changed, 1 insertions, 74 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 07098597db53..046dbed0c2c5 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c | |||
@@ -107,13 +107,6 @@ | |||
107 | #define PLLC_OUT 0x84 | 107 | #define PLLC_OUT 0x84 |
108 | #define PLLM_OUT 0x94 | 108 | #define PLLM_OUT 0x94 |
109 | 109 | ||
110 | #define PMC_CLK_OUT_CNTRL 0x1a8 | ||
111 | #define PMC_DPD_PADS_ORIDE 0x1c | ||
112 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 | ||
113 | #define PMC_CTRL 0 | ||
114 | #define PMC_CTRL_BLINK_ENB 7 | ||
115 | #define PMC_BLINK_TIMER 0x40 | ||
116 | |||
117 | #define OSC_CTRL 0x50 | 110 | #define OSC_CTRL 0x50 |
118 | #define OSC_CTRL_OSC_FREQ_SHIFT 28 | 111 | #define OSC_CTRL_OSC_FREQ_SHIFT 28 |
119 | #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 | 112 | #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 |
@@ -177,7 +170,6 @@ static DEFINE_SPINLOCK(pll_d_lock); | |||
177 | static DEFINE_SPINLOCK(pll_d2_lock); | 170 | static DEFINE_SPINLOCK(pll_d2_lock); |
178 | static DEFINE_SPINLOCK(pll_u_lock); | 171 | static DEFINE_SPINLOCK(pll_u_lock); |
179 | static DEFINE_SPINLOCK(pll_re_lock); | 172 | static DEFINE_SPINLOCK(pll_re_lock); |
180 | static DEFINE_SPINLOCK(clk_out_lock); | ||
181 | static DEFINE_SPINLOCK(sysrate_lock); | 173 | static DEFINE_SPINLOCK(sysrate_lock); |
182 | 174 | ||
183 | static struct div_nmp pllxc_nmp = { | 175 | static struct div_nmp pllxc_nmp = { |
@@ -1199,71 +1191,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base, | |||
1199 | clks[TEGRA114_CLK_PLL_E_OUT0] = clk; | 1191 | clks[TEGRA114_CLK_PLL_E_OUT0] = clk; |
1200 | } | 1192 | } |
1201 | 1193 | ||
1202 | static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", | ||
1203 | "clk_m_div4", "extern1", | ||
1204 | }; | ||
1205 | |||
1206 | static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", | ||
1207 | "clk_m_div4", "extern2", | ||
1208 | }; | ||
1209 | |||
1210 | static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", | ||
1211 | "clk_m_div4", "extern3", | ||
1212 | }; | ||
1213 | |||
1214 | static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) | ||
1215 | { | ||
1216 | struct clk *clk; | ||
1217 | |||
1218 | /* clk_out_1 */ | ||
1219 | clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, | ||
1220 | ARRAY_SIZE(clk_out1_parents), | ||
1221 | CLK_SET_RATE_NO_REPARENT, | ||
1222 | pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, | ||
1223 | &clk_out_lock); | ||
1224 | clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk; | ||
1225 | clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, | ||
1226 | pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, | ||
1227 | &clk_out_lock); | ||
1228 | clks[TEGRA114_CLK_CLK_OUT_1] = clk; | ||
1229 | |||
1230 | /* clk_out_2 */ | ||
1231 | clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, | ||
1232 | ARRAY_SIZE(clk_out2_parents), | ||
1233 | CLK_SET_RATE_NO_REPARENT, | ||
1234 | pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, | ||
1235 | &clk_out_lock); | ||
1236 | clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk; | ||
1237 | clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, | ||
1238 | pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, | ||
1239 | &clk_out_lock); | ||
1240 | clks[TEGRA114_CLK_CLK_OUT_2] = clk; | ||
1241 | |||
1242 | /* clk_out_3 */ | ||
1243 | clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, | ||
1244 | ARRAY_SIZE(clk_out3_parents), | ||
1245 | CLK_SET_RATE_NO_REPARENT, | ||
1246 | pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, | ||
1247 | &clk_out_lock); | ||
1248 | clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk; | ||
1249 | clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, | ||
1250 | pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, | ||
1251 | &clk_out_lock); | ||
1252 | clks[TEGRA114_CLK_CLK_OUT_3] = clk; | ||
1253 | |||
1254 | /* blink */ | ||
1255 | /* clear the blink timer register to directly output clk_32k */ | ||
1256 | writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); | ||
1257 | clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, | ||
1258 | pmc_base + PMC_DPD_PADS_ORIDE, | ||
1259 | PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); | ||
1260 | clk = clk_register_gate(NULL, "blink", "blink_override", 0, | ||
1261 | pmc_base + PMC_CTRL, | ||
1262 | PMC_CTRL_BLINK_ENB, 0, NULL); | ||
1263 | clks[TEGRA114_CLK_BLINK] = clk; | ||
1264 | |||
1265 | } | ||
1266 | |||
1267 | static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", | 1194 | static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", |
1268 | "pll_p", "pll_p_out2", "unused", | 1195 | "pll_p", "pll_p_out2", "unused", |
1269 | "clk_32k", "pll_m_out1" }; | 1196 | "clk_32k", "pll_m_out1" }; |
@@ -1612,7 +1539,7 @@ static void __init tegra114_clock_init(struct device_node *np) | |||
1612 | tegra114_pll_init(clk_base, pmc_base); | 1539 | tegra114_pll_init(clk_base, pmc_base); |
1613 | tegra114_periph_clk_init(clk_base, pmc_base); | 1540 | tegra114_periph_clk_init(clk_base, pmc_base); |
1614 | tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params); | 1541 | tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params); |
1615 | tegra114_pmc_clk_init(pmc_base); | 1542 | tegra_pmc_clk_init(pmc_base, tegra114_clks); |
1616 | tegra114_super_clk_init(clk_base); | 1543 | tegra114_super_clk_init(clk_base); |
1617 | 1544 | ||
1618 | tegra_add_of_provider(np); | 1545 | tegra_add_of_provider(np); |