Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into next

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.16 are pretty typical: mostly clock
  driver additions and fixes.  There are additions to the clock core
  code for some of the basic types (e.g. the common divider type has
  some fixes and featured added to it).

  One minor annoyance is a last-minute dependency that wasn't handled
  quite right.  Commit ba0fae3b06a6 ("clk: berlin: add core clock driver
  for BG2/BG2CD") in this pull request depends on
  include/dt-bindings/clock/berlin2.h, which is already in your tree via
  the arm-soc pull request.  Building for the berlin platform will break
  when the clk tree is built on it's own, but merged into your master
  branch everything should be fine"

* tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits)
  mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
  clk: export __clk_round_rate for providers
  clk: versatile: free icst on error return
  clk: qcom: Return error pointers for unimplemented clocks
  clk: qcom: Support msm8974pro global clock control hardware
  clk: qcom: Properly support display clocks on msm8974
  clk: qcom: Support display RCG clocks
  clk: qcom: Return highest rate when round_rate() exceeds plan
  clk: qcom: Fix mmcc-8974's PLL configurations
  clk: qcom: Fix clk_rcg2_is_enabled() check
  clk: berlin: add core clock driver for BG2Q
  clk: berlin: add core clock driver for BG2/BG2CD
  clk: berlin: add driver for BG2x complex divider cells
  clk: berlin: add driver for BG2x simple PLLs
  clk: berlin: add driver for BG2x audio/video PLL
  clk: st: Terminate of match table
  clk/exynos4: Fix compilation warning
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  clk: divider: Fix overflow in clk_divider_bestdiv
  clk: u300: Terminate of match table
  ...

2 files changed, 73 insertions, 0 deletions

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 9e232644f07e..3806d97e529b 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
         return rate;
 }
 
+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
+                                       unsigned long *best_parent_rate,
+                                       struct clk **best_parent_p)
+{
+        struct clk *clk = hw->clk, *parent, *best_parent = NULL;
+        int i, num_parents;
+        unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
+
+        /* find the parent that can help provide the fastest rate <= rate */
+        num_parents = __clk_get_num_parents(clk);
+        for (i = 0; i < num_parents; i++) {
+                parent = clk_get_parent_by_index(clk, i);
+                if (!parent)
+                        continue;
+                if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+                        parent_rate = __clk_round_rate(parent, rate);
+                else
+                        parent_rate = __clk_get_rate(parent);
+
+                child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
+
+                if (child_rate <= rate && child_rate > best_child_rate) {
+                        best_parent = parent;
+                        best = parent_rate;
+                        best_child_rate = child_rate;
+                }
+        }
+
+        if (best_parent)
+                *best_parent_p = best_parent;
+        *best_parent_rate = best;
+
+        return best_child_rate;
+}
+
 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long parent_rate)
 {
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 const struct clk_ops clk_factors_ops = {
+        .determine_rate = clk_factors_determine_rate,
         .recalc_rate = clk_factors_recalc_rate,
         .round_rate = clk_factors_round_rate,
         .set_rate = clk_factors_set_rate,
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9eddf22d56a4..426483422d3d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -507,6 +507,43 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
 
 
 /**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
+{
+        #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+        #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+        struct clk_hw *hw = __clk_get_hw(clk);
+        struct clk_composite *composite = to_clk_composite(hw);
+        struct clk_hw *rate_hw = composite->rate_hw;
+        struct clk_factors *factors = to_clk_factors(rate_hw);
+        unsigned long flags = 0;
+        u32 reg;
+
+        if (factors->lock)
+                spin_lock_irqsave(factors->lock, flags);
+
+        reg = readl(factors->reg);
+
+        /* set sample clock phase control */
+        reg &= ~(0x7 << 20);
+        reg |= ((sample & 0x7) << 20);
+
+        /* set output clock phase control */
+        reg &= ~(0x7 << 8);
+        reg |= ((output & 0x7) << 8);
+
+        writel(reg, factors->reg);
+
+        if (factors->lock)
+                spin_unlock_irqrestore(factors->lock, flags);
+}
+EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
+
+
+/**
  * sunxi_factors_clk_setup() - Setup function for factor clocks
  */