clk: st: STiH407: Support for clockgenC0

The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2 files changed, 83 insertions, 0 deletions

diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 4cd10b2e3b15..84fcf715bf96 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
         .get_rate       = clk_fs660c32_dig_get_rate,
 };
 
+static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+        .nrst_present = true,
+        .nrst   = { CLKGEN_FIELD(0x2f0, 0x1, 0),
+                    CLKGEN_FIELD(0x2f0, 0x1, 1),
+                    CLKGEN_FIELD(0x2f0, 0x1, 2),
+                    CLKGEN_FIELD(0x2f0, 0x1, 3) },
+        .npda   = CLKGEN_FIELD(0x2f0, 0x1, 12),
+        .nsb    = { CLKGEN_FIELD(0x2f0, 0x1, 8),
+                    CLKGEN_FIELD(0x2f0, 0x1, 9),
+                    CLKGEN_FIELD(0x2f0, 0x1, 10),
+                    CLKGEN_FIELD(0x2f0, 0x1, 11) },
+        .nsdiv_present = true,
+        .nsdiv  = { CLKGEN_FIELD(0x304, 0x1, 24),
+                    CLKGEN_FIELD(0x308, 0x1, 24),
+                    CLKGEN_FIELD(0x30c, 0x1, 24),
+                    CLKGEN_FIELD(0x310, 0x1, 24) },
+        .mdiv   = { CLKGEN_FIELD(0x304, 0x1f, 15),
+                    CLKGEN_FIELD(0x308, 0x1f, 15),
+                    CLKGEN_FIELD(0x30c, 0x1f, 15),
+                    CLKGEN_FIELD(0x310, 0x1f, 15) },
+        .en     = { CLKGEN_FIELD(0x2fc, 0x1, 0),
+                    CLKGEN_FIELD(0x2fc, 0x1, 1),
+                    CLKGEN_FIELD(0x2fc, 0x1, 2),
+                    CLKGEN_FIELD(0x2fc, 0x1, 3) },
+        .ndiv   = CLKGEN_FIELD(0x2f4, 0x7, 16),
+        .pe     = { CLKGEN_FIELD(0x304, 0x7fff, 0),
+                    CLKGEN_FIELD(0x308, 0x7fff, 0),
+                    CLKGEN_FIELD(0x30c, 0x7fff, 0),
+                    CLKGEN_FIELD(0x310, 0x7fff, 0) },
+        .sdiv   = { CLKGEN_FIELD(0x304, 0xf, 20),
+                    CLKGEN_FIELD(0x308, 0xf, 20),
+                    CLKGEN_FIELD(0x30c, 0xf, 20),
+                    CLKGEN_FIELD(0x310, 0xf, 20) },
+        .lockstatus_present = true,
+        .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+        .powerup_polarity = 1,
+        .standby_polarity = 1,
+        .pll_ops        = &st_quadfs_pll_c32_ops,
+        .rtbl           = fs660c32_rtbl,
+        .rtbl_cnt       = ARRAY_SIZE(fs660c32_rtbl),
+        .get_rate       = clk_fs660c32_dig_get_rate,
+};
+
 /**
  * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
  *
@@ -938,6 +981,14 @@ static struct of_device_id quadfs_of_match[] = {
                 .compatible = "st,stih416-quadfs660-F",
                 .data = &st_fs660c32_F_416
         },
+        {
+                .compatible = "st,stih407-quadfs660-C",
+                .data = &st_fs660c32_C_407
+        },
+        {
+                .compatible = "st,stih407-quadfs660-D",
+                .data = &st_fs660c32_D_407
+        },
         {}
 };
 
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d4ef4f479776..5327a7474c53 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -192,6 +192,30 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
         .ops            = &stm_pll3200c32_ops,
 };
 
+static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+        /* 407 C0 PLL0 */
+        .pdn_status     = CLKGEN_FIELD(0x2a0,   0x1,                    8),
+        .locked_status  = CLKGEN_FIELD(0x2a0,   0x1,                    24),
+        .ndiv           = CLKGEN_FIELD(0x2a4,   C32_NDIV_MASK,          16),
+        .idf            = CLKGEN_FIELD(0x2a4,   C32_IDF_MASK,           0x0),
+        .num_odfs = 1,
+        .odf            = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,           0) },
+        .odf_gate       = { CLKGEN_FIELD(0x2b4, 0x1,                    6) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
+static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+        /* 407 C0 PLL1 */
+        .pdn_status     = CLKGEN_FIELD(0x2c8,   0x1,                    8),
+        .locked_status  = CLKGEN_FIELD(0x2c8,   0x1,                    24),
+        .ndiv           = CLKGEN_FIELD(0x2cc,   C32_NDIV_MASK,          16),
+        .idf            = CLKGEN_FIELD(0x2cc,   C32_IDF_MASK,           0x0),
+        .num_odfs = 1,
+        .odf            = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK,           0) },
+        .odf_gate       = { CLKGEN_FIELD(0x2dc, 0x1,                    6) },
+        .ops            = &stm_pll3200c32_ops,
+};
+
 /**
  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  *
@@ -586,6 +610,14 @@ static struct of_device_id c32_pll_of_match[] = {
                 .compatible = "st,stih407-plls-c32-a0",
                 .data = &st_pll3200c32_407_a0,
         },
+        {
+                .compatible = "st,stih407-plls-c32-c0_0",
+                .data = &st_pll3200c32_407_c0_0,
+        },
+        {
+                .compatible = "st,stih407-plls-c32-c0_1",
+                .data = &st_pll3200c32_407_c0_1,
+        },
         {}
 };