diff options
author | Javier Martinez Canillas <javier.martinez@collabora.co.uk> | 2015-01-23 23:25:01 -0500 |
---|---|---|
committer | Kukjin Kim <kgene@kernel.org> | 2015-01-28 18:52:22 -0500 |
commit | 8856010029985ba4d63a8942deb7f9e780285dd2 (patch) | |
tree | b0f4c8c470d780021e31e5dd072e340a79bddf1d /drivers/clk/samsung | |
parent | 6591a02e17e6d6587c3cf7588d523fa6f26b584a (diff) |
clk: exynos5420: Add IDs for clocks used in DISP1 power domain
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:
ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)
Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 848d602efc06..07d666cc6a29 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c | |||
@@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { | |||
635 | SRC_TOP3, 0, 1), | 635 | SRC_TOP3, 0, 1), |
636 | MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, | 636 | MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, |
637 | SRC_TOP3, 4, 1), | 637 | SRC_TOP3, 4, 1), |
638 | MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p, | 638 | MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", |
639 | SRC_TOP3, 8, 1), | 639 | mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), |
640 | MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, | 640 | MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, |
641 | SRC_TOP3, 12, 1), | 641 | SRC_TOP3, 12, 1), |
642 | MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, | 642 | MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, |
@@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { | |||
663 | MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, | 663 | MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, |
664 | SRC_TOP4, 28, 1), | 664 | SRC_TOP4, 28, 1), |
665 | 665 | ||
666 | MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p, | 666 | MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", |
667 | SRC_TOP5, 0, 1), | 667 | mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), |
668 | MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, | 668 | MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, |
669 | SRC_TOP5, 4, 1), | 669 | SRC_TOP5, 4, 1), |
670 | MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, | 670 | MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, |
@@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { | |||
675 | SRC_TOP5, 16, 1), | 675 | SRC_TOP5, 16, 1), |
676 | MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, | 676 | MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, |
677 | SRC_TOP5, 20, 1), | 677 | SRC_TOP5, 20, 1), |
678 | MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, | 678 | MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", |
679 | SRC_TOP5, 24, 1), | 679 | mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), |
680 | MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, | 680 | MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, |
681 | SRC_TOP5, 28, 1), | 681 | SRC_TOP5, 28, 1), |
682 | 682 | ||
@@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { | |||
693 | SRC_TOP10, 0, 1), | 693 | SRC_TOP10, 0, 1), |
694 | MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, | 694 | MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, |
695 | SRC_TOP10, 4, 1), | 695 | SRC_TOP10, 4, 1), |
696 | MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), | 696 | MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, |
697 | SRC_TOP10, 8, 1), | ||
697 | MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, | 698 | MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, |
698 | SRC_TOP10, 12, 1), | 699 | SRC_TOP10, 12, 1), |
699 | MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, | 700 | MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, |
@@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { | |||
717 | MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, | 718 | MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, |
718 | SRC_TOP11, 28, 1), | 719 | SRC_TOP11, 28, 1), |
719 | 720 | ||
720 | MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p, | 721 | MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", |
721 | SRC_TOP12, 4, 1), | 722 | mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), |
722 | MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, | 723 | MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, |
723 | SRC_TOP12, 8, 1), | 724 | SRC_TOP12, 8, 1), |
724 | MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, | 725 | MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, |
@@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { | |||
726 | MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), | 727 | MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), |
727 | MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, | 728 | MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, |
728 | SRC_TOP12, 20, 1), | 729 | SRC_TOP12, 20, 1), |
729 | MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, | 730 | MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", |
730 | SRC_TOP12, 24, 1), | 731 | mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), |
731 | MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, | 732 | MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, |
732 | SRC_TOP12, 28, 1), | 733 | SRC_TOP12, 28, 1), |
733 | 734 | ||