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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:56:08 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:56:08 -0500
commit7e21774db5cc9cf8fe93a64a2f0c6cf47db8ab24 (patch)
tree460812792bc3b23789a83968b7bad840cc3eb047 /drivers/clk/samsung
parent0ba3307a8ec35252f7b1e222e32889a6f3d9ceb3 (diff)
parent2e84d75116c17c2034e917b411250d2d11755435 (diff)
Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c159
-rw-r--r--drivers/clk/samsung/clk-exynos4.c857
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c699
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c650
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c81
5 files changed, 1282 insertions, 1164 deletions
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 68e515d093d8..884187fbfe00 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -14,9 +14,17 @@
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of_address.h> 15#include <linux/of_address.h>
16#include <linux/syscore_ops.h> 16#include <linux/syscore_ops.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
17 19
18#include <dt-bindings/clk/exynos-audss-clk.h> 20#include <dt-bindings/clk/exynos-audss-clk.h>
19 21
22enum exynos_audss_clk_type {
23 TYPE_EXYNOS4210,
24 TYPE_EXYNOS5250,
25 TYPE_EXYNOS5420,
26};
27
20static DEFINE_SPINLOCK(lock); 28static DEFINE_SPINLOCK(lock);
21static struct clk **clk_table; 29static struct clk **clk_table;
22static void __iomem *reg_base; 30static void __iomem *reg_base;
@@ -26,10 +34,6 @@ static struct clk_onecell_data clk_data;
26#define ASS_CLK_DIV 0x4 34#define ASS_CLK_DIV 0x4
27#define ASS_CLK_GATE 0x8 35#define ASS_CLK_GATE 0x8
28 36
29/* list of all parent clock list */
30static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
31static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
32
33#ifdef CONFIG_PM_SLEEP 37#ifdef CONFIG_PM_SLEEP
34static unsigned long reg_save[][2] = { 38static unsigned long reg_save[][2] = {
35 {ASS_CLK_SRC, 0}, 39 {ASS_CLK_SRC, 0},
@@ -61,31 +65,69 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
61}; 65};
62#endif /* CONFIG_PM_SLEEP */ 66#endif /* CONFIG_PM_SLEEP */
63 67
68static const struct of_device_id exynos_audss_clk_of_match[] = {
69 { .compatible = "samsung,exynos4210-audss-clock",
70 .data = (void *)TYPE_EXYNOS4210, },
71 { .compatible = "samsung,exynos5250-audss-clock",
72 .data = (void *)TYPE_EXYNOS5250, },
73 { .compatible = "samsung,exynos5420-audss-clock",
74 .data = (void *)TYPE_EXYNOS5420, },
75 {},
76};
77
64/* register exynos_audss clocks */ 78/* register exynos_audss clocks */
65static void __init exynos_audss_clk_init(struct device_node *np) 79static int exynos_audss_clk_probe(struct platform_device *pdev)
66{ 80{
67 reg_base = of_iomap(np, 0); 81 int i, ret = 0;
68 if (!reg_base) { 82 struct resource *res;
69 pr_err("%s: failed to map audss registers\n", __func__); 83 const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
70 return; 84 const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
85 const char *sclk_pcm_p = "sclk_pcm0";
86 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
87 const struct of_device_id *match;
88 enum exynos_audss_clk_type variant;
89
90 match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
91 if (!match)
92 return -EINVAL;
93 variant = (enum exynos_audss_clk_type)match->data;
94
95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
96 reg_base = devm_ioremap_resource(&pdev->dev, res);
97 if (IS_ERR(reg_base)) {
98 dev_err(&pdev->dev, "failed to map audss registers\n");
99 return PTR_ERR(reg_base);
71 } 100 }
72 101
73 clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, 102 clk_table = devm_kzalloc(&pdev->dev,
103 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
74 GFP_KERNEL); 104 GFP_KERNEL);
75 if (!clk_table) { 105 if (!clk_table)
76 pr_err("%s: could not allocate clk lookup table\n", __func__); 106 return -ENOMEM;
77 return;
78 }
79 107
80 clk_data.clks = clk_table; 108 clk_data.clks = clk_table;
81 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; 109 if (variant == TYPE_EXYNOS5420)
82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 110 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
83 111 else
112 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
113
114 pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
115 pll_in = devm_clk_get(&pdev->dev, "pll_in");
116 if (!IS_ERR(pll_ref))
117 mout_audss_p[0] = __clk_get_name(pll_ref);
118 if (!IS_ERR(pll_in))
119 mout_audss_p[1] = __clk_get_name(pll_in);
84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", 120 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
85 mout_audss_p, ARRAY_SIZE(mout_audss_p), 121 mout_audss_p, ARRAY_SIZE(mout_audss_p),
86 CLK_SET_RATE_NO_REPARENT, 122 CLK_SET_RATE_NO_REPARENT,
87 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 123 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
88 124
125 cdclk = devm_clk_get(&pdev->dev, "cdclk");
126 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
127 if (!IS_ERR(cdclk))
128 mout_i2s_p[1] = __clk_get_name(cdclk);
129 if (!IS_ERR(sclk_audio))
130 mout_i2s_p[2] = __clk_get_name(sclk_audio);
89 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", 131 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
90 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 132 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
91 CLK_SET_RATE_NO_REPARENT, 133 CLK_SET_RATE_NO_REPARENT,
@@ -119,17 +161,88 @@ static void __init exynos_audss_clk_init(struct device_node *np)
119 "sclk_pcm", CLK_SET_RATE_PARENT, 161 "sclk_pcm", CLK_SET_RATE_PARENT,
120 reg_base + ASS_CLK_GATE, 4, 0, &lock); 162 reg_base + ASS_CLK_GATE, 4, 0, &lock);
121 163
164 sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
165 if (!IS_ERR(sclk_pcm_in))
166 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
122 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", 167 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
123 "div_pcm0", CLK_SET_RATE_PARENT, 168 sclk_pcm_p, CLK_SET_RATE_PARENT,
124 reg_base + ASS_CLK_GATE, 5, 0, &lock); 169 reg_base + ASS_CLK_GATE, 5, 0, &lock);
125 170
171 if (variant == TYPE_EXYNOS5420) {
172 clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
173 "dout_srp", CLK_SET_RATE_PARENT,
174 reg_base + ASS_CLK_GATE, 9, 0, &lock);
175 }
176
177 for (i = 0; i < clk_data.clk_num; i++) {
178 if (IS_ERR(clk_table[i])) {
179 dev_err(&pdev->dev, "failed to register clock %d\n", i);
180 ret = PTR_ERR(clk_table[i]);
181 goto unregister;
182 }
183 }
184
185 ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
186 &clk_data);
187 if (ret) {
188 dev_err(&pdev->dev, "failed to add clock provider\n");
189 goto unregister;
190 }
191
126#ifdef CONFIG_PM_SLEEP 192#ifdef CONFIG_PM_SLEEP
127 register_syscore_ops(&exynos_audss_clk_syscore_ops); 193 register_syscore_ops(&exynos_audss_clk_syscore_ops);
128#endif 194#endif
129 195
130 pr_info("Exynos: Audss: clock setup completed\n"); 196 dev_info(&pdev->dev, "setup completed\n");
197
198 return 0;
199
200unregister:
201 for (i = 0; i < clk_data.clk_num; i++) {
202 if (!IS_ERR(clk_table[i]))
203 clk_unregister(clk_table[i]);
204 }
205
206 return ret;
131} 207}
132CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", 208
133 exynos_audss_clk_init); 209static int exynos_audss_clk_remove(struct platform_device *pdev)
134CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", 210{
135 exynos_audss_clk_init); 211 int i;
212
213 of_clk_del_provider(pdev->dev.of_node);
214
215 for (i = 0; i < clk_data.clk_num; i++) {
216 if (!IS_ERR(clk_table[i]))
217 clk_unregister(clk_table[i]);
218 }
219
220 return 0;
221}
222
223static struct platform_driver exynos_audss_clk_driver = {
224 .driver = {
225 .name = "exynos-audss-clk",
226 .owner = THIS_MODULE,
227 .of_match_table = exynos_audss_clk_of_match,
228 },
229 .probe = exynos_audss_clk_probe,
230 .remove = exynos_audss_clk_remove,
231};
232
233static int __init exynos_audss_clk_init(void)
234{
235 return platform_driver_register(&exynos_audss_clk_driver);
236}
237core_initcall(exynos_audss_clk_init);
238
239static void __exit exynos_audss_clk_exit(void)
240{
241 platform_driver_unregister(&exynos_audss_clk_driver);
242}
243module_exit(exynos_audss_clk_exit);
244
245MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
246MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
247MODULE_LICENSE("GPL v2");
248MODULE_ALIAS("platform:exynos-audss-clk");
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 3852e44db0f8..010f071af883 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for all Exynos4 SoCs. 10 * Common Clock Framework support for all Exynos4 SoCs.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos4.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -130,68 +131,6 @@ enum exynos4_plls {
130}; 131};
131 132
132/* 133/*
133 * Let each supported clock get a unique id. This id is used to lookup the clock
134 * for device tree based platforms. The clocks are categorized into three
135 * sections: core, sclk gate and bus interface gate clocks.
136 *
137 * When adding a new clock to this list, it is advised to choose a clock
138 * category and add it to the end of that category. That is because the the
139 * device tree source file is referring to these ids and any change in the
140 * sequence number of existing clocks will require corresponding change in the
141 * device tree files. This limitation would go away when pre-processor support
142 * for dtc would be available.
143 */
144enum exynos4_clks {
145 none,
146
147 /* core clocks */
148 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
149 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
150 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
151 mout_apll, /* 20 */
152
153 /* gate for special clocks (sclk) */
154 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
155 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
156 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
157 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
158 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
159 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
160 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
161 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
162 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
163
164 /* gate clocks */
165 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
166 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
167 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
168 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
169 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
170 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
171 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
172 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
173 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
174 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
175 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
176 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
177 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
178 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
179 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
180 spi1_isp_sclk, uart_isp_sclk, tmu_apbif,
181
182 /* mux clocks */
183 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
184 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
185 aclk400_mcuisp,
186
187 /* div clocks */
188 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
189 div_aclk400_mcuisp,
190
191 nr_clks,
192};
193
194/*
195 * list of controller registers to be saved and restored during a 134 * list of controller registers to be saved and restored during a
196 * suspend/resume cycle. 135 * suspend/resume cycle.
197 */ 136 */
@@ -347,256 +286,256 @@ PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
347 286
348/* fixed rate clocks generated outside the soc */ 287/* fixed rate clocks generated outside the soc */
349static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 288static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
350 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), 289 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0),
351 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), 290 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0),
352}; 291};
353 292
354/* fixed rate clocks generated inside the soc */ 293/* fixed rate clocks generated inside the soc */
355static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 294static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
356 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 295 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
357 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 296 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
358 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 297 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
359}; 298};
360 299
361static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 300static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
362 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 301 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
363}; 302};
364 303
365/* list of mux clocks supported in all exynos4 soc's */ 304/* list of mux clocks supported in all exynos4 soc's */
366static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 305static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
367 MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 306 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
368 CLK_SET_RATE_PARENT, 0, "mout_apll"), 307 CLK_SET_RATE_PARENT, 0, "mout_apll"),
369 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 308 MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
370 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 309 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
371 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 310 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
372 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 311 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
373 CLK_SET_RATE_PARENT, 0), 312 CLK_SET_RATE_PARENT, 0),
374 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 313 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
375 CLK_SET_RATE_PARENT, 0), 314 CLK_SET_RATE_PARENT, 0),
376 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 315 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
377 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 316 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
378 MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 317 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
379 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 318 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
380}; 319};
381 320
382/* list of mux clocks supported in exynos4210 soc */ 321/* list of mux clocks supported in exynos4210 soc */
383static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 322static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
384 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 323 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
385}; 324};
386 325
387static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 326static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
388 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 327 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
389 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 328 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
390 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 329 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
391 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 330 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
392 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 331 MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
393 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 332 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
394 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 333 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
395 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 334 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
396 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 335 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
397 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 336 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
398 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 337 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
399 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 338 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
400 MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 339 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
401 MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 340 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
402 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 341 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
403 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 342 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
404 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 343 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
405 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 344 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
406 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 345 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
407 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 346 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
408 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 347 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
409 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 348 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
410 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 349 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
411 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 350 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
412 CLK_SET_RATE_PARENT, 0), 351 CLK_SET_RATE_PARENT, 0),
413 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 352 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
414 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 353 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
415 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 354 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
416 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 355 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
417 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 356 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
418 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 357 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
419 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 358 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
420 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 359 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
421 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 360 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
422 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 361 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
423 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 362 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
424 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 363 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
425 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 364 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
426 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 365 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
427 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 366 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
428 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 367 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
429 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 368 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
430 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 369 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
431 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 370 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
432}; 371};
433 372
434/* list of mux clocks supported in exynos4x12 soc */ 373/* list of mux clocks supported in exynos4x12 soc */
435static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 374static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
436 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, 375 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
437 SRC_CPU, 24, 1), 376 SRC_CPU, 24, 1),
438 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 377 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
439 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 378 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
440 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, 379 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
441 SRC_TOP1, 12, 1), 380 SRC_TOP1, 12, 1),
442 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 381 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
443 SRC_TOP1, 16, 1), 382 SRC_TOP1, 16, 1),
444 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 383 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
445 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, 384 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
446 SRC_TOP1, 24, 1), 385 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
447 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 386 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
448 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 387 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
449 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 388 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
450 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 389 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
451 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 390 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
452 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 391 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
453 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 392 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
454 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 393 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
455 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 394 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
456 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 395 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
457 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 396 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
458 MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 397 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
459 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 398 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
460 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 399 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
461 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 400 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
462 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 401 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
463 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 402 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
464 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 403 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
465 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 404 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
466 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 405 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
467 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 406 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
468 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 407 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
469 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 408 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
470 CLK_SET_RATE_PARENT, 0), 409 CLK_SET_RATE_PARENT, 0),
471 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 410 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
472 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 411 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
473 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 412 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
474 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 413 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
475 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 414 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
476 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 415 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
477 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 416 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
478 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 417 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
479 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 418 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
480 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 419 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
481 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 420 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
482 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 421 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
483 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 422 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
484 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 423 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
485 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 424 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
486 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 425 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
487 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 426 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
488 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 427 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
489 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 428 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
490 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 429 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
491 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 430 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
492 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 431 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
493 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 432 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
494 MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 433 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
495 MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 434 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
496 MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 435 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
497}; 436};
498 437
499/* list of divider clocks supported in all exynos4 soc's */ 438/* list of divider clocks supported in all exynos4 soc's */
500static struct samsung_div_clock exynos4_div_clks[] __initdata = { 439static struct samsung_div_clock exynos4_div_clks[] __initdata = {
501 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), 440 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
502 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), 441 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
503 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 442 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
504 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 443 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
505 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 444 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
506 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 445 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
507 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 446 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
508 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 447 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
509 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 448 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
510 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 449 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
511 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 450 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
512 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, 451 DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
513 CLK_SET_RATE_PARENT, 0), 452 CLK_SET_RATE_PARENT, 0),
514 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 453 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
515 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 454 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
516 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 455 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
517 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 456 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
518 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 457 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
519 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 458 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
520 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 459 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
521 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 460 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
522 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 461 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
523 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 462 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
524 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 463 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
525 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 464 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
526 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 465 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
527 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 466 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
528 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 467 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
529 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 468 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 469 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 470 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 471 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
533 DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8, 472 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
534 CLK_SET_RATE_PARENT, 0), 473 CLK_SET_RATE_PARENT, 0),
535 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 474 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
536 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 475 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
537 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 476 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
538 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 477 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
539 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 478 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
540 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 479 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
541 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 480 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
542 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 481 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
543 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 482 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
544 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 483 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
545 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 484 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
546 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 485 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
547 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 486 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
548 DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3), 487 DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
549 DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 488 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
550 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 489 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
551 CLK_SET_RATE_PARENT, 0), 490 CLK_SET_RATE_PARENT, 0),
552 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 491 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
553 CLK_SET_RATE_PARENT, 0), 492 CLK_SET_RATE_PARENT, 0),
554 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 493 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
555 CLK_SET_RATE_PARENT, 0), 494 CLK_SET_RATE_PARENT, 0),
556 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 495 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
557 CLK_SET_RATE_PARENT, 0), 496 CLK_SET_RATE_PARENT, 0),
558 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 497 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
559 CLK_SET_RATE_PARENT, 0), 498 CLK_SET_RATE_PARENT, 0),
560}; 499};
561 500
562/* list of divider clocks supported in exynos4210 soc */ 501/* list of divider clocks supported in exynos4210 soc */
563static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 502static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
564 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 503 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
565 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 504 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
566 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 505 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
567 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 506 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
568 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 507 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
569 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 508 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
570 CLK_SET_RATE_PARENT, 0), 509 CLK_SET_RATE_PARENT, 0),
571}; 510};
572 511
573/* list of divider clocks supported in exynos4x12 soc */ 512/* list of divider clocks supported in exynos4x12 soc */
574static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 513static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
575 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 514 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
576 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 515 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
577 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 516 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
578 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 517 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
579 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 518 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
580 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 519 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
581 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 520 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
582 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 521 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
583 DIV_TOP, 24, 3), 522 DIV_TOP, 24, 3),
584 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 523 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
585 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 524 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
586 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 525 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
587 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 526 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
588 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 527 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
589 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 528 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
590 DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 529 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
591 CLK_GET_RATE_NOCACHE, 0), 530 CLK_GET_RATE_NOCACHE, 0),
592 DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 531 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
593 CLK_GET_RATE_NOCACHE, 0), 532 CLK_GET_RATE_NOCACHE, 0),
594 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 533 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
595 DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 534 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
596 4, 3, CLK_GET_RATE_NOCACHE, 0), 535 4, 3, CLK_GET_RATE_NOCACHE, 0),
597 DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 536 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
598 8, 3, CLK_GET_RATE_NOCACHE, 0), 537 8, 3, CLK_GET_RATE_NOCACHE, 0),
599 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 538 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
600}; 539};
601 540
602/* list of gate clocks supported in all exynos4 soc's */ 541/* list of gate clocks supported in all exynos4 soc's */
@@ -606,333 +545,341 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
606 * the device name and clock alias names specified below for some 545 * the device name and clock alias names specified below for some
607 * of the clocks can be removed. 546 * of the clocks can be removed.
608 */ 547 */
609 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 548 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
610 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), 549 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
611 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 550 0),
612 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 551 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
613 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 552 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
614 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 553 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
615 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 554 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
616 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 555 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
617 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), 556 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
618 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 557 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
619 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 558 0),
620 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 559 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
560 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
561 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
621 CLK_SET_RATE_PARENT, 0), 562 CLK_SET_RATE_PARENT, 0),
622 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 563 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
623 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 564 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
624 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 565 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
625 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 566 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
626 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 567 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
627 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 568 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
628 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 569 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
629 CLK_SET_RATE_PARENT, 0), 570 CLK_SET_RATE_PARENT, 0),
630 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 571 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
631 CLK_SET_RATE_PARENT, 0), 572 CLK_SET_RATE_PARENT, 0),
632 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", 573 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
633 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 574 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
634 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 575 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
635 CLK_SET_RATE_PARENT, 0), 576 CLK_SET_RATE_PARENT, 0),
636 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 577 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
637 CLK_SET_RATE_PARENT, 0), 578 CLK_SET_RATE_PARENT, 0),
638 GATE(vp, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 579 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
639 GATE(mixer, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 580 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
640 GATE(hdmi, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 581 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
641 GATE(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 582 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
642 GATE(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 583 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
643 GATE(usb_host, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 584 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
644 GATE(sclk_fimc0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 585 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
645 CLK_SET_RATE_PARENT, 0), 586 CLK_SET_RATE_PARENT, 0),
646 GATE(sclk_fimc1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 587 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
647 CLK_SET_RATE_PARENT, 0), 588 CLK_SET_RATE_PARENT, 0),
648 GATE(sclk_fimc2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 589 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
649 CLK_SET_RATE_PARENT, 0), 590 CLK_SET_RATE_PARENT, 0),
650 GATE(sclk_fimc3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 591 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
651 CLK_SET_RATE_PARENT, 0), 592 CLK_SET_RATE_PARENT, 0),
652 GATE(sclk_csis0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 593 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
653 CLK_SET_RATE_PARENT, 0), 594 CLK_SET_RATE_PARENT, 0),
654 GATE(sclk_csis1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 595 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
655 CLK_SET_RATE_PARENT, 0), 596 CLK_SET_RATE_PARENT, 0),
656 GATE(sclk_fimd0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 597 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
657 CLK_SET_RATE_PARENT, 0), 598 CLK_SET_RATE_PARENT, 0),
658 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 599 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
659 CLK_SET_RATE_PARENT, 0), 600 CLK_SET_RATE_PARENT, 0),
660 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 601 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
661 CLK_SET_RATE_PARENT, 0), 602 CLK_SET_RATE_PARENT, 0),
662 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 603 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
663 CLK_SET_RATE_PARENT, 0), 604 CLK_SET_RATE_PARENT, 0),
664 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 605 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
665 CLK_SET_RATE_PARENT, 0), 606 CLK_SET_RATE_PARENT, 0),
666 GATE(sclk_mmc4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 607 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
667 CLK_SET_RATE_PARENT, 0), 608 CLK_SET_RATE_PARENT, 0),
668 GATE(sclk_uart0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 609 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
669 CLK_SET_RATE_PARENT, 0), 610 CLK_SET_RATE_PARENT, 0),
670 GATE(sclk_uart1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 611 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
671 CLK_SET_RATE_PARENT, 0), 612 CLK_SET_RATE_PARENT, 0),
672 GATE(sclk_uart2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 613 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
673 CLK_SET_RATE_PARENT, 0), 614 CLK_SET_RATE_PARENT, 0),
674 GATE(sclk_uart3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 615 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
675 CLK_SET_RATE_PARENT, 0), 616 CLK_SET_RATE_PARENT, 0),
676 GATE(sclk_uart4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 617 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
677 CLK_SET_RATE_PARENT, 0), 618 CLK_SET_RATE_PARENT, 0),
678 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 619 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
679 CLK_SET_RATE_PARENT, 0), 620 CLK_SET_RATE_PARENT, 0),
680 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 621 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
681 CLK_SET_RATE_PARENT, 0), 622 CLK_SET_RATE_PARENT, 0),
682 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 623 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
683 CLK_SET_RATE_PARENT, 0), 624 CLK_SET_RATE_PARENT, 0),
684 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 625 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
685 CLK_SET_RATE_PARENT, 0), 626 CLK_SET_RATE_PARENT, 0),
686 GATE(fimc0, "fimc0", "aclk160", GATE_IP_CAM, 0, 627 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
687 0, 0), 628 0, 0),
688 GATE(fimc1, "fimc1", "aclk160", GATE_IP_CAM, 1, 629 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
689 0, 0), 630 0, 0),
690 GATE(fimc2, "fimc2", "aclk160", GATE_IP_CAM, 2, 631 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
691 0, 0), 632 0, 0),
692 GATE(fimc3, "fimc3", "aclk160", GATE_IP_CAM, 3, 633 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
693 0, 0), 634 0, 0),
694 GATE(csis0, "csis0", "aclk160", GATE_IP_CAM, 4, 635 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
695 0, 0), 636 0, 0),
696 GATE(csis1, "csis1", "aclk160", GATE_IP_CAM, 5, 637 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
697 0, 0), 638 0, 0),
698 GATE(smmu_fimc0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 639 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
699 0, 0), 640 0, 0),
700 GATE(smmu_fimc1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 641 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
701 0, 0), 642 0, 0),
702 GATE(smmu_fimc2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 643 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
703 0, 0), 644 0, 0),
704 GATE(smmu_fimc3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 645 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
705 0, 0), 646 0, 0),
706 GATE(smmu_jpeg, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 647 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
707 0, 0), 648 0, 0),
708 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 649 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
709 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 650 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
710 GATE(smmu_tv, "smmu_tv", "aclk160", GATE_IP_TV, 4, 651 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
711 0, 0), 652 0, 0),
712 GATE(mfc, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 653 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
713 GATE(smmu_mfcl, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 654 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
714 0, 0), 655 0, 0),
715 GATE(smmu_mfcr, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 656 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
716 0, 0), 657 0, 0),
717 GATE(fimd0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 658 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
718 0, 0), 659 0, 0),
719 GATE(smmu_fimd0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 660 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
720 0, 0), 661 0, 0),
721 GATE(pdma0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 662 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
722 0, 0), 663 0, 0),
723 GATE(pdma1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 664 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
724 0, 0), 665 0, 0),
725 GATE(sdmmc0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 666 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
726 0, 0), 667 0, 0),
727 GATE(sdmmc1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 668 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
728 0, 0), 669 0, 0),
729 GATE(sdmmc2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 670 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
730 0, 0), 671 0, 0),
731 GATE(sdmmc3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 672 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
732 0, 0), 673 0, 0),
733 GATE(uart0, "uart0", "aclk100", GATE_IP_PERIL, 0, 674 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
734 0, 0), 675 0, 0),
735 GATE(uart1, "uart1", "aclk100", GATE_IP_PERIL, 1, 676 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
736 0, 0), 677 0, 0),
737 GATE(uart2, "uart2", "aclk100", GATE_IP_PERIL, 2, 678 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
738 0, 0), 679 0, 0),
739 GATE(uart3, "uart3", "aclk100", GATE_IP_PERIL, 3, 680 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
740 0, 0), 681 0, 0),
741 GATE(uart4, "uart4", "aclk100", GATE_IP_PERIL, 4, 682 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
742 0, 0), 683 0, 0),
743 GATE(i2c0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 684 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
744 0, 0), 685 0, 0),
745 GATE(i2c1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 686 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
746 0, 0), 687 0, 0),
747 GATE(i2c2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 688 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
748 0, 0), 689 0, 0),
749 GATE(i2c3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 690 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
750 0, 0), 691 0, 0),
751 GATE(i2c4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 692 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
752 0, 0), 693 0, 0),
753 GATE(i2c5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 694 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
754 0, 0), 695 0, 0),
755 GATE(i2c6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 696 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
756 0, 0), 697 0, 0),
757 GATE(i2c7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 698 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
758 0, 0), 699 0, 0),
759 GATE(i2c_hdmi, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 700 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
760 0, 0), 701 0, 0),
761 GATE(spi0, "spi0", "aclk100", GATE_IP_PERIL, 16, 702 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
762 0, 0), 703 0, 0),
763 GATE(spi1, "spi1", "aclk100", GATE_IP_PERIL, 17, 704 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
764 0, 0), 705 0, 0),
765 GATE(spi2, "spi2", "aclk100", GATE_IP_PERIL, 18, 706 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
766 0, 0), 707 0, 0),
767 GATE(i2s1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 708 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
768 0, 0), 709 0, 0),
769 GATE(i2s2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 710 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
770 0, 0), 711 0, 0),
771 GATE(pcm1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 712 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
772 0, 0), 713 0, 0),
773 GATE(pcm2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 714 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
774 0, 0), 715 0, 0),
775 GATE(spdif, "spdif", "aclk100", GATE_IP_PERIL, 26, 716 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
776 0, 0), 717 0, 0),
777 GATE(ac97, "ac97", "aclk100", GATE_IP_PERIL, 27, 718 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
778 0, 0), 719 0, 0),
779}; 720};
780 721
781/* list of gate clocks supported in exynos4210 soc */ 722/* list of gate clocks supported in exynos4210 soc */
782static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 723static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
783 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 724 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
784 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 725 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
785 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 726 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
786 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 727 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
787 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 728 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
788 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), 729 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
789 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 730 0),
790 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 731 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
791 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 732 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
792 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 733 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
793 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 734 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
794 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 735 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
795 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 736 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
796 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 737 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
738 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
797 CLK_IGNORE_UNUSED, 0), 739 CLK_IGNORE_UNUSED, 0),
798 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), 740 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
799 GATE(smmu_rotator, "smmu_rotator", "aclk200", 741 0),
742 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
800 E4210_GATE_IP_IMAGE, 4, 0, 0), 743 E4210_GATE_IP_IMAGE, 4, 0, 0),
801 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", 744 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
802 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 745 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
803 GATE(sclk_sata, "sclk_sata", "div_sata", 746 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
804 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 747 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
805 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 748 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
806 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 749 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
807 GATE(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 750 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
808 0, 0), 751 0, 0),
809 GATE(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 752 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
810 0, 0), 753 0, 0),
811 GATE(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 754 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
812 0, 0), 755 0, 0),
813 GATE(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 756 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
814 0, 0), 757 0, 0),
815 GATE(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 758 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
816 0, 0), 759 0, 0),
817 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 760 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
818 CLK_SET_RATE_PARENT, 0), 761 CLK_SET_RATE_PARENT, 0),
819 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), 762 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
763 0),
820}; 764};
821 765
822/* list of gate clocks supported in exynos4x12 soc */ 766/* list of gate clocks supported in exynos4x12 soc */
823static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 767static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
824 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 768 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
825 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 769 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
826 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 770 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
827 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 771 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
828 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), 772 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
829 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 773 0),
830 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 774 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
831 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 775 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
776 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
832 CLK_IGNORE_UNUSED, 0), 777 CLK_IGNORE_UNUSED, 0),
833 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), 778 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
834 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 779 0),
780 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
835 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 781 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
836 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 782 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
837 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 783 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
838 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", 784 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
839 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 785 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
840 GATE(smmu_rotator, "smmu_rotator", "aclk200", 786 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
841 E4X12_GATE_IP_IMAGE, 4, 0, 0), 787 E4X12_GATE_IP_IMAGE, 4, 0, 0),
842 GATE(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 788 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
843 0, 0), 789 0, 0),
844 GATE(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 790 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
845 0, 0), 791 0, 0),
846 GATE(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 792 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
847 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", 793 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp",
848 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 794 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
849 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", 795 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre",
850 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), 796 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
851 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", 797 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre",
852 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), 798 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
853 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", 799 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
854 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), 800 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
855 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", 801 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp",
856 E4X12_GATE_IP_ISP, 0, 0, 0), 802 E4X12_GATE_IP_ISP, 0, 0, 0),
857 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", 803 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp",
858 E4X12_GATE_IP_ISP, 1, 0, 0), 804 E4X12_GATE_IP_ISP, 1, 0, 0),
859 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", 805 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp",
860 E4X12_GATE_IP_ISP, 2, 0, 0), 806 E4X12_GATE_IP_ISP, 2, 0, 0),
861 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", 807 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp",
862 E4X12_GATE_IP_ISP, 3, 0, 0), 808 E4X12_GATE_IP_ISP, 3, 0, 0),
863 GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 809 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
864 GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 810 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
865 0, 0), 811 0, 0),
866 GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 812 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
867 0, 0), 813 0, 0),
868 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 814 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
869 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 815 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
870 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 816 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
871 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 817 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
872 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, 818 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
873 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 819 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
874 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 820 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
875 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 821 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
876 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 822 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
877 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 823 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
878 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 824 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
879 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 825 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
880 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 826 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
881 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 827 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
882 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 828 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
883 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 829 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
884 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 830 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
885 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 831 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
886 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 832 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
887 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 833 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
888 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 834 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
889 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 835 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
890 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 836 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
891 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 837 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
892 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 838 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
893 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 839 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
894 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 840 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
895 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 841 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
896 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 842 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
897 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 843 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
898 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 844 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
899 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 845 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
900 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 846 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
901 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 847 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
902 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 848 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
903 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 849 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
904 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 850 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
905 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 851 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
906 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 852 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
907 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 853 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
908 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 854 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
909 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 855 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
910 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 856 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
911 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 857 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
912 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 858 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
913 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 859 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
914 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 860 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
915 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 861 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
916 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 862 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
917 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 863 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
918 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 864 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
919 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 865 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
920 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 866 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
921 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), 867 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
868 0),
922}; 869};
923 870
924static struct samsung_clock_alias exynos4_aliases[] __initdata = { 871static struct samsung_clock_alias exynos4_aliases[] __initdata = {
925 ALIAS(mout_core, NULL, "moutcore"), 872 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
926 ALIAS(arm_clk, NULL, "armclk"), 873 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
927 ALIAS(sclk_apll, NULL, "mout_apll"), 874 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
928}; 875};
929 876
930static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 877static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
931 ALIAS(sclk_mpll, NULL, "mout_mpll"), 878 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
932}; 879};
933 880
934static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 881static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
935 ALIAS(mout_mpll_user_c, NULL, "mout_mpll"), 882 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
936}; 883};
937 884
938/* 885/*
@@ -978,7 +925,7 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
978 finpll_f = clk_get_rate(clk); 925 finpll_f = clk_get_rate(clk);
979 } 926 }
980 927
981 fclk.id = fin_pll; 928 fclk.id = CLK_FIN_PLL;
982 fclk.name = "fin_pll"; 929 fclk.name = "fin_pll";
983 fclk.parent_name = NULL; 930 fclk.parent_name = NULL;
984 fclk.flags = CLK_IS_ROOT; 931 fclk.flags = CLK_IS_ROOT;
@@ -1068,24 +1015,24 @@ static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
1068}; 1015};
1069 1016
1070static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1017static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1071 [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 1018 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1072 APLL_CON0, "fout_apll", NULL), 1019 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
1073 [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", 1020 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1074 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1021 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
1075 [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 1022 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1076 EPLL_CON0, "fout_epll", NULL), 1023 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
1077 [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc", 1024 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1078 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1025 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
1079}; 1026};
1080 1027
1081static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1028static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1082 [apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll", 1029 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1083 APLL_LOCK, APLL_CON0, NULL), 1030 APLL_LOCK, APLL_CON0, NULL),
1084 [mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", 1031 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1085 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1032 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1086 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", 1033 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1087 EPLL_LOCK, EPLL_CON0, NULL), 1034 EPLL_LOCK, EPLL_CON0, NULL),
1088 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", 1035 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1089 VPLL_LOCK, VPLL_CON0, NULL), 1036 VPLL_LOCK, VPLL_CON0, NULL),
1090}; 1037};
1091 1038
@@ -1099,11 +1046,11 @@ static void __init exynos4_clk_init(struct device_node *np,
1099 panic("%s: failed to map registers\n", __func__); 1046 panic("%s: failed to map registers\n", __func__);
1100 1047
1101 if (exynos4_soc == EXYNOS4210) 1048 if (exynos4_soc == EXYNOS4210)
1102 samsung_clk_init(np, reg_base, nr_clks, 1049 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
1103 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1050 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1104 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); 1051 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1105 else 1052 else
1106 samsung_clk_init(np, reg_base, nr_clks, 1053 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
1107 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1054 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1108 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); 1055 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1109 1056
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e52359cf9b6f..ff4beebe1f0b 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for Exynos5250 SoC. 10 * Common Clock Framework support for Exynos5250 SoC.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos5250.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -36,6 +37,7 @@
36#define GPLL_CON0 0x10150 37#define GPLL_CON0 0x10150
37#define SRC_TOP0 0x10210 38#define SRC_TOP0 0x10210
38#define SRC_TOP2 0x10218 39#define SRC_TOP2 0x10218
40#define SRC_TOP3 0x1021c
39#define SRC_GSCL 0x10220 41#define SRC_GSCL 0x10220
40#define SRC_DISP1_0 0x1022c 42#define SRC_DISP1_0 0x1022c
41#define SRC_MAU 0x10240 43#define SRC_MAU 0x10240
@@ -66,6 +68,7 @@
66#define DIV_PERIC4 0x10568 68#define DIV_PERIC4 0x10568
67#define DIV_PERIC5 0x1056c 69#define DIV_PERIC5 0x1056c
68#define GATE_IP_GSCL 0x10920 70#define GATE_IP_GSCL 0x10920
71#define GATE_IP_DISP1 0x10928
69#define GATE_IP_MFC 0x1092c 72#define GATE_IP_MFC 0x1092c
70#define GATE_IP_GEN 0x10934 73#define GATE_IP_GEN 0x10934
71#define GATE_IP_FSYS 0x10944 74#define GATE_IP_FSYS 0x10944
@@ -75,7 +78,6 @@
75#define BPLL_CON0 0x20110 78#define BPLL_CON0 0x20110
76#define SRC_CDREX 0x20200 79#define SRC_CDREX 0x20200
77#define PLL_DIV2_SEL 0x20a24 80#define PLL_DIV2_SEL 0x20a24
78#define GATE_IP_DISP1 0x10928
79 81
80/* list of PLLs to be registered */ 82/* list of PLLs to be registered */
81enum exynos5250_plls { 83enum exynos5250_plls {
@@ -84,52 +86,6 @@ enum exynos5250_plls {
84}; 86};
85 87
86/* 88/*
87 * Let each supported clock get a unique id. This id is used to lookup the clock
88 * for device tree based platforms. The clocks are categorized into three
89 * sections: core, sclk gate and bus interface gate clocks.
90 *
91 * When adding a new clock to this list, it is advised to choose a clock
92 * category and add it to the end of that category. That is because the the
93 * device tree source file is referring to these ids and any change in the
94 * sequence number of existing clocks will require corresponding change in the
95 * device tree files. This limitation would go away when pre-processor support
96 * for dtc would be available.
97 */
98enum exynos5250_clks {
99 none,
100
101 /* core clocks */
102 fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
103 fout_epll, fout_vpll,
104
105 /* gate for special clocks (sclk) */
106 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
107 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
108 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
109 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
110 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
111 div_i2s1, div_i2s2, sclk_hdmiphy,
112
113 /* gate clocks */
114 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
115 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
116 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
117 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
118 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
119 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
120 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
121 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
122 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
123 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
124 smmu_mdma0,
125
126 /* mux clocks */
127 mout_hdmi = 1024,
128
129 nr_clks,
130};
131
132/*
133 * list of controller registers to be saved and restored during a 89 * list of controller registers to be saved and restored during a
134 * suspend/resume cycle. 90 * suspend/resume cycle.
135 */ 91 */
@@ -139,6 +95,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
139 SRC_CORE1, 95 SRC_CORE1,
140 SRC_TOP0, 96 SRC_TOP0,
141 SRC_TOP2, 97 SRC_TOP2,
98 SRC_TOP3,
142 SRC_GSCL, 99 SRC_GSCL,
143 SRC_DISP1_0, 100 SRC_DISP1_0,
144 SRC_MAU, 101 SRC_MAU,
@@ -182,7 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
182 139
183/* list of all parent clock list */ 140/* list of all parent clock list */
184PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 141PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
185PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; 142PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
186PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 143PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
187PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 144PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
188PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 145PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
@@ -191,311 +148,432 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
191PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 148PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
192PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 149PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
193PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 150PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
194PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" }; 151PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
195PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" }; 152PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
196PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" }; 153PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
197PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" }; 154PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
155PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
156PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
157PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
198PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 158PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
199PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" }; 159PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
200PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 160PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
201 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", 161 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
202 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 162 "mout_mpll_user", "mout_epll", "mout_vpll",
203 "sclk_cpll" }; 163 "mout_cpll", "none", "none",
164 "none", "none", "none",
165 "none" };
204PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 166PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
205 "sclk_uhostphy", "sclk_hdmiphy", 167 "sclk_uhostphy", "fin_pll",
206 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 168 "mout_mpll_user", "mout_epll", "mout_vpll",
207 "sclk_cpll" }; 169 "mout_cpll", "none", "none",
170 "none", "none", "none",
171 "none" };
208PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 172PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
209 "sclk_uhostphy", "sclk_hdmiphy", 173 "sclk_uhostphy", "fin_pll",
210 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 174 "mout_mpll_user", "mout_epll", "mout_vpll",
211 "sclk_cpll" }; 175 "mout_cpll", "none", "none",
176 "none", "none", "none",
177 "none" };
212PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 178PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
213 "sclk_uhostphy", "sclk_hdmiphy", 179 "sclk_uhostphy", "fin_pll",
214 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 180 "mout_mpll_user", "mout_epll", "mout_vpll",
215 "sclk_cpll" }; 181 "mout_cpll", "none", "none",
182 "none", "none", "none",
183 "none" };
216PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 184PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
217 "spdif_extclk" }; 185 "spdif_extclk" };
218 186
219/* fixed rate clocks generated outside the soc */ 187/* fixed rate clocks generated outside the soc */
220static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 188static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
221 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 189 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
222}; 190};
223 191
224/* fixed rate clocks generated inside the soc */ 192/* fixed rate clocks generated inside the soc */
225static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 193static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
226 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 194 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
227 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 195 FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
228 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 196 FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
229 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 197 FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
230}; 198};
231 199
232static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 200static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
233 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 201 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
234 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 202 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
235}; 203};
236 204
237static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 205static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
238 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 206 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
239}; 207};
240 208
241static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 209static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
242 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), 210 /*
243 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 211 * NOTE: Following table is sorted by (clock domain, register address,
244 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 212 * bitfield shift) triplet in ascending order. When adding new entries,
245 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 213 * please make sure that the order is kept, to avoid merge conflicts
246 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 214 * and make further work with defined data easier.
247 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 215 */
248 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 216
249 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), 217 /*
250 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 218 * CMU_CPU
251 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 219 */
252 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 220 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
253 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 221 CLK_SET_RATE_PARENT, 0, "mout_apll"),
254 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 222 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
255 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 223
256 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 224 /*
257 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 225 * CMU_CORE
258 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 226 */
259 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 227 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
260 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 228
261 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 229 /*
262 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 230 * CMU_TOP
263 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 231 */
264 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 232 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
265 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 233 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
266 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 234 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
267 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 235
268 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 236 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
269 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 237 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
270 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 238 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
271 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 239 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
272 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 240 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
273 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 241
274 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 242 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
275 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 243 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
276 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 244 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
277 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 245
278 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 246 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
279 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 247 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
280 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 248 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
281 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 249 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
282 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 250 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
283 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 251
252 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
253 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
254 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
255 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
256
257 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
258
259 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
260 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
261 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
262 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
263 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
264 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
265
266 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
267
268 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
269 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
270 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
271 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
272 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
273
274 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
275 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
276 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
277 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
278 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
279 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
280
281 /*
282 * CMU_CDREX
283 */
284 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
285
286 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
287 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
284}; 288};
285 289
286static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 290static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
287 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 291 /*
288 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 292 * NOTE: Following table is sorted by (clock domain, register address,
289 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3), 293 * bitfield shift) triplet in ascending order. When adding new entries,
290 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), 294 * please make sure that the order is kept, to avoid merge conflicts
291 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3), 295 * and make further work with defined data easier.
292 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 296 */
293 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 297
294 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 298 /*
295 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 299 * CMU_CPU
296 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 300 */
297 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 301 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
298 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 302 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
299 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 303 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
300 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 304
301 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 305 /*
302 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 306 * CMU_TOP
303 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 307 */
304 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 308 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
305 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 309 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
306 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 310 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
307 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 311 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
308 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 312 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
309 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 313
310 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 314 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
311 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 315
312 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 316 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
313 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 317 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
314 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 318 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
315 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 319 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
316 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 320 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
317 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 321
318 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 322 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
319 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 323 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
320 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 324 DIV_F(0, "div_mipi1_pre", "div_mipi1",
321 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
322 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
323 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
324 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
325 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
326 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
327 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
328 DIV_F(none, "div_mipi1_pre", "div_mipi1",
329 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 325 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
330 DIV_F(none, "div_mmc_pre0", "div_mmc0", 326 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
327 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
328
329 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
330
331 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
332 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
333
334 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
335 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
336
337 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
338 DIV_F(0, "div_mmc_pre0", "div_mmc0",
331 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 339 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
332 DIV_F(none, "div_mmc_pre1", "div_mmc1", 340 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
341 DIV_F(0, "div_mmc_pre1", "div_mmc1",
333 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 342 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
334 DIV_F(none, "div_mmc_pre2", "div_mmc2", 343
344 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
345 DIV_F(0, "div_mmc_pre2", "div_mmc2",
335 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 346 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
336 DIV_F(none, "div_mmc_pre3", "div_mmc3", 347 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
348 DIV_F(0, "div_mmc_pre3", "div_mmc3",
337 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 349 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
338 DIV_F(none, "div_spi_pre0", "div_spi0", 350
351 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
352 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
353 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
354 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
355
356 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
357 DIV_F(0, "div_spi_pre0", "div_spi0",
339 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 358 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
340 DIV_F(none, "div_spi_pre1", "div_spi1", 359 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
360 DIV_F(0, "div_spi_pre1", "div_spi1",
341 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 361 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
342 DIV_F(none, "div_spi_pre2", "div_spi2", 362
363 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
364 DIV_F(0, "div_spi_pre2", "div_spi2",
343 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 365 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
366
367 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
368
369 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
370 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
371 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
372 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
373
374 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
375 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
344}; 376};
345 377
346static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 378static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
347 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), 379 /*
348 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), 380 * NOTE: Following table is sorted by (clock domain, register address,
349 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0), 381 * bitfield shift) triplet in ascending order. When adding new entries,
350 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0), 382 * please make sure that the order is kept, to avoid merge conflicts
351 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 383 * and make further work with defined data easier.
352 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 384 */
353 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0), 385
354 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0), 386 /*
355 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), 387 * CMU_ACP
356 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), 388 */
357 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 389 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
358 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0), 390 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
359 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0), 391 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
360 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 392
361 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0), 393 /*
362 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 394 * CMU_TOP
363 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 395 */
364 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0), 396 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
365 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
366 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
367 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
368 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
369 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
370 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
371 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
372 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
373 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
374 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
375 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
376 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
377 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
378 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
379 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
380 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
381 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
382 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
383 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
384 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
385 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
386 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
387 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
388 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
389 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
390 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
391 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
392 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
393 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
394 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
395 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
396 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
397 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
398 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
399 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
400 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
401 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
402 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
403 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
404 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
405 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
406 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
407 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
408 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
409 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
410 GATE(sysreg, "sysreg", "aclk66",
411 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
412 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
413 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
414 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
415 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
416 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
417 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
418 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
419 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
420 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
421 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
422 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
423 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
424 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
425 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
426 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
427 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
428 GATE(cmu_top, "cmu_top", "aclk66",
429 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
430 GATE(cmu_core, "cmu_core", "aclk66",
431 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
432 GATE(cmu_mem, "cmu_mem", "aclk66",
433 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
434 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
435 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 397 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_cam0, "sclk_cam0", "div_cam0", 398 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
437 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 399 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_cam1, "sclk_cam1", "div_cam1", 400 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
439 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 401 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa", 402 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
441 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 403 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
442 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb", 404 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
443 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 405 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
444 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", 406
407 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
445 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 408 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
446 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1", 409 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
447 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 410 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_dp, "sclk_dp", "div_dp", 411 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
449 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 412 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 413 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
451 SRC_MASK_DISP1_0, 20, 0, 0), 414 SRC_MASK_DISP1_0, 20, 0, 0),
452 GATE(sclk_audio0, "sclk_audio0", "div_audio0", 415
416 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
453 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 417 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
454 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", 418
419 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
455 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 420 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", 421 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
457 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 422 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", 423 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
459 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 424 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
460 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", 425 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
461 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 426 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
462 GATE(sclk_sata, "sclk_sata", "div_sata", 427 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
463 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 428 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
464 GATE(sclk_usb3, "sclk_usb3", "div_usb3", 429 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
465 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 430 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
466 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg", 431
432 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
467 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 433 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
468 GATE(sclk_uart0, "sclk_uart0", "div_uart0", 434
435 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
469 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 436 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
470 GATE(sclk_uart1, "sclk_uart1", "div_uart1", 437 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
471 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 438 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
472 GATE(sclk_uart2, "sclk_uart2", "div_uart2", 439 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
473 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 440 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
474 GATE(sclk_uart3, "sclk_uart3", "div_uart3", 441 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
475 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 442 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
476 GATE(sclk_pwm, "sclk_pwm", "div_pwm", 443 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
477 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 444 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
478 GATE(sclk_audio1, "sclk_audio1", "div_audio1", 445
446 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
479 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 447 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
480 GATE(sclk_audio2, "sclk_audio2", "div_audio2", 448 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
481 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 449 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
482 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 450 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
483 SRC_MASK_PERIC1, 4, 0, 0), 451 SRC_MASK_PERIC1, 4, 0, 0),
484 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", 452 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
485 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 453 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
486 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", 454 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
487 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 455 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
488 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", 456 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
489 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 457 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
490 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0), 458
491 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0), 459 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
492 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0), 460 0),
493 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0), 461 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
494 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 462 0),
495 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 463 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
496 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), 464 0),
497 GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0), 465 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
498 GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0), 466 0),
467 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
468 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
469 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
470 GATE_IP_GSCL, 7, 0, 0),
471 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
472 GATE_IP_GSCL, 8, 0, 0),
473 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
474 GATE_IP_GSCL, 9, 0, 0),
475 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
476 GATE_IP_GSCL, 10, 0, 0),
477
478 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
479 0),
480 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
481 0),
482 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
483 0),
484 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
485 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
486 0),
487 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
488 0),
489
490 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
491 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
492 0),
493 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
494 0),
495
496 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
497 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
498 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
499 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
500 0),
501 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
502 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
503
504 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
505 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
506 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
507 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
508 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
509 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
510 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
511 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
512 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
513 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
514 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
515 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
516 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
517 GATE_IP_FSYS, 24, 0, 0),
518 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
519 0),
520
521 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
522 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
523 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
524 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
525 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
526 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
527 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
528 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
529 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
530 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
531 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
532 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
533 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
534 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
535 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
536 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
537 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
538 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
539 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
540 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
541 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
542 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
543 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
544 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
545 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
546 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
547 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
548 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
549 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
550
551 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
552 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
553 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
554 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
555 0),
556 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
557 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
558 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
559 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
560 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
561 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
562 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
563 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
564 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
565 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
566 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
567 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
568 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
569 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
570 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
571 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
572 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
573 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
574 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
575 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
576 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
499}; 577};
500 578
501static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 579static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
@@ -521,20 +599,41 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
521 { }, 599 { },
522}; 600};
523 601
602static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
603 /* sorted in descending order */
604 /* PLL_35XX_RATE(rate, m, p, s) */
605 PLL_35XX_RATE(1700000000, 425, 6, 0),
606 PLL_35XX_RATE(1600000000, 200, 3, 0),
607 PLL_35XX_RATE(1500000000, 250, 4, 0),
608 PLL_35XX_RATE(1400000000, 175, 3, 0),
609 PLL_35XX_RATE(1300000000, 325, 6, 0),
610 PLL_35XX_RATE(1200000000, 200, 4, 0),
611 PLL_35XX_RATE(1100000000, 275, 6, 0),
612 PLL_35XX_RATE(1000000000, 125, 3, 0),
613 PLL_35XX_RATE(900000000, 150, 4, 0),
614 PLL_35XX_RATE(800000000, 100, 3, 0),
615 PLL_35XX_RATE(700000000, 175, 3, 1),
616 PLL_35XX_RATE(600000000, 200, 4, 1),
617 PLL_35XX_RATE(500000000, 125, 3, 1),
618 PLL_35XX_RATE(400000000, 100, 3, 1),
619 PLL_35XX_RATE(300000000, 200, 4, 2),
620 PLL_35XX_RATE(200000000, 100, 3, 2),
621};
622
524static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 623static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
525 [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 624 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
526 APLL_CON0, "fout_apll", NULL), 625 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
527 [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 626 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
528 MPLL_CON0, "fout_mpll", NULL), 627 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
529 [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 628 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
530 BPLL_CON0, NULL), 629 BPLL_CON0, NULL),
531 [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK, 630 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
532 GPLL_CON0, NULL), 631 GPLL_CON0, NULL),
533 [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK, 632 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
534 CPLL_CON0, NULL), 633 CPLL_CON0, NULL),
535 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 634 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
536 EPLL_CON0, NULL), 635 EPLL_CON0, NULL),
537 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc", 636 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
538 VPLL_LOCK, VPLL_CON0, NULL), 637 VPLL_LOCK, VPLL_CON0, NULL),
539}; 638};
540 639
@@ -556,7 +655,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
556 panic("%s: unable to determine soc\n", __func__); 655 panic("%s: unable to determine soc\n", __func__);
557 } 656 }
558 657
559 samsung_clk_init(np, reg_base, nr_clks, 658 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
560 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs), 659 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
561 NULL, 0); 660 NULL, 0);
562 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 661 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
@@ -565,8 +664,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
565 samsung_clk_register_mux(exynos5250_pll_pmux_clks, 664 samsung_clk_register_mux(exynos5250_pll_pmux_clks,
566 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 665 ARRAY_SIZE(exynos5250_pll_pmux_clks));
567 666
568 if (_get_rate("fin_pll") == 24 * MHZ) 667 if (_get_rate("fin_pll") == 24 * MHZ) {
569 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; 668 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
669 exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
670 }
570 671
571 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 672 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
572 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 673 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
@@ -585,6 +686,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
585 ARRAY_SIZE(exynos5250_gate_clks)); 686 ARRAY_SIZE(exynos5250_gate_clks));
586 687
587 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 688 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
588 _get_rate("armclk")); 689 _get_rate("div_arm2"));
589} 690}
590CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); 691CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 48c4a9350b91..ab4f2f7d88ef 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for Exynos5420 SoC. 10 * Common Clock Framework support for Exynos5420 SoC.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos5420.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -107,48 +108,6 @@ enum exynos5420_plls {
107 nr_plls /* number of PLLs */ 108 nr_plls /* number of PLLs */
108}; 109};
109 110
110enum exynos5420_clks {
111 none,
112
113 /* core clocks */
114 fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
115 fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
116
117 /* gate for special clocks (sclk) */
118 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
119 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
120 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
121 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
122 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
123 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
124
125 /* gate clocks */
126 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
127 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
128 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
129 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
130 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
131 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
132 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
133 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
134 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
135 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
136 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
137 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
138 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
139 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
140 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
141 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
142
143 /* mux clocks */
144 mout_hdmi = 640,
145
146 /* divider clocks */
147 dout_pixel = 768,
148
149 nr_clks,
150};
151
152/* 111/*
153 * list of controller registers to be saved and restored during a 112 * list of controller registers to be saved and restored during a
154 * suspend/resume cycle. 113 * suspend/resume cycle.
@@ -298,225 +257,226 @@ PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
298 257
299/* fixed rate clocks generated outside the soc */ 258/* fixed rate clocks generated outside the soc */
300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 259static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
301 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 260 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
302}; 261};
303 262
304/* fixed rate clocks generated inside the soc */ 263/* fixed rate clocks generated inside the soc */
305static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 264static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
306 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 265 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
307 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 266 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
308 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 267 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
309 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 268 FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
310 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 269 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
311}; 270};
312 271
313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 272static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
314 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 273 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
315}; 274};
316 275
317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 276static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
318 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 277 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
319 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 278 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
320 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), 279 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
321 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 280 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
322 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 281 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
323 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 282 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
324 283
325 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 284 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
326 285
327 MUX_A(none, "mout_aclk400_mscl", group1_p, 286 MUX_A(0, "mout_aclk400_mscl", group1_p,
328 SRC_TOP0, 4, 2, "aclk400_mscl"), 287 SRC_TOP0, 4, 2, "aclk400_mscl"),
329 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 288 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
330 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 289 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
331 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 290 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
332 291
333 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 292 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
334 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 293 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
335 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 294 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
336 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 295 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
337 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 296 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
338 297
339 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 298 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
340 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 299 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
341 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 300 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
342 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 301 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
343 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 302 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
344 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 303 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
345 304
346 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 305 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
347 SRC_TOP3, 4, 1), 306 SRC_TOP3, 4, 1),
348 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p, 307 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
349 SRC_TOP3, 8, 1, "aclk200_disp1"), 308 SRC_TOP3, 8, 1, "aclk200_disp1"),
350 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 309 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
351 SRC_TOP3, 12, 1), 310 SRC_TOP3, 12, 1),
352 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 311 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
353 SRC_TOP3, 28, 1), 312 SRC_TOP3, 28, 1),
354 313
355 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 314 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
356 SRC_TOP4, 0, 1), 315 SRC_TOP4, 0, 1),
357 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 316 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
358 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 317 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
359 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 318 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
360 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 319 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
361 320
362 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 321 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
363 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 322 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
364 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 323 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
365 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p, 324 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
366 SRC_TOP5, 16, 1, "aclkg3d"), 325 SRC_TOP5, 16, 1, "aclkg3d"),
367 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 326 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
368 SRC_TOP5, 20, 1), 327 SRC_TOP5, 20, 1),
369 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 328 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
370 SRC_TOP5, 24, 1), 329 SRC_TOP5, 24, 1),
371 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 330 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
372 SRC_TOP5, 28, 1), 331 SRC_TOP5, 28, 1),
373 332
374 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 333 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
375 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 334 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
376 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 335 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
377 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 336 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
378 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 337 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
379 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 338 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
380 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 339 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
381 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 340 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
382 341
383 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 342 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
384 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 343 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
385 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 344 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
386 SRC_TOP10, 12, 1), 345 SRC_TOP10, 12, 1),
387 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 346 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
388 347
389 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 348 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
390 SRC_TOP11, 0, 1), 349 SRC_TOP11, 0, 1),
391 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 350 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
392 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 351 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
393 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 352 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
394 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 353 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
395 354
396 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 355 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
397 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 356 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
398 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 357 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
399 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 358 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
400 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 359 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
401 SRC_TOP12, 24, 1), 360 SRC_TOP12, 24, 1),
402 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 361 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
403 362
404 /* DISP1 Block */ 363 /* DISP1 Block */
405 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 364 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
406 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 365 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
407 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 366 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
408 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 367 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
409 MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 368 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
410 369
411 /* MAU Block */ 370 /* MAU Block */
412 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 371 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
413 372
414 /* FSYS Block */ 373 /* FSYS Block */
415 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 374 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
416 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 375 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
417 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 376 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
418 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 377 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
419 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 378 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
420 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 379 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
421 380
422 /* PERIC Block */ 381 /* PERIC Block */
423 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 382 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
424 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 383 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
425 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 384 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
426 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 385 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
427 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 386 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
428 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 387 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
429 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 388 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
430 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 389 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
431 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 390 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
432 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 391 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
433 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 392 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
434 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 393 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
435}; 394};
436 395
437static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 396static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
438 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 397 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 398 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3), 399 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 400 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
442 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 401 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 402
444 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 403 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 404 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 405 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
447 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 406 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 407 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 408
450 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 409 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451 DIV_TOP1, 0, 3), 410 DIV_TOP1, 0, 3),
452 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 411 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
453 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 412 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 413 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 414 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
456 415
457 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 416 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
458 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 417 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 418 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 419 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1", 420 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
462 DIV_TOP2, 24, 3, "aclk300_disp1"), 421 DIV_TOP2, 24, 3, "aclk300_disp1"),
463 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 422 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 423
465 /* DISP1 Block */ 424 /* DISP1 Block */
466 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 425 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
467 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 426 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 427 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469 DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 428 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
470 429
471 /* Audio Block */ 430 /* Audio Block */
472 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 431 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
473 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 432 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
474 433
475 /* USB3.0 */ 434 /* USB3.0 */
476 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 435 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
477 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 436 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
478 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 437 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
479 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 438 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
480 439
481 /* MMC */ 440 /* MMC */
482 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 441 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
483 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 442 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
484 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 443 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 444
486 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 445 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
487 446
488 /* UART and PWM */ 447 /* UART and PWM */
489 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 448 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
490 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 449 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
491 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 450 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
492 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 451 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
493 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 452 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
494 453
495 /* SPI */ 454 /* SPI */
496 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 455 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
497 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 456 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 457 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 458
500 /* PCM */ 459 /* PCM */
501 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 460 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 461 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
503 462
504 /* Audio - I2S */ 463 /* Audio - I2S */
505 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 464 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
506 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 465 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
507 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 466 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
508 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 467 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
509 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 468 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 469
511 /* SPI Pre-Ratio */ 470 /* SPI Pre-Ratio */
512 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 471 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
513 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 472 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
514 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 473 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
515}; 474};
516 475
517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 476static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
518 /* TODO: Re-verify the CG bits for all the gate clocks */ 477 /* TODO: Re-verify the CG bits for all the gate clocks */
519 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), 478 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
479 "mct"),
520 480
521 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 481 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
522 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 482 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -545,217 +505,227 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
545 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 505 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
546 506
547 /* sclk */ 507 /* sclk */
548 GATE(sclk_uart0, "sclk_uart0", "dout_uart0", 508 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
549 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 509 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_uart1, "sclk_uart1", "dout_uart1", 510 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
551 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 511 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_uart2, "sclk_uart2", "dout_uart2", 512 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
553 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 513 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
554 GATE(sclk_uart3, "sclk_uart3", "dout_uart3", 514 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
555 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 515 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
556 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0", 516 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
557 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 517 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
558 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1", 518 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
559 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 519 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2", 520 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
561 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 521 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
562 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 522 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
563 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 523 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
564 GATE(sclk_pwm, "sclk_pwm", "dout_pwm", 524 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
565 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 525 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1", 526 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
567 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 527 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
568 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2", 528 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
569 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 529 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
570 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1", 530 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
571 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 531 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
572 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2", 532 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
573 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 533 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
574 534
575 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0", 535 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
576 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 536 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
577 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1", 537 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
578 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 538 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
579 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2", 539 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
580 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 540 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
581 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301", 541 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
582 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 542 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
583 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300", 543 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
584 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 544 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
585 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300", 545 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
586 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 546 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
587 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301", 547 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
588 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 548 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
589 549
590 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro", 550 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
591 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 551 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
592 552
593 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl", 553 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
594 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 554 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
595 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl", 555 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
596 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 556 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
597 557
598 /* Display */ 558 /* Display */
599 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1", 559 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
600 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 560 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
601 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1", 561 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
602 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 562 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
603 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 563 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
604 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 564 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
605 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", 565 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
606 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 566 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
607 GATE(sclk_dp1, "sclk_dp1", "dout_dp1", 567 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
608 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 568 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
609 569
610 /* Maudio Block */ 570 /* Maudio Block */
611 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0", 571 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
612 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 572 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
613 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0", 573 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
614 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 574 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
615 /* FSYS */ 575 /* FSYS */
616 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 576 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
617 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 577 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
618 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 578 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
619 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 579 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
620 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 580 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
621 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 581 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
622 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 582 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
623 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 583 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
624 GATE(sromc, "sromc", "aclk200_fsys2", 584 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
625 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 585 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
626 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 586 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
627 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 587 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
628 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 588 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
629 589
630 /* UART */ 590 /* UART */
631 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 591 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
632 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 592 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
633 GATE_A(uart2, "uart2", "aclk66_peric", 593 GATE_A(CLK_UART2, "uart2", "aclk66_peric",
634 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 594 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
635 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 595 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
636 /* I2C */ 596 /* I2C */
637 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 597 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
638 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 598 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
639 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 599 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
640 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 600 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
641 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 601 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
642 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 602 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
643 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 603 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
644 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 604 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
645 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0), 605 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
646 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 606 0),
607 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
647 /* SPI */ 608 /* SPI */
648 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 609 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
649 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 610 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
650 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 611 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
651 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 612 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
652 /* I2S */ 613 /* I2S */
653 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 614 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
654 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 615 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
655 /* PCM */ 616 /* PCM */
656 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 617 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
657 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 618 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
658 /* PWM */ 619 /* PWM */
659 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 620 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
660 /* SPDIF */ 621 /* SPDIF */
661 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 622 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
662 623
663 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 624 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
664 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 625 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
665 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 626 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
666 627
667 GATE(chipid, "chipid", "aclk66_psgen", 628 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
668 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 629 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
669 GATE(sysreg, "sysreg", "aclk66_psgen", 630 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
670 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 631 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
671 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 632 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
672 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 633 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
673 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 634 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
674 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 635 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
675 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 636 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
676 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 637 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
677 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 638 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
678 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 639 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
679 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 640 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
680 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 641 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
681 642
682 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0), 643 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
683 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 644 0),
684 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 645 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
685 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 646 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
686 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 647 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
687 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 648 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
688 649 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
689 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 650
690 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 651 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
691 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 652 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
692 653 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
693 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0), 654
694 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl", 655 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
656 0),
657 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
695 GATE_IP_GSCL1, 3, 0, 0), 658 GATE_IP_GSCL1, 3, 0, 0),
696 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl", 659 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
697 GATE_IP_GSCL1, 4, 0, 0), 660 GATE_IP_GSCL1, 4, 0, 0),
698 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0), 661 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
699 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0), 662 0),
700 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 663 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
701 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 664 0),
702 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl", 665 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
666 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
667 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
703 GATE_IP_GSCL1, 16, 0, 0), 668 GATE_IP_GSCL1, 16, 0, 0),
704 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl", 669 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
705 GATE_IP_GSCL1, 17, 0, 0), 670 GATE_IP_GSCL1, 17, 0, 0),
706 671
707 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 672 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
708 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 673 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
709 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 674 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
710 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 675 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
711 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 676 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
712 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0), 677 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
713 678 0),
714 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 679
715 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 680 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
716 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 681 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
717 682 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
718 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 683
719 684 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
720 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 685
721 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 686 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
722 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 687 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
723 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 688 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
724 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 689 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
725 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 690 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
726 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 691 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
727 692 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
728 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 693
729 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 694 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
730 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 695 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
731 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), 696 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
732 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), 697 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
733 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), 698 0),
734 GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), 699 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
700 0),
701 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
702 0),
703 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
704 0),
735}; 705};
736 706
737static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 707static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
738 [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 708 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
739 APLL_CON0, NULL), 709 APLL_CON0, NULL),
740 [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 710 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
741 MPLL_CON0, NULL), 711 CPLL_CON0, NULL),
742 [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, 712 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
743 DPLL_CON0, NULL), 713 DPLL_CON0, NULL),
744 [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 714 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
745 EPLL_CON0, NULL), 715 EPLL_CON0, NULL),
746 [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK, 716 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
747 RPLL_CON0, NULL), 717 RPLL_CON0, NULL),
748 [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK, 718 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
749 IPLL_CON0, NULL), 719 IPLL_CON0, NULL),
750 [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK, 720 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
751 SPLL_CON0, NULL), 721 SPLL_CON0, NULL),
752 [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, 722 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
753 VPLL_CON0, NULL), 723 VPLL_CON0, NULL),
754 [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 724 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
755 MPLL_CON0, NULL), 725 MPLL_CON0, NULL),
756 [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 726 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
757 BPLL_CON0, NULL), 727 BPLL_CON0, NULL),
758 [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK, 728 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
759 KPLL_CON0, NULL), 729 KPLL_CON0, NULL),
760}; 730};
761 731
@@ -777,7 +747,7 @@ static void __init exynos5420_clk_init(struct device_node *np)
777 panic("%s: unable to determine soc\n", __func__); 747 panic("%s: unable to determine soc\n", __func__);
778 } 748 }
779 749
780 samsung_clk_init(np, reg_base, nr_clks, 750 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
781 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs), 751 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
782 NULL, 0); 752 NULL, 0);
783 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 753 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index f8658945bfd2..cbc15b56891d 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -9,6 +9,7 @@
9 * Common Clock Framework support for Exynos5440 SoC. 9 * Common Clock Framework support for Exynos5440 SoC.
10*/ 10*/
11 11
12#include <dt-bindings/clock/exynos5440.h>
12#include <linux/clk.h> 13#include <linux/clk.h>
13#include <linux/clkdev.h> 14#include <linux/clkdev.h>
14#include <linux/clk-provider.h> 15#include <linux/clk-provider.h>
@@ -22,79 +23,65 @@
22#define CPU_CLK_STATUS 0xfc 23#define CPU_CLK_STATUS 0xfc
23#define MISC_DOUT1 0x558 24#define MISC_DOUT1 0x558
24 25
25/*
26 * Let each supported clock get a unique id. This id is used to lookup the clock
27 * for device tree based platforms.
28 */
29enum exynos5440_clks {
30 none, xtal, arm_clk,
31
32 spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
33 usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
34 b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
35
36 nr_clks,
37};
38
39/* parent clock name list */ 26/* parent clock name list */
40PNAME(mout_armclk_p) = { "cplla", "cpllb" }; 27PNAME(mout_armclk_p) = { "cplla", "cpllb" };
41PNAME(mout_spi_p) = { "div125", "div200" }; 28PNAME(mout_spi_p) = { "div125", "div200" };
42 29
43/* fixed rate clocks generated outside the soc */ 30/* fixed rate clocks generated outside the soc */
44static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { 31static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
45 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0), 32 FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0),
46}; 33};
47 34
48/* fixed rate clocks */ 35/* fixed rate clocks */
49static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { 36static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
50 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000), 37 FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000),
51 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), 38 FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
52 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), 39 FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
53 FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), 40 FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
54 FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), 41 FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
55}; 42};
56 43
57/* fixed factor clocks */ 44/* fixed factor clocks */
58static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { 45static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
59 FFACTOR(none, "div250", "ppll", 1, 4, 0), 46 FFACTOR(0, "div250", "ppll", 1, 4, 0),
60 FFACTOR(none, "div200", "ppll", 1, 5, 0), 47 FFACTOR(0, "div200", "ppll", 1, 5, 0),
61 FFACTOR(none, "div125", "div250", 1, 2, 0), 48 FFACTOR(0, "div125", "div250", 1, 2, 0),
62}; 49};
63 50
64/* mux clocks */ 51/* mux clocks */
65static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { 52static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
66 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), 53 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
67 MUX_A(arm_clk, "arm_clk", mout_armclk_p, 54 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
68 CPU_CLK_STATUS, 0, 1, "armclk"), 55 CPU_CLK_STATUS, 0, 1, "armclk"),
69}; 56};
70 57
71/* divider clocks */ 58/* divider clocks */
72static struct samsung_div_clock exynos5440_div_clks[] __initdata = { 59static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
73 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), 60 DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
74}; 61};
75 62
76/* gate clocks */ 63/* gate clocks */
77static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { 64static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
78 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), 65 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
79 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), 66 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
80 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), 67 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
81 GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), 68 GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
82 GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), 69 GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
83 GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), 70 GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
84 GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), 71 GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
85 GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), 72 GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
86 GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), 73 GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
87 GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), 74 GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
88 GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), 75 GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
89 GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), 76 GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
90 GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), 77 GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
91 GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), 78 GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
92 GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), 79 GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
93 GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), 80 GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
94 GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), 81 GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
95 GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), 82 GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
96 GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), 83 GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
97 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
98}; 85};
99 86
100static struct of_device_id ext_clk_match[] __initdata = { 87static struct of_device_id ext_clk_match[] __initdata = {
@@ -114,7 +101,7 @@ static void __init exynos5440_clk_init(struct device_node *np)
114 return; 101 return;
115 } 102 }
116 103
117 samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0); 104 samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0);
118 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, 105 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
119 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); 106 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
120 107
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 23:58:42 -0400