diff options
author | Naveen Krishna Ch <naveenkrishna.ch@gmail.com> | 2014-09-22 00:47:04 -0400 |
---|---|---|
committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2014-10-31 05:45:47 -0400 |
commit | 532abc3a4a4502e13315d246c545d7567c80b03e (patch) | |
tree | 325466600155fbce30bf9b3b70a09b8e61ee1d1e /drivers/clk/samsung | |
parent | 0e5af27008f947fe983004d502c3b2c1ddde1029 (diff) |
clk: samsung: add initial clock support for Exynos7 SoC
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r-- | drivers/clk/samsung/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/samsung/clk-exynos7.c | 425 |
2 files changed, 426 insertions, 0 deletions
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index d8535e6df1db..006c6f294310 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile | |||
@@ -13,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o | |||
13 | obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o | 13 | obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o |
14 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o | 14 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o |
15 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o | 15 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o |
16 | obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o | ||
16 | obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o | 17 | obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o |
17 | obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o | 18 | obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o |
18 | obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o | 19 | obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o |
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c new file mode 100644 index 000000000000..54206d4d408a --- /dev/null +++ b/drivers/clk/samsung/clk-exynos7.c | |||
@@ -0,0 +1,425 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | ||
3 | * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #include <linux/clk.h> | ||
12 | #include <linux/clkdev.h> | ||
13 | #include <linux/clk-provider.h> | ||
14 | #include <linux/of.h> | ||
15 | |||
16 | #include "clk.h" | ||
17 | #include <dt-bindings/clock/exynos7-clk.h> | ||
18 | |||
19 | /* Register Offset definitions for CMU_TOPC (0x10570000) */ | ||
20 | #define CC_PLL_LOCK 0x0000 | ||
21 | #define BUS0_PLL_LOCK 0x0004 | ||
22 | #define BUS1_DPLL_LOCK 0x0008 | ||
23 | #define MFC_PLL_LOCK 0x000C | ||
24 | #define AUD_PLL_LOCK 0x0010 | ||
25 | #define CC_PLL_CON0 0x0100 | ||
26 | #define BUS0_PLL_CON0 0x0110 | ||
27 | #define BUS1_DPLL_CON0 0x0120 | ||
28 | #define MFC_PLL_CON0 0x0130 | ||
29 | #define AUD_PLL_CON0 0x0140 | ||
30 | #define MUX_SEL_TOPC0 0x0200 | ||
31 | #define MUX_SEL_TOPC1 0x0204 | ||
32 | #define MUX_SEL_TOPC3 0x020C | ||
33 | #define DIV_TOPC1 0x0604 | ||
34 | #define DIV_TOPC3 0x060C | ||
35 | |||
36 | static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { | ||
37 | FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), | ||
38 | FFACTOR(0, "ffac_topc_bus0_pll_div4", | ||
39 | "ffac_topc_bus0_pll_div2", 1, 2, 0), | ||
40 | FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), | ||
41 | FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), | ||
42 | FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), | ||
43 | }; | ||
44 | |||
45 | /* List of parent clocks for Muxes in CMU_TOPC */ | ||
46 | PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; | ||
47 | PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; | ||
48 | PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; | ||
49 | PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; | ||
50 | |||
51 | PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", | ||
52 | "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", | ||
53 | "mout_sclk_mfc_pll_cmuc" }; | ||
54 | |||
55 | PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", | ||
56 | "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; | ||
57 | PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", | ||
58 | "ffac_topc_bus1_pll_div2"}; | ||
59 | PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", | ||
60 | "ffac_topc_cc_pll_div2"}; | ||
61 | PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", | ||
62 | "ffac_topc_mfc_pll_div2"}; | ||
63 | |||
64 | |||
65 | PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", | ||
66 | "ffac_topc_bus0_pll_div2"}; | ||
67 | |||
68 | static unsigned long topc_clk_regs[] __initdata = { | ||
69 | CC_PLL_LOCK, | ||
70 | BUS0_PLL_LOCK, | ||
71 | BUS1_DPLL_LOCK, | ||
72 | MFC_PLL_LOCK, | ||
73 | AUD_PLL_LOCK, | ||
74 | CC_PLL_CON0, | ||
75 | BUS0_PLL_CON0, | ||
76 | BUS1_DPLL_CON0, | ||
77 | MFC_PLL_CON0, | ||
78 | AUD_PLL_CON0, | ||
79 | MUX_SEL_TOPC0, | ||
80 | MUX_SEL_TOPC1, | ||
81 | MUX_SEL_TOPC3, | ||
82 | DIV_TOPC1, | ||
83 | DIV_TOPC3, | ||
84 | }; | ||
85 | |||
86 | static struct samsung_mux_clock topc_mux_clks[] __initdata = { | ||
87 | MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), | ||
88 | MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), | ||
89 | MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), | ||
90 | MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), | ||
91 | |||
92 | MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, | ||
93 | MUX_SEL_TOPC0, 16, 2), | ||
94 | MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, | ||
95 | MUX_SEL_TOPC0, 20, 1), | ||
96 | MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, | ||
97 | MUX_SEL_TOPC0, 24, 1), | ||
98 | MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, | ||
99 | MUX_SEL_TOPC0, 28, 1), | ||
100 | |||
101 | MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, | ||
102 | MUX_SEL_TOPC1, 16, 1), | ||
103 | |||
104 | MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), | ||
105 | }; | ||
106 | |||
107 | static struct samsung_div_clock topc_div_clks[] __initdata = { | ||
108 | DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", | ||
109 | DIV_TOPC1, 24, 4), | ||
110 | |||
111 | DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", | ||
112 | DIV_TOPC3, 0, 3), | ||
113 | DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", | ||
114 | DIV_TOPC3, 8, 3), | ||
115 | DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", | ||
116 | DIV_TOPC3, 12, 3), | ||
117 | DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", | ||
118 | DIV_TOPC3, 16, 3), | ||
119 | }; | ||
120 | |||
121 | static struct samsung_pll_clock topc_pll_clks[] __initdata = { | ||
122 | PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, | ||
123 | BUS0_PLL_CON0, NULL), | ||
124 | PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, | ||
125 | CC_PLL_CON0, NULL), | ||
126 | PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, | ||
127 | BUS1_DPLL_CON0, NULL), | ||
128 | PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, | ||
129 | MFC_PLL_CON0, NULL), | ||
130 | PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, | ||
131 | AUD_PLL_CON0, NULL), | ||
132 | }; | ||
133 | |||
134 | static struct samsung_cmu_info topc_cmu_info __initdata = { | ||
135 | .pll_clks = topc_pll_clks, | ||
136 | .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), | ||
137 | .mux_clks = topc_mux_clks, | ||
138 | .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), | ||
139 | .div_clks = topc_div_clks, | ||
140 | .nr_div_clks = ARRAY_SIZE(topc_div_clks), | ||
141 | .fixed_factor_clks = topc_fixed_factor_clks, | ||
142 | .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), | ||
143 | .nr_clk_ids = TOPC_NR_CLK, | ||
144 | .clk_regs = topc_clk_regs, | ||
145 | .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), | ||
146 | }; | ||
147 | |||
148 | static void __init exynos7_clk_topc_init(struct device_node *np) | ||
149 | { | ||
150 | samsung_cmu_register_one(np, &topc_cmu_info); | ||
151 | } | ||
152 | |||
153 | CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", | ||
154 | exynos7_clk_topc_init); | ||
155 | |||
156 | /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ | ||
157 | #define MUX_SEL_TOP00 0x0200 | ||
158 | #define MUX_SEL_TOP01 0x0204 | ||
159 | #define MUX_SEL_TOP03 0x020C | ||
160 | #define MUX_SEL_TOP0_PERIC3 0x023C | ||
161 | #define DIV_TOP03 0x060C | ||
162 | #define DIV_TOP0_PERIC3 0x063C | ||
163 | #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C | ||
164 | |||
165 | /* List of parent clocks for Muxes in CMU_TOP0 */ | ||
166 | PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; | ||
167 | PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; | ||
168 | PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; | ||
169 | PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; | ||
170 | |||
171 | PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", | ||
172 | "ffac_top0_bus0_pll_div2"}; | ||
173 | PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", | ||
174 | "ffac_top0_bus1_pll_div2"}; | ||
175 | PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", | ||
176 | "ffac_top0_cc_pll_div2"}; | ||
177 | PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", | ||
178 | "ffac_top0_mfc_pll_div2"}; | ||
179 | |||
180 | PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", | ||
181 | "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", | ||
182 | "mout_top0_half_mfc_pll"}; | ||
183 | |||
184 | static unsigned long top0_clk_regs[] __initdata = { | ||
185 | MUX_SEL_TOP00, | ||
186 | MUX_SEL_TOP01, | ||
187 | MUX_SEL_TOP03, | ||
188 | MUX_SEL_TOP0_PERIC3, | ||
189 | DIV_TOP03, | ||
190 | DIV_TOP0_PERIC3, | ||
191 | ENABLE_SCLK_TOP0_PERIC3, | ||
192 | }; | ||
193 | |||
194 | static struct samsung_mux_clock top0_mux_clks[] __initdata = { | ||
195 | MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), | ||
196 | MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), | ||
197 | MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), | ||
198 | MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), | ||
199 | |||
200 | MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, | ||
201 | MUX_SEL_TOP01, 4, 1), | ||
202 | MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, | ||
203 | MUX_SEL_TOP01, 8, 1), | ||
204 | MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, | ||
205 | MUX_SEL_TOP01, 12, 1), | ||
206 | MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, | ||
207 | MUX_SEL_TOP01, 16, 1), | ||
208 | |||
209 | MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), | ||
210 | MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), | ||
211 | |||
212 | MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), | ||
213 | MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), | ||
214 | MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), | ||
215 | MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), | ||
216 | }; | ||
217 | |||
218 | static struct samsung_div_clock top0_div_clks[] __initdata = { | ||
219 | DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", | ||
220 | DIV_TOP03, 12, 6), | ||
221 | DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", | ||
222 | DIV_TOP03, 20, 6), | ||
223 | |||
224 | DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), | ||
225 | DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), | ||
226 | DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), | ||
227 | DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), | ||
228 | }; | ||
229 | |||
230 | static struct samsung_gate_clock top0_gate_clks[] __initdata = { | ||
231 | GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", | ||
232 | ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), | ||
233 | GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", | ||
234 | ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), | ||
235 | GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", | ||
236 | ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), | ||
237 | GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", | ||
238 | ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), | ||
239 | }; | ||
240 | |||
241 | static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { | ||
242 | FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), | ||
243 | FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), | ||
244 | FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), | ||
245 | FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), | ||
246 | }; | ||
247 | |||
248 | static struct samsung_cmu_info top0_cmu_info __initdata = { | ||
249 | .mux_clks = top0_mux_clks, | ||
250 | .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), | ||
251 | .div_clks = top0_div_clks, | ||
252 | .nr_div_clks = ARRAY_SIZE(top0_div_clks), | ||
253 | .gate_clks = top0_gate_clks, | ||
254 | .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), | ||
255 | .fixed_factor_clks = top0_fixed_factor_clks, | ||
256 | .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), | ||
257 | .nr_clk_ids = TOP0_NR_CLK, | ||
258 | .clk_regs = top0_clk_regs, | ||
259 | .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), | ||
260 | }; | ||
261 | |||
262 | static void __init exynos7_clk_top0_init(struct device_node *np) | ||
263 | { | ||
264 | samsung_cmu_register_one(np, &top0_cmu_info); | ||
265 | } | ||
266 | |||
267 | CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", | ||
268 | exynos7_clk_top0_init); | ||
269 | |||
270 | /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ | ||
271 | #define MUX_SEL_PERIC0 0x0200 | ||
272 | #define ENABLE_PCLK_PERIC0 0x0900 | ||
273 | #define ENABLE_SCLK_PERIC0 0x0A00 | ||
274 | |||
275 | /* List of parent clocks for Muxes in CMU_PERIC0 */ | ||
276 | PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; | ||
277 | PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; | ||
278 | |||
279 | static unsigned long peric0_clk_regs[] __initdata = { | ||
280 | MUX_SEL_PERIC0, | ||
281 | ENABLE_PCLK_PERIC0, | ||
282 | ENABLE_SCLK_PERIC0, | ||
283 | }; | ||
284 | |||
285 | static struct samsung_mux_clock peric0_mux_clks[] __initdata = { | ||
286 | MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, | ||
287 | MUX_SEL_PERIC0, 0, 1), | ||
288 | MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, | ||
289 | MUX_SEL_PERIC0, 16, 1), | ||
290 | }; | ||
291 | |||
292 | static struct samsung_gate_clock peric0_gate_clks[] __initdata = { | ||
293 | GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", | ||
294 | ENABLE_PCLK_PERIC0, 16, 0, 0), | ||
295 | |||
296 | GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", | ||
297 | ENABLE_SCLK_PERIC0, 16, 0, 0), | ||
298 | }; | ||
299 | |||
300 | static struct samsung_cmu_info peric0_cmu_info __initdata = { | ||
301 | .mux_clks = peric0_mux_clks, | ||
302 | .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), | ||
303 | .gate_clks = peric0_gate_clks, | ||
304 | .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), | ||
305 | .nr_clk_ids = PERIC0_NR_CLK, | ||
306 | .clk_regs = peric0_clk_regs, | ||
307 | .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), | ||
308 | }; | ||
309 | |||
310 | static void __init exynos7_clk_peric0_init(struct device_node *np) | ||
311 | { | ||
312 | samsung_cmu_register_one(np, &peric0_cmu_info); | ||
313 | } | ||
314 | |||
315 | /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ | ||
316 | #define MUX_SEL_PERIC10 0x0200 | ||
317 | #define MUX_SEL_PERIC11 0x0204 | ||
318 | #define ENABLE_PCLK_PERIC1 0x0900 | ||
319 | #define ENABLE_SCLK_PERIC10 0x0A00 | ||
320 | |||
321 | CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", | ||
322 | exynos7_clk_peric0_init); | ||
323 | |||
324 | /* List of parent clocks for Muxes in CMU_PERIC1 */ | ||
325 | PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; | ||
326 | PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; | ||
327 | PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; | ||
328 | PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; | ||
329 | |||
330 | static unsigned long peric1_clk_regs[] __initdata = { | ||
331 | MUX_SEL_PERIC10, | ||
332 | MUX_SEL_PERIC11, | ||
333 | ENABLE_PCLK_PERIC1, | ||
334 | ENABLE_SCLK_PERIC10, | ||
335 | }; | ||
336 | |||
337 | static struct samsung_mux_clock peric1_mux_clks[] __initdata = { | ||
338 | MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, | ||
339 | MUX_SEL_PERIC10, 0, 1), | ||
340 | |||
341 | MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, | ||
342 | MUX_SEL_PERIC11, 20, 1), | ||
343 | MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, | ||
344 | MUX_SEL_PERIC11, 24, 1), | ||
345 | MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, | ||
346 | MUX_SEL_PERIC11, 28, 1), | ||
347 | }; | ||
348 | |||
349 | static struct samsung_gate_clock peric1_gate_clks[] __initdata = { | ||
350 | GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", | ||
351 | ENABLE_PCLK_PERIC1, 9, 0, 0), | ||
352 | GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", | ||
353 | ENABLE_PCLK_PERIC1, 10, 0, 0), | ||
354 | GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", | ||
355 | ENABLE_PCLK_PERIC1, 11, 0, 0), | ||
356 | |||
357 | GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", | ||
358 | ENABLE_SCLK_PERIC10, 9, 0, 0), | ||
359 | GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", | ||
360 | ENABLE_SCLK_PERIC10, 10, 0, 0), | ||
361 | GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", | ||
362 | ENABLE_SCLK_PERIC10, 11, 0, 0), | ||
363 | }; | ||
364 | |||
365 | static struct samsung_cmu_info peric1_cmu_info __initdata = { | ||
366 | .mux_clks = peric1_mux_clks, | ||
367 | .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), | ||
368 | .gate_clks = peric1_gate_clks, | ||
369 | .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), | ||
370 | .nr_clk_ids = PERIC1_NR_CLK, | ||
371 | .clk_regs = peric1_clk_regs, | ||
372 | .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), | ||
373 | }; | ||
374 | |||
375 | static void __init exynos7_clk_peric1_init(struct device_node *np) | ||
376 | { | ||
377 | samsung_cmu_register_one(np, &peric1_cmu_info); | ||
378 | } | ||
379 | |||
380 | CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", | ||
381 | exynos7_clk_peric1_init); | ||
382 | |||
383 | /* Register Offset definitions for CMU_PERIS (0x10040000) */ | ||
384 | #define MUX_SEL_PERIS 0x0200 | ||
385 | #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 | ||
386 | #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 | ||
387 | |||
388 | /* List of parent clocks for Muxes in CMU_PERIS */ | ||
389 | PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; | ||
390 | |||
391 | static unsigned long peris_clk_regs[] __initdata = { | ||
392 | MUX_SEL_PERIS, | ||
393 | ENABLE_PCLK_PERIS_SECURE_CHIPID, | ||
394 | ENABLE_SCLK_PERIS_SECURE_CHIPID, | ||
395 | }; | ||
396 | |||
397 | static struct samsung_mux_clock peris_mux_clks[] __initdata = { | ||
398 | MUX(0, "mout_aclk_peris_66_user", | ||
399 | mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), | ||
400 | }; | ||
401 | |||
402 | static struct samsung_gate_clock peris_gate_clks[] __initdata = { | ||
403 | GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", | ||
404 | ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), | ||
405 | GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", | ||
406 | ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), | ||
407 | }; | ||
408 | |||
409 | static struct samsung_cmu_info peris_cmu_info __initdata = { | ||
410 | .mux_clks = peris_mux_clks, | ||
411 | .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), | ||
412 | .gate_clks = peris_gate_clks, | ||
413 | .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), | ||
414 | .nr_clk_ids = PERIS_NR_CLK, | ||
415 | .clk_regs = peris_clk_regs, | ||
416 | .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), | ||
417 | }; | ||
418 | |||
419 | static void __init exynos7_clk_peris_init(struct device_node *np) | ||
420 | { | ||
421 | samsung_cmu_register_one(np, &peris_cmu_info); | ||
422 | } | ||
423 | |||
424 | CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", | ||
425 | exynos7_clk_peris_init); | ||