diff options
author | Sachin Kamat <sachin.kamat@linaro.org> | 2013-08-07 00:48:37 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2013-08-08 18:57:34 -0400 |
commit | 3c701c51ef918ce7bbe6ba983ea2e0e0cead5810 (patch) | |
tree | af0cd5f4ecc04a8cb46a93ba1bf65470b7cae0b2 /drivers/clk/samsung | |
parent | 7cc560dea4152139e16bea6e56ffa9e1bc461082 (diff) |
clk: exynos4: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index fec319d33c24..742b4c58ced9 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c | |||
@@ -194,7 +194,7 @@ enum exynos4_clks { | |||
194 | * list of controller registers to be saved and restored during a | 194 | * list of controller registers to be saved and restored during a |
195 | * suspend/resume cycle. | 195 | * suspend/resume cycle. |
196 | */ | 196 | */ |
197 | static __initdata unsigned long exynos4210_clk_save[] = { | 197 | static unsigned long exynos4210_clk_save[] __initdata = { |
198 | E4210_SRC_IMAGE, | 198 | E4210_SRC_IMAGE, |
199 | E4210_SRC_LCD1, | 199 | E4210_SRC_LCD1, |
200 | E4210_SRC_MASK_LCD1, | 200 | E4210_SRC_MASK_LCD1, |
@@ -205,7 +205,7 @@ static __initdata unsigned long exynos4210_clk_save[] = { | |||
205 | E4210_MPLL_CON0, | 205 | E4210_MPLL_CON0, |
206 | }; | 206 | }; |
207 | 207 | ||
208 | static __initdata unsigned long exynos4x12_clk_save[] = { | 208 | static unsigned long exynos4x12_clk_save[] __initdata = { |
209 | E4X12_GATE_IP_IMAGE, | 209 | E4X12_GATE_IP_IMAGE, |
210 | E4X12_GATE_IP_PERIR, | 210 | E4X12_GATE_IP_PERIR, |
211 | E4X12_SRC_CAM1, | 211 | E4X12_SRC_CAM1, |
@@ -214,7 +214,7 @@ static __initdata unsigned long exynos4x12_clk_save[] = { | |||
214 | E4X12_MPLL_CON0, | 214 | E4X12_MPLL_CON0, |
215 | }; | 215 | }; |
216 | 216 | ||
217 | static __initdata unsigned long exynos4_clk_regs[] = { | 217 | static unsigned long exynos4_clk_regs[] __initdata = { |
218 | SRC_LEFTBUS, | 218 | SRC_LEFTBUS, |
219 | DIV_LEFTBUS, | 219 | DIV_LEFTBUS, |
220 | GATE_IP_LEFTBUS, | 220 | GATE_IP_LEFTBUS, |
@@ -978,13 +978,13 @@ static void __init exynos4_clk_register_finpll(unsigned long xom) | |||
978 | 978 | ||
979 | } | 979 | } |
980 | 980 | ||
981 | static __initdata struct of_device_id ext_clk_match[] = { | 981 | static struct of_device_id ext_clk_match[] __initdata = { |
982 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, | 982 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, |
983 | { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, | 983 | { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, |
984 | {}, | 984 | {}, |
985 | }; | 985 | }; |
986 | 986 | ||
987 | static struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = { | 987 | static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = { |
988 | [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, | 988 | [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, |
989 | APLL_CON0, "fout_apll", NULL), | 989 | APLL_CON0, "fout_apll", NULL), |
990 | [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", | 990 | [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", |