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authorAndrzej Hajda <a.hajda@samsung.com>2014-01-07 09:47:31 -0500
committerTomasz Figa <t.figa@samsung.com>2014-01-08 12:02:38 -0500
commit2d73823750542c0dcbc9e7e00cd36d70ade3a65f (patch)
treeca363f43f056cc66b1c4f4f575b878c34cee20ef /drivers/clk/samsung
parent26460bc5588832fd660081cb36103efdaa04291d (diff)
clk: exynos4: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c857
1 files changed, 402 insertions, 455 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 1a7c1b929c69..2f7e440aebf8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for all Exynos4 SoCs. 10 * Common Clock Framework support for all Exynos4 SoCs.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos4.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -130,68 +131,6 @@ enum exynos4_plls {
130}; 131};
131 132
132/* 133/*
133 * Let each supported clock get a unique id. This id is used to lookup the clock
134 * for device tree based platforms. The clocks are categorized into three
135 * sections: core, sclk gate and bus interface gate clocks.
136 *
137 * When adding a new clock to this list, it is advised to choose a clock
138 * category and add it to the end of that category. That is because the the
139 * device tree source file is referring to these ids and any change in the
140 * sequence number of existing clocks will require corresponding change in the
141 * device tree files. This limitation would go away when pre-processor support
142 * for dtc would be available.
143 */
144enum exynos4_clks {
145 none,
146
147 /* core clocks */
148 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
149 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
150 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
151 mout_apll, /* 20 */
152
153 /* gate for special clocks (sclk) */
154 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
155 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
156 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
157 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
158 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
159 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
160 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
161 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
162 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
163
164 /* gate clocks */
165 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
166 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
167 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
168 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
169 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
170 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
171 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
172 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
173 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
174 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
175 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
176 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
177 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
178 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
179 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
180 spi1_isp_sclk, uart_isp_sclk, tmu_apbif,
181
182 /* mux clocks */
183 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
184 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
185 aclk400_mcuisp,
186
187 /* div clocks */
188 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
189 div_aclk400_mcuisp,
190
191 nr_clks,
192};
193
194/*
195 * list of controller registers to be saved and restored during a 134 * list of controller registers to be saved and restored during a
196 * suspend/resume cycle. 135 * suspend/resume cycle.
197 */ 136 */
@@ -347,255 +286,255 @@ PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
347 286
348/* fixed rate clocks generated outside the soc */ 287/* fixed rate clocks generated outside the soc */
349static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 288static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
350 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), 289 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0),
351 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), 290 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0),
352}; 291};
353 292
354/* fixed rate clocks generated inside the soc */ 293/* fixed rate clocks generated inside the soc */
355static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 294static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
356 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 295 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
357 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 296 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
358 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 297 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
359}; 298};
360 299
361static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 300static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
362 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 301 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
363}; 302};
364 303
365/* list of mux clocks supported in all exynos4 soc's */ 304/* list of mux clocks supported in all exynos4 soc's */
366static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 305static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
367 MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 306 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
368 CLK_SET_RATE_PARENT, 0, "mout_apll"), 307 CLK_SET_RATE_PARENT, 0, "mout_apll"),
369 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 308 MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
370 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 309 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
371 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 310 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
372 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 311 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
373 CLK_SET_RATE_PARENT, 0), 312 CLK_SET_RATE_PARENT, 0),
374 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 313 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
375 CLK_SET_RATE_PARENT, 0), 314 CLK_SET_RATE_PARENT, 0),
376 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 315 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
377 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 316 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
378 MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 317 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
379 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 318 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
380}; 319};
381 320
382/* list of mux clocks supported in exynos4210 soc */ 321/* list of mux clocks supported in exynos4210 soc */
383static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 322static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
384 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 323 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
385}; 324};
386 325
387static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 326static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
388 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 327 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
389 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 328 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
390 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 329 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
391 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 330 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
392 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 331 MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
393 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 332 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
394 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 333 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
395 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 334 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
396 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 335 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
397 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 336 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
398 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 337 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
399 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 338 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
400 MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 339 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
401 MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 340 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
402 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 341 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
403 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 342 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
404 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 343 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
405 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 344 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
406 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 345 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
407 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 346 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
408 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 347 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
409 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 348 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
410 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 349 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
411 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 350 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
412 CLK_SET_RATE_PARENT, 0), 351 CLK_SET_RATE_PARENT, 0),
413 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 352 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
414 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 353 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
415 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 354 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
416 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 355 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
417 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 356 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
418 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 357 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
419 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 358 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
420 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 359 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
421 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 360 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
422 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 361 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
423 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 362 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
424 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 363 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
425 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 364 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
426 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 365 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
427 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 366 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
428 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 367 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
429 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 368 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
430 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 369 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
431 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 370 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
432}; 371};
433 372
434/* list of mux clocks supported in exynos4x12 soc */ 373/* list of mux clocks supported in exynos4x12 soc */
435static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 374static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
436 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, 375 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
437 SRC_CPU, 24, 1), 376 SRC_CPU, 24, 1),
438 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 377 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
439 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 378 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
440 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, 379 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
441 SRC_TOP1, 12, 1), 380 SRC_TOP1, 12, 1),
442 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 381 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
443 SRC_TOP1, 16, 1), 382 SRC_TOP1, 16, 1),
444 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 383 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
445 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, 384 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
446 SRC_TOP1, 24, 1), 385 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
447 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 386 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
448 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 387 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
449 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 388 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
450 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 389 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
451 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 390 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
452 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 391 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
453 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 392 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
454 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 393 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
455 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 394 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
456 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 395 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
457 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 396 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
458 MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 397 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
459 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 398 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
460 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 399 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
461 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 400 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
462 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 401 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
463 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 402 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
464 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 403 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
465 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 404 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
466 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 405 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
467 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 406 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
468 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 407 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
469 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 408 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
470 CLK_SET_RATE_PARENT, 0), 409 CLK_SET_RATE_PARENT, 0),
471 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 410 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
472 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 411 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
473 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 412 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
474 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 413 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
475 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 414 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
476 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 415 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
477 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 416 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
478 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 417 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
479 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 418 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
480 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 419 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
481 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 420 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
482 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 421 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
483 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 422 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
484 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 423 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
485 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 424 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
486 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 425 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
487 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 426 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
488 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 427 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
489 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 428 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
490 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 429 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
491 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 430 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
492 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 431 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
493 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 432 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
494 MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 433 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
495 MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 434 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
496 MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 435 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
497}; 436};
498 437
499/* list of divider clocks supported in all exynos4 soc's */ 438/* list of divider clocks supported in all exynos4 soc's */
500static struct samsung_div_clock exynos4_div_clks[] __initdata = { 439static struct samsung_div_clock exynos4_div_clks[] __initdata = {
501 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), 440 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
502 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), 441 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
503 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 442 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
504 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 443 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
505 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 444 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
506 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 445 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
507 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 446 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
508 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 447 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
509 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 448 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
510 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 449 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
511 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 450 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
512 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, 451 DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
513 CLK_SET_RATE_PARENT, 0), 452 CLK_SET_RATE_PARENT, 0),
514 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 453 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
515 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 454 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
516 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 455 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
517 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 456 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
518 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 457 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
519 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 458 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
520 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 459 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
521 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 460 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
522 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 461 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
523 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 462 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
524 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 463 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
525 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 464 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
526 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 465 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
527 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 466 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
528 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 467 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
529 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 468 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 469 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 470 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 471 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
533 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), 472 DIV(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
534 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 473 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
535 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 474 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
536 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 475 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
537 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 476 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
538 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 477 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
539 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 478 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
540 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 479 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
541 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 480 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
542 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 481 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
543 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 482 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
544 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 483 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
545 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 484 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
546 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 485 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
547 DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3), 486 DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
548 DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 487 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
549 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 488 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
550 CLK_SET_RATE_PARENT, 0), 489 CLK_SET_RATE_PARENT, 0),
551 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 490 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
552 CLK_SET_RATE_PARENT, 0), 491 CLK_SET_RATE_PARENT, 0),
553 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 492 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
554 CLK_SET_RATE_PARENT, 0), 493 CLK_SET_RATE_PARENT, 0),
555 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 494 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
556 CLK_SET_RATE_PARENT, 0), 495 CLK_SET_RATE_PARENT, 0),
557 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 496 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
558 CLK_SET_RATE_PARENT, 0), 497 CLK_SET_RATE_PARENT, 0),
559}; 498};
560 499
561/* list of divider clocks supported in exynos4210 soc */ 500/* list of divider clocks supported in exynos4210 soc */
562static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 501static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
563 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 502 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
564 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 503 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
565 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 504 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
566 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 505 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
567 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 506 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
568 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 507 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
569 CLK_SET_RATE_PARENT, 0), 508 CLK_SET_RATE_PARENT, 0),
570}; 509};
571 510
572/* list of divider clocks supported in exynos4x12 soc */ 511/* list of divider clocks supported in exynos4x12 soc */
573static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 512static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
574 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 513 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
575 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 514 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
576 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 515 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
577 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 516 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
578 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 517 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
579 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 518 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
580 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 519 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
581 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 520 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
582 DIV_TOP, 24, 3), 521 DIV_TOP, 24, 3),
583 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 522 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
584 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 523 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
585 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 524 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
586 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 525 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
587 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 526 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
588 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 527 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
589 DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 528 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
590 CLK_GET_RATE_NOCACHE, 0), 529 CLK_GET_RATE_NOCACHE, 0),
591 DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 530 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
592 CLK_GET_RATE_NOCACHE, 0), 531 CLK_GET_RATE_NOCACHE, 0),
593 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 532 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
594 DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 533 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
595 4, 3, CLK_GET_RATE_NOCACHE, 0), 534 4, 3, CLK_GET_RATE_NOCACHE, 0),
596 DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 535 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
597 8, 3, CLK_GET_RATE_NOCACHE, 0), 536 8, 3, CLK_GET_RATE_NOCACHE, 0),
598 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 537 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
599}; 538};
600 539
601/* list of gate clocks supported in all exynos4 soc's */ 540/* list of gate clocks supported in all exynos4 soc's */
@@ -605,333 +544,341 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
605 * the device name and clock alias names specified below for some 544 * the device name and clock alias names specified below for some
606 * of the clocks can be removed. 545 * of the clocks can be removed.
607 */ 546 */
608 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 547 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
609 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), 548 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
610 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 549 0),
611 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 550 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
612 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 551 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
613 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 552 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
614 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 553 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
615 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 554 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
616 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), 555 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
617 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 556 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
618 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 557 0),
619 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 558 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
559 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
560 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
620 CLK_SET_RATE_PARENT, 0), 561 CLK_SET_RATE_PARENT, 0),
621 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 562 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
622 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 563 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
623 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 564 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
624 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 565 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
625 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 566 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
626 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 567 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
627 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 568 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
628 CLK_SET_RATE_PARENT, 0), 569 CLK_SET_RATE_PARENT, 0),
629 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 570 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
630 CLK_SET_RATE_PARENT, 0), 571 CLK_SET_RATE_PARENT, 0),
631 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", 572 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
632 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 573 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
633 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 574 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
634 CLK_SET_RATE_PARENT, 0), 575 CLK_SET_RATE_PARENT, 0),
635 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 576 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
636 CLK_SET_RATE_PARENT, 0), 577 CLK_SET_RATE_PARENT, 0),
637 GATE(vp, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 578 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
638 GATE(mixer, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 579 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
639 GATE(hdmi, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 580 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
640 GATE(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 581 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
641 GATE(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 582 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
642 GATE(usb_host, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 583 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
643 GATE(sclk_fimc0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 584 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
644 CLK_SET_RATE_PARENT, 0), 585 CLK_SET_RATE_PARENT, 0),
645 GATE(sclk_fimc1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 586 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
646 CLK_SET_RATE_PARENT, 0), 587 CLK_SET_RATE_PARENT, 0),
647 GATE(sclk_fimc2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 588 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
648 CLK_SET_RATE_PARENT, 0), 589 CLK_SET_RATE_PARENT, 0),
649 GATE(sclk_fimc3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 590 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
650 CLK_SET_RATE_PARENT, 0), 591 CLK_SET_RATE_PARENT, 0),
651 GATE(sclk_csis0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 592 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
652 CLK_SET_RATE_PARENT, 0), 593 CLK_SET_RATE_PARENT, 0),
653 GATE(sclk_csis1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 594 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
654 CLK_SET_RATE_PARENT, 0), 595 CLK_SET_RATE_PARENT, 0),
655 GATE(sclk_fimd0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 596 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
656 CLK_SET_RATE_PARENT, 0), 597 CLK_SET_RATE_PARENT, 0),
657 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 598 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
658 CLK_SET_RATE_PARENT, 0), 599 CLK_SET_RATE_PARENT, 0),
659 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 600 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
660 CLK_SET_RATE_PARENT, 0), 601 CLK_SET_RATE_PARENT, 0),
661 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 602 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
662 CLK_SET_RATE_PARENT, 0), 603 CLK_SET_RATE_PARENT, 0),
663 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 604 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
664 CLK_SET_RATE_PARENT, 0), 605 CLK_SET_RATE_PARENT, 0),
665 GATE(sclk_mmc4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 606 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
666 CLK_SET_RATE_PARENT, 0), 607 CLK_SET_RATE_PARENT, 0),
667 GATE(sclk_uart0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 608 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
668 CLK_SET_RATE_PARENT, 0), 609 CLK_SET_RATE_PARENT, 0),
669 GATE(sclk_uart1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 610 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
670 CLK_SET_RATE_PARENT, 0), 611 CLK_SET_RATE_PARENT, 0),
671 GATE(sclk_uart2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 612 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
672 CLK_SET_RATE_PARENT, 0), 613 CLK_SET_RATE_PARENT, 0),
673 GATE(sclk_uart3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 614 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
674 CLK_SET_RATE_PARENT, 0), 615 CLK_SET_RATE_PARENT, 0),
675 GATE(sclk_uart4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 616 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
676 CLK_SET_RATE_PARENT, 0), 617 CLK_SET_RATE_PARENT, 0),
677 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 618 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
678 CLK_SET_RATE_PARENT, 0), 619 CLK_SET_RATE_PARENT, 0),
679 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 620 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
680 CLK_SET_RATE_PARENT, 0), 621 CLK_SET_RATE_PARENT, 0),
681 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 622 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
682 CLK_SET_RATE_PARENT, 0), 623 CLK_SET_RATE_PARENT, 0),
683 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 624 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
684 CLK_SET_RATE_PARENT, 0), 625 CLK_SET_RATE_PARENT, 0),
685 GATE(fimc0, "fimc0", "aclk160", GATE_IP_CAM, 0, 626 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
686 0, 0), 627 0, 0),
687 GATE(fimc1, "fimc1", "aclk160", GATE_IP_CAM, 1, 628 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
688 0, 0), 629 0, 0),
689 GATE(fimc2, "fimc2", "aclk160", GATE_IP_CAM, 2, 630 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
690 0, 0), 631 0, 0),
691 GATE(fimc3, "fimc3", "aclk160", GATE_IP_CAM, 3, 632 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
692 0, 0), 633 0, 0),
693 GATE(csis0, "csis0", "aclk160", GATE_IP_CAM, 4, 634 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
694 0, 0), 635 0, 0),
695 GATE(csis1, "csis1", "aclk160", GATE_IP_CAM, 5, 636 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
696 0, 0), 637 0, 0),
697 GATE(smmu_fimc0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 638 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
698 0, 0), 639 0, 0),
699 GATE(smmu_fimc1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 640 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
700 0, 0), 641 0, 0),
701 GATE(smmu_fimc2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 642 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
702 0, 0), 643 0, 0),
703 GATE(smmu_fimc3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 644 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
704 0, 0), 645 0, 0),
705 GATE(smmu_jpeg, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 646 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
706 0, 0), 647 0, 0),
707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 648 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 649 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
709 GATE(smmu_tv, "smmu_tv", "aclk160", GATE_IP_TV, 4, 650 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
710 0, 0), 651 0, 0),
711 GATE(mfc, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 652 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
712 GATE(smmu_mfcl, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 653 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
713 0, 0), 654 0, 0),
714 GATE(smmu_mfcr, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 655 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
715 0, 0), 656 0, 0),
716 GATE(fimd0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 657 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
717 0, 0), 658 0, 0),
718 GATE(smmu_fimd0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 659 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
719 0, 0), 660 0, 0),
720 GATE(pdma0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 661 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
721 0, 0), 662 0, 0),
722 GATE(pdma1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 663 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
723 0, 0), 664 0, 0),
724 GATE(sdmmc0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 665 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
725 0, 0), 666 0, 0),
726 GATE(sdmmc1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 667 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
727 0, 0), 668 0, 0),
728 GATE(sdmmc2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 669 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
729 0, 0), 670 0, 0),
730 GATE(sdmmc3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 671 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
731 0, 0), 672 0, 0),
732 GATE(uart0, "uart0", "aclk100", GATE_IP_PERIL, 0, 673 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
733 0, 0), 674 0, 0),
734 GATE(uart1, "uart1", "aclk100", GATE_IP_PERIL, 1, 675 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
735 0, 0), 676 0, 0),
736 GATE(uart2, "uart2", "aclk100", GATE_IP_PERIL, 2, 677 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
737 0, 0), 678 0, 0),
738 GATE(uart3, "uart3", "aclk100", GATE_IP_PERIL, 3, 679 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
739 0, 0), 680 0, 0),
740 GATE(uart4, "uart4", "aclk100", GATE_IP_PERIL, 4, 681 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
741 0, 0), 682 0, 0),
742 GATE(i2c0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 683 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
743 0, 0), 684 0, 0),
744 GATE(i2c1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 685 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
745 0, 0), 686 0, 0),
746 GATE(i2c2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 687 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
747 0, 0), 688 0, 0),
748 GATE(i2c3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 689 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
749 0, 0), 690 0, 0),
750 GATE(i2c4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 691 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
751 0, 0), 692 0, 0),
752 GATE(i2c5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 693 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
753 0, 0), 694 0, 0),
754 GATE(i2c6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 695 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
755 0, 0), 696 0, 0),
756 GATE(i2c7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 697 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
757 0, 0), 698 0, 0),
758 GATE(i2c_hdmi, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 699 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
759 0, 0), 700 0, 0),
760 GATE(spi0, "spi0", "aclk100", GATE_IP_PERIL, 16, 701 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
761 0, 0), 702 0, 0),
762 GATE(spi1, "spi1", "aclk100", GATE_IP_PERIL, 17, 703 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
763 0, 0), 704 0, 0),
764 GATE(spi2, "spi2", "aclk100", GATE_IP_PERIL, 18, 705 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
765 0, 0), 706 0, 0),
766 GATE(i2s1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 707 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
767 0, 0), 708 0, 0),
768 GATE(i2s2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 709 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
769 0, 0), 710 0, 0),
770 GATE(pcm1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 711 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
771 0, 0), 712 0, 0),
772 GATE(pcm2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 713 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
773 0, 0), 714 0, 0),
774 GATE(spdif, "spdif", "aclk100", GATE_IP_PERIL, 26, 715 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
775 0, 0), 716 0, 0),
776 GATE(ac97, "ac97", "aclk100", GATE_IP_PERIL, 27, 717 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
777 0, 0), 718 0, 0),
778}; 719};
779 720
780/* list of gate clocks supported in exynos4210 soc */ 721/* list of gate clocks supported in exynos4210 soc */
781static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 722static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 723 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 724 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 725 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
785 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 726 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
786 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 727 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
787 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), 728 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
788 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 729 0),
789 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 730 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
790 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 731 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
791 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 732 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
792 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 733 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
793 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 734 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
794 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 735 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
795 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 736 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
737 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
796 CLK_IGNORE_UNUSED, 0), 738 CLK_IGNORE_UNUSED, 0),
797 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), 739 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
798 GATE(smmu_rotator, "smmu_rotator", "aclk200", 740 0),
741 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
799 E4210_GATE_IP_IMAGE, 4, 0, 0), 742 E4210_GATE_IP_IMAGE, 4, 0, 0),
800 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", 743 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
801 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 744 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
802 GATE(sclk_sata, "sclk_sata", "div_sata", 745 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
803 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 746 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
804 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 747 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
805 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 748 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
806 GATE(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 749 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
807 0, 0), 750 0, 0),
808 GATE(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 751 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
809 0, 0), 752 0, 0),
810 GATE(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 753 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
811 0, 0), 754 0, 0),
812 GATE(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 755 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
813 0, 0), 756 0, 0),
814 GATE(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 757 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
815 0, 0), 758 0, 0),
816 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 759 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
817 CLK_SET_RATE_PARENT, 0), 760 CLK_SET_RATE_PARENT, 0),
818 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), 761 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
762 0),
819}; 763};
820 764
821/* list of gate clocks supported in exynos4x12 soc */ 765/* list of gate clocks supported in exynos4x12 soc */
822static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 766static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
823 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 767 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
824 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 768 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
825 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 769 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
826 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 770 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
827 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), 771 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
828 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 772 0),
829 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 773 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
830 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 774 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
775 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
831 CLK_IGNORE_UNUSED, 0), 776 CLK_IGNORE_UNUSED, 0),
832 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), 777 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
833 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 778 0),
779 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
834 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 780 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
835 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 781 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
836 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 782 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
837 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", 783 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
838 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 784 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
839 GATE(smmu_rotator, "smmu_rotator", "aclk200", 785 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
840 E4X12_GATE_IP_IMAGE, 4, 0, 0), 786 E4X12_GATE_IP_IMAGE, 4, 0, 0),
841 GATE(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 787 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
842 0, 0), 788 0, 0),
843 GATE(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 789 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
844 0, 0), 790 0, 0),
845 GATE(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 791 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
846 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", 792 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp",
847 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 793 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
848 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", 794 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre",
849 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), 795 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
850 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", 796 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre",
851 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), 797 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
852 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", 798 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
853 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), 799 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
854 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", 800 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp",
855 E4X12_GATE_IP_ISP, 0, 0, 0), 801 E4X12_GATE_IP_ISP, 0, 0, 0),
856 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", 802 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp",
857 E4X12_GATE_IP_ISP, 1, 0, 0), 803 E4X12_GATE_IP_ISP, 1, 0, 0),
858 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", 804 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp",
859 E4X12_GATE_IP_ISP, 2, 0, 0), 805 E4X12_GATE_IP_ISP, 2, 0, 0),
860 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", 806 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp",
861 E4X12_GATE_IP_ISP, 3, 0, 0), 807 E4X12_GATE_IP_ISP, 3, 0, 0),
862 GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 808 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
863 GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 809 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
864 0, 0), 810 0, 0),
865 GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 811 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
866 0, 0), 812 0, 0),
867 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 813 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
868 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 814 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
869 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 815 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
870 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 816 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
871 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, 817 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
872 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 818 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
873 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 819 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
874 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 820 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
875 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 821 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
876 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 822 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
877 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 823 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
878 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 824 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
879 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 825 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
880 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 826 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
881 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 827 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
882 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 828 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
883 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 829 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
884 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 830 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
885 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 831 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
886 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 832 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
887 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 833 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
888 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 834 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
889 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 835 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
890 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 836 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
891 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 837 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
892 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 838 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
893 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 839 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
894 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 840 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
895 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 841 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
896 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 842 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
897 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 843 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
898 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 844 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
899 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 845 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
900 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 846 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
901 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 847 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
902 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 848 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
903 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 849 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
904 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 850 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
905 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 851 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
906 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 852 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
907 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 853 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
908 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 854 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
909 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 855 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
910 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 856 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
911 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 857 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
912 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 858 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
913 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 859 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
914 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 860 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
915 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 861 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
916 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 862 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
917 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 863 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
918 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 864 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
919 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 865 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
920 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), 866 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
867 0),
921}; 868};
922 869
923static struct samsung_clock_alias exynos4_aliases[] __initdata = { 870static struct samsung_clock_alias exynos4_aliases[] __initdata = {
924 ALIAS(mout_core, NULL, "moutcore"), 871 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
925 ALIAS(arm_clk, NULL, "armclk"), 872 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
926 ALIAS(sclk_apll, NULL, "mout_apll"), 873 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
927}; 874};
928 875
929static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 876static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
930 ALIAS(sclk_mpll, NULL, "mout_mpll"), 877 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
931}; 878};
932 879
933static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 880static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
934 ALIAS(mout_mpll_user_c, NULL, "mout_mpll"), 881 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
935}; 882};
936 883
937/* 884/*
@@ -977,7 +924,7 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
977 finpll_f = clk_get_rate(clk); 924 finpll_f = clk_get_rate(clk);
978 } 925 }
979 926
980 fclk.id = fin_pll; 927 fclk.id = CLK_FIN_PLL;
981 fclk.name = "fin_pll"; 928 fclk.name = "fin_pll";
982 fclk.parent_name = NULL; 929 fclk.parent_name = NULL;
983 fclk.flags = CLK_IS_ROOT; 930 fclk.flags = CLK_IS_ROOT;
@@ -1067,24 +1014,24 @@ static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
1067}; 1014};
1068 1015
1069static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1016static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1070 [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 1017 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1071 APLL_CON0, "fout_apll", NULL), 1018 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
1072 [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", 1019 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1073 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1020 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
1074 [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 1021 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1075 EPLL_CON0, "fout_epll", NULL), 1022 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
1076 [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc", 1023 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1077 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1024 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
1078}; 1025};
1079 1026
1080static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1027static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1081 [apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll", 1028 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1082 APLL_LOCK, APLL_CON0, NULL), 1029 APLL_LOCK, APLL_CON0, NULL),
1083 [mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", 1030 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1084 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1031 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1085 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", 1032 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1086 EPLL_LOCK, EPLL_CON0, NULL), 1033 EPLL_LOCK, EPLL_CON0, NULL),
1087 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", 1034 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1088 VPLL_LOCK, VPLL_CON0, NULL), 1035 VPLL_LOCK, VPLL_CON0, NULL),
1089}; 1036};
1090 1037
@@ -1098,11 +1045,11 @@ static void __init exynos4_clk_init(struct device_node *np,
1098 panic("%s: failed to map registers\n", __func__); 1045 panic("%s: failed to map registers\n", __func__);
1099 1046
1100 if (exynos4_soc == EXYNOS4210) 1047 if (exynos4_soc == EXYNOS4210)
1101 samsung_clk_init(np, reg_base, nr_clks, 1048 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
1102 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1049 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1103 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); 1050 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1104 else 1051 else
1105 samsung_clk_init(np, reg_base, nr_clks, 1052 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
1106 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1053 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1107 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); 1054 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1108 1055
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 23:58:19 -0400