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authorChanwoo Choi <cw00.choi@samsung.com>2015-02-02 09:24:01 -0500
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-02-04 12:58:11 -0500
commit06d2f9dfa663367e8cc1690d7e5ce4113e5dbcc1 (patch)
treec691b7076f3a94d18ddc7279e8a0416c2f9e4a90 /drivers/clk/samsung
parenta29308dad5dc4695a344ed9042cae8a1b8e35267 (diff)
clk: samsung: exynos5433: Add clocks for CMU_MIF domain
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c599
1 files changed, 599 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 24218dba8218..09ccf11bab64 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -740,6 +740,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
740#define MFC_PLL_CON0 0x0130 740#define MFC_PLL_CON0 0x0130
741#define MFC_PLL_CON1 0x0134 741#define MFC_PLL_CON1 0x0134
742#define MFC_PLL_FREQ_DET 0x013c 742#define MFC_PLL_FREQ_DET 0x013c
743#define MUX_SEL_MIF0 0x0200
744#define MUX_SEL_MIF1 0x0204
745#define MUX_SEL_MIF2 0x0208
746#define MUX_SEL_MIF3 0x020c
747#define MUX_SEL_MIF4 0x0210
748#define MUX_SEL_MIF5 0x0214
749#define MUX_SEL_MIF6 0x0218
750#define MUX_SEL_MIF7 0x021c
751#define MUX_ENABLE_MIF0 0x0300
752#define MUX_ENABLE_MIF1 0x0304
753#define MUX_ENABLE_MIF2 0x0308
754#define MUX_ENABLE_MIF3 0x030c
755#define MUX_ENABLE_MIF4 0x0310
756#define MUX_ENABLE_MIF5 0x0314
757#define MUX_ENABLE_MIF6 0x0318
758#define MUX_ENABLE_MIF7 0x031c
759#define MUX_STAT_MIF0 0x0400
760#define MUX_STAT_MIF1 0x0404
761#define MUX_STAT_MIF2 0x0408
762#define MUX_STAT_MIF3 0x040c
763#define MUX_STAT_MIF4 0x0410
764#define MUX_STAT_MIF5 0x0414
765#define MUX_STAT_MIF6 0x0418
766#define MUX_STAT_MIF7 0x041c
767#define DIV_MIF1 0x0604
768#define DIV_MIF2 0x0608
769#define DIV_MIF3 0x060c
770#define DIV_MIF4 0x0610
771#define DIV_MIF5 0x0614
772#define DIV_MIF_PLL_FREQ_DET 0x0618
773#define DIV_STAT_MIF1 0x0704
774#define DIV_STAT_MIF2 0x0708
775#define DIV_STAT_MIF3 0x070c
776#define DIV_STAT_MIF4 0x0710
777#define DIV_STAT_MIF5 0x0714
778#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
779#define ENABLE_ACLK_MIF0 0x0800
780#define ENABLE_ACLK_MIF1 0x0804
781#define ENABLE_ACLK_MIF2 0x0808
782#define ENABLE_ACLK_MIF3 0x080c
783#define ENABLE_PCLK_MIF 0x0900
784#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
785#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
786#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
787#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
788#define ENABLE_SCLK_MIF 0x0a00
789#define ENABLE_IP_MIF0 0x0b00
790#define ENABLE_IP_MIF1 0x0b04
791#define ENABLE_IP_MIF2 0x0b08
792#define ENABLE_IP_MIF3 0x0b0c
793#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
794#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
795#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
796#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
797#define CLKOUT_CMU_MIF 0x0c00
798#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
799#define DREX_FREQ_CTRL0 0x1000
800#define DREX_FREQ_CTRL1 0x1004
801#define PAUSE 0x1008
802#define DDRPHY_LOCK_CTRL 0x100c
743 803
744static unsigned long mif_clk_regs[] __initdata = { 804static unsigned long mif_clk_regs[] __initdata = {
745 MEM0_PLL_LOCK, 805 MEM0_PLL_LOCK,
@@ -758,6 +818,66 @@ static unsigned long mif_clk_regs[] __initdata = {
758 MFC_PLL_CON0, 818 MFC_PLL_CON0,
759 MFC_PLL_CON1, 819 MFC_PLL_CON1,
760 MFC_PLL_FREQ_DET, 820 MFC_PLL_FREQ_DET,
821 MUX_SEL_MIF0,
822 MUX_SEL_MIF1,
823 MUX_SEL_MIF2,
824 MUX_SEL_MIF3,
825 MUX_SEL_MIF4,
826 MUX_SEL_MIF5,
827 MUX_SEL_MIF6,
828 MUX_SEL_MIF7,
829 MUX_ENABLE_MIF0,
830 MUX_ENABLE_MIF1,
831 MUX_ENABLE_MIF2,
832 MUX_ENABLE_MIF3,
833 MUX_ENABLE_MIF4,
834 MUX_ENABLE_MIF5,
835 MUX_ENABLE_MIF6,
836 MUX_ENABLE_MIF7,
837 MUX_STAT_MIF0,
838 MUX_STAT_MIF1,
839 MUX_STAT_MIF2,
840 MUX_STAT_MIF3,
841 MUX_STAT_MIF4,
842 MUX_STAT_MIF5,
843 MUX_STAT_MIF6,
844 MUX_STAT_MIF7,
845 DIV_MIF1,
846 DIV_MIF2,
847 DIV_MIF3,
848 DIV_MIF4,
849 DIV_MIF5,
850 DIV_MIF_PLL_FREQ_DET,
851 DIV_STAT_MIF1,
852 DIV_STAT_MIF2,
853 DIV_STAT_MIF3,
854 DIV_STAT_MIF4,
855 DIV_STAT_MIF5,
856 DIV_STAT_MIF_PLL_FREQ_DET,
857 ENABLE_ACLK_MIF0,
858 ENABLE_ACLK_MIF1,
859 ENABLE_ACLK_MIF2,
860 ENABLE_ACLK_MIF3,
861 ENABLE_PCLK_MIF,
862 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
863 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
864 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
865 ENABLE_PCLK_MIF_SECURE_RTC,
866 ENABLE_SCLK_MIF,
867 ENABLE_IP_MIF0,
868 ENABLE_IP_MIF1,
869 ENABLE_IP_MIF2,
870 ENABLE_IP_MIF3,
871 ENABLE_IP_MIF_SECURE_DREX0_TZ,
872 ENABLE_IP_MIF_SECURE_DREX1_TZ,
873 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
874 ENABLE_IP_MIF_SECURE_RTC,
875 CLKOUT_CMU_MIF,
876 CLKOUT_CMU_MIF_DIV_STAT,
877 DREX_FREQ_CTRL0,
878 DREX_FREQ_CTRL1,
879 PAUSE,
880 DDRPHY_LOCK_CTRL,
761}; 881};
762 882
763static struct samsung_pll_clock mif_pll_clks[] __initdata = { 883static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -771,9 +891,488 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
771 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), 891 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
772}; 892};
773 893
894/* list of all parent clock list */
895PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
896PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
897PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
898PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
899PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
900PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
901PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
902PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
903
904PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
905PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
906PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
907PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
908
909PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
910PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
911
912PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
913 "mout_bus_pll_div2", };
914PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
915
916PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
917 "sclk_mphy_pll", };
918PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
919 "mout_mfc_pll_div2", };
920PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
921PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
922 "sclk_mphy_pll", };
923PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
924 "mout_mfc_pll_div2", };
925
926PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
927 "sclk_mphy_pll", };
928PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
929 "mout_mfc_pll_div2", };
930PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
931PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
932PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
933
934PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
935PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
936
937PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
938 "sclk_mphy_pll", };
939PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
940 "mout_mfc_pll_div2", };
941PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
942PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
943
944static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
945 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
946 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
947 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
948 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
949 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
950};
951
952static struct samsung_mux_clock mif_mux_clks[] __initdata = {
953 /* MUX_SEL_MIF0 */
954 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
955 MUX_SEL_MIF0, 28, 1),
956 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
957 MUX_SEL_MIF0, 24, 1),
958 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
959 MUX_SEL_MIF0, 20, 1),
960 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
961 MUX_SEL_MIF0, 16, 1),
962 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
963 12, 1),
964 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
965 8, 1),
966 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
967 4, 1),
968 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
969 0, 1),
970
971 /* MUX_SEL_MIF1 */
972 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
973 MUX_SEL_MIF1, 24, 1),
974 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
975 MUX_SEL_MIF1, 20, 1),
976 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
977 MUX_SEL_MIF1, 16, 1),
978 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
979 MUX_SEL_MIF1, 12, 1),
980 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
981 MUX_SEL_MIF1, 8, 1),
982 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
983 MUX_SEL_MIF1, 4, 1),
984
985 /* MUX_SEL_MIF2 */
986 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
987 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
988 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
989 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
990
991 /* MUX_SEL_MIF3 */
992 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
993 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
994 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
995 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
996
997 /* MUX_SEL_MIF4 */
998 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
999 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1000 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1001 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1002 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1003 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1004 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1005 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1006 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1007 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1008 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1009 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1010
1011 /* MUX_SEL_MIF5 */
1012 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1013 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1014 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1015 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1016 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1017 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1018 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1019 MUX_SEL_MIF5, 8, 1),
1020 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1021 MUX_SEL_MIF5, 4, 1),
1022 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1023 MUX_SEL_MIF5, 0, 1),
1024
1025 /* MUX_SEL_MIF6 */
1026 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1027 MUX_SEL_MIF6, 8, 1),
1028 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1029 MUX_SEL_MIF6, 4, 1),
1030 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1031 MUX_SEL_MIF6, 0, 1),
1032
1033 /* MUX_SEL_MIF7 */
1034 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1035 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1036 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1037 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1038 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1039 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1040 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1041 MUX_SEL_MIF7, 8, 1),
1042 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1043 MUX_SEL_MIF7, 4, 1),
1044 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1045 MUX_SEL_MIF7, 0, 1),
1046};
1047
1048static struct samsung_div_clock mif_div_clks[] __initdata = {
1049 /* DIV_MIF1 */
1050 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1051 DIV_MIF1, 16, 2),
1052 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1053 12, 2),
1054 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1055 8, 2),
1056 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1057 4, 4),
1058
1059 /* DIV_MIF2 */
1060 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1061 DIV_MIF2, 20, 3),
1062 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1063 DIV_MIF2, 16, 4),
1064 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1065 DIV_MIF2, 12, 4),
1066 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1067 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1068 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1069 DIV_MIF2, 4, 2),
1070 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1071 DIV_MIF2, 0, 3),
1072
1073 /* DIV_MIF3 */
1074 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1075 DIV_MIF3, 16, 4),
1076 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1077 DIV_MIF3, 4, 3),
1078 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1079 DIV_MIF3, 0, 3),
1080
1081 /* DIV_MIF4 */
1082 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1083 DIV_MIF4, 24, 4),
1084 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1085 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1086 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1087 DIV_MIF4, 16, 4),
1088 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1089 DIV_MIF4, 12, 4),
1090 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1091 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1092 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1093 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1094 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1095 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1096
1097 /* DIV_MIF5 */
1098 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1099 0, 3),
1100};
1101
1102static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1103 /* ENABLE_ACLK_MIF0 */
1104 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1105 19, CLK_IGNORE_UNUSED, 0),
1106 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1107 18, CLK_IGNORE_UNUSED, 0),
1108 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1109 17, CLK_IGNORE_UNUSED, 0),
1110 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1111 16, CLK_IGNORE_UNUSED, 0),
1112 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1113 15, CLK_IGNORE_UNUSED, 0),
1114 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1115 14, CLK_IGNORE_UNUSED, 0),
1116 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1117 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1118 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1119 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1120 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1121 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1122 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1123 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1124 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1125 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1126 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1127 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1128 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1129 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1130 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1131 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1132 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1133 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1134 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1135 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1136 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1137 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1138 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1139 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1140 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1141 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1142 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1143 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1144
1145 /* ENABLE_ACLK_MIF1 */
1146 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1147 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1148 CLK_IGNORE_UNUSED, 0),
1149 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1150 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1151 27, CLK_IGNORE_UNUSED, 0),
1152 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1153 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1154 26, CLK_IGNORE_UNUSED, 0),
1155 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1156 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1157 25, CLK_IGNORE_UNUSED, 0),
1158 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1159 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1160 24, CLK_IGNORE_UNUSED, 0),
1161 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1162 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1163 23, CLK_IGNORE_UNUSED, 0),
1164 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1165 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1166 22, CLK_IGNORE_UNUSED, 0),
1167 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1168 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1169 21, CLK_IGNORE_UNUSED, 0),
1170 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1171 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1172 20, CLK_IGNORE_UNUSED, 0),
1173 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1174 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1175 19, CLK_IGNORE_UNUSED, 0),
1176 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1177 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1178 18, CLK_IGNORE_UNUSED, 0),
1179 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1180 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1181 17, CLK_IGNORE_UNUSED, 0),
1182 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1183 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1184 16, CLK_IGNORE_UNUSED, 0),
1185 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1186 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1187 15, CLK_IGNORE_UNUSED, 0),
1188 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1189 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1190 14, CLK_IGNORE_UNUSED, 0),
1191 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1192 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1193 13, CLK_IGNORE_UNUSED, 0),
1194 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1195 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1196 12, CLK_IGNORE_UNUSED, 0),
1197 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1198 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1199 11, CLK_IGNORE_UNUSED, 0),
1200 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1201 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1202 10, CLK_IGNORE_UNUSED, 0),
1203 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1204 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1205 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1206 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1207 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1208 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1209 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1210 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1211 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1212 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1213 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1214 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1215 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1216 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1217 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1218 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1219 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1220 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1221 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1222 0, CLK_IGNORE_UNUSED, 0),
1223
1224 /* ENABLE_ACLK_MIF2 */
1225 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1226 ENABLE_ACLK_MIF2, 20, 0, 0),
1227 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1228 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1229 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1230 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1231 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1232 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1233 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1234 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1235 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1236 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1237 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1238 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1239 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1240 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1241 CLK_IGNORE_UNUSED, 0),
1242 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1243 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1244 5, CLK_IGNORE_UNUSED, 0),
1245 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1246 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1247 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1248 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1249 3, CLK_IGNORE_UNUSED, 0),
1250 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1251 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1252
1253 /* ENABLE_ACLK_MIF3 */
1254 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1255 ENABLE_ACLK_MIF3, 4,
1256 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1257 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1258 ENABLE_ACLK_MIF3, 1,
1259 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1260 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1261 ENABLE_ACLK_MIF3, 0,
1262 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1263
1264 /* ENABLE_PCLK_MIF */
1265 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1266 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1267 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1268 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1269 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1270 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1271 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1272 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1273 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1274 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1275 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1276 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1277 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1278 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1279 CLK_IGNORE_UNUSED, 0),
1280 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1281 ENABLE_PCLK_MIF, 19, 0, 0),
1282 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1283 ENABLE_PCLK_MIF, 18, 0, 0),
1284 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1285 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1286 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1287 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1288 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1289 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1290 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1291 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1292 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1293 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1294 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1295 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1296 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1297 ENABLE_PCLK_MIF, 11, 0, 0),
1298 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1299 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1300 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1301 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1302 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1303 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1304 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1305 ENABLE_PCLK_MIF, 7, 0, 0),
1306 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1307 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1308 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1309 ENABLE_PCLK_MIF, 5, 0, 0),
1310 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1311 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1312 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1313 ENABLE_PCLK_MIF, 2, 0, 0),
1314 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1315 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1316
1317 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1318 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1319 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1320
1321 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1322 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1323 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1324
1325 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1326 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1327 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1328
1329 /* ENABLE_PCLK_MIF_SECURE_RTC */
1330 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1331 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1332
1333 /* ENABLE_SCLK_MIF */
1334 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1335 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1336 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1337 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1338 14, CLK_IGNORE_UNUSED, 0),
1339 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1340 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1341 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1342 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1343 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1344 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1345 7, CLK_IGNORE_UNUSED, 0),
1346 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1347 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1348 6, CLK_IGNORE_UNUSED, 0),
1349 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1350 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1351 5, CLK_IGNORE_UNUSED, 0),
1352 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1353 ENABLE_SCLK_MIF, 4,
1354 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1355 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1356 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1358 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1359 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1360 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1361 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1362 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1363};
1364
774static struct samsung_cmu_info mif_cmu_info __initdata = { 1365static struct samsung_cmu_info mif_cmu_info __initdata = {
775 .pll_clks = mif_pll_clks, 1366 .pll_clks = mif_pll_clks,
776 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1367 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1368 .mux_clks = mif_mux_clks,
1369 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1370 .div_clks = mif_div_clks,
1371 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1372 .gate_clks = mif_gate_clks,
1373 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1374 .fixed_factor_clks = mif_fixed_factor_clks,
1375 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
777 .nr_clk_ids = MIF_NR_CLK, 1376 .nr_clk_ids = MIF_NR_CLK,
778 .clk_regs = mif_clk_regs, 1377 .clk_regs = mif_clk_regs,
779 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1378 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 08:56:44 -0500