diff options
author | Naveen Krishna Chatradhi <ch.naveen@samsung.com> | 2014-02-17 04:44:31 -0500 |
---|---|---|
committer | Tomasz Figa <t.figa@samsung.com> | 2014-05-14 13:23:26 -0400 |
commit | 5b73721b60360163169a8eccd3c4285f4a605d07 (patch) | |
tree | 34dfdb2e750fde2d75cbb7cde0b7f4848e7ecf95 /drivers/clk/samsung/clk-exynos5420.c | |
parent | 91a1263fd2bab8704fa0a940c1ab6b813143ecc4 (diff) |
clk: samsung: exynos5250/5420: Add gate clock for SSS module
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
-rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index c3e0894d0279..a8704540a214 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #define DIV_CPU1 0x504 | 27 | #define DIV_CPU1 0x504 |
28 | #define GATE_BUS_CPU 0x700 | 28 | #define GATE_BUS_CPU 0x700 |
29 | #define GATE_SCLK_CPU 0x800 | 29 | #define GATE_SCLK_CPU 0x800 |
30 | #define GATE_IP_G2D 0x8800 | ||
30 | #define CPLL_LOCK 0x10020 | 31 | #define CPLL_LOCK 0x10020 |
31 | #define DPLL_LOCK 0x10030 | 32 | #define DPLL_LOCK 0x10030 |
32 | #define EPLL_LOCK 0x10040 | 33 | #define EPLL_LOCK 0x10040 |
@@ -515,6 +516,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { | |||
515 | }; | 516 | }; |
516 | 517 | ||
517 | static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { | 518 | static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { |
519 | /* G2D */ | ||
520 | GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), | ||
521 | |||
518 | /* TODO: Re-verify the CG bits for all the gate clocks */ | 522 | /* TODO: Re-verify the CG bits for all the gate clocks */ |
519 | GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, | 523 | GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, |
520 | "mct"), | 524 | "mct"), |