diff options
author | Sachin Kamat <sachin.kamat@linaro.org> | 2013-08-07 00:48:39 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2013-08-08 18:57:36 -0400 |
commit | 202e5ae945ad0662c4abaea38c58ab58a694cc44 (patch) | |
tree | c338f0a07b1f4e4d31341f2852190acf210c27c7 /drivers/clk/samsung/clk-exynos5420.c | |
parent | b6993ecb87ac65cf7e718f4f45579e4f78fc1c27 (diff) |
clk: exynos5420: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
-rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 872e13d5a444..e035fd0afbc7 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c | |||
@@ -147,7 +147,7 @@ enum exynos5420_clks { | |||
147 | * list of controller registers to be saved and restored during a | 147 | * list of controller registers to be saved and restored during a |
148 | * suspend/resume cycle. | 148 | * suspend/resume cycle. |
149 | */ | 149 | */ |
150 | static __initdata unsigned long exynos5420_clk_regs[] = { | 150 | static unsigned long exynos5420_clk_regs[] __initdata = { |
151 | SRC_CPU, | 151 | SRC_CPU, |
152 | DIV_CPU0, | 152 | DIV_CPU0, |
153 | DIV_CPU1, | 153 | DIV_CPU1, |
@@ -727,7 +727,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { | |||
727 | GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), | 727 | GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), |
728 | }; | 728 | }; |
729 | 729 | ||
730 | static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = { | 730 | static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { |
731 | [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, | 731 | [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, |
732 | APLL_CON0, NULL), | 732 | APLL_CON0, NULL), |
733 | [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, | 733 | [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, |
@@ -752,7 +752,7 @@ static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = { | |||
752 | KPLL_CON0, NULL), | 752 | KPLL_CON0, NULL), |
753 | }; | 753 | }; |
754 | 754 | ||
755 | static __initdata struct of_device_id ext_clk_match[] = { | 755 | static struct of_device_id ext_clk_match[] __initdata = { |
756 | { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, | 756 | { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, |
757 | { }, | 757 | { }, |
758 | }; | 758 | }; |