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authorThomas Abraham <thomas.abraham@linaro.org>2013-03-09 03:02:52 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-03-25 05:16:47 -0400
commite062b571777f52dfbfc15f9edc2d36a45664bb3a (patch)
tree7764928dfa8963d2cdf9c052726aa6bc65d4effd /drivers/clk/samsung/clk-exynos4.c
parent1c4c5fe0b787ab02bf7c01b091e82e8d09ee1d64 (diff)
clk: exynos4: register clocks using common clock framework
The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c843
1 files changed, 843 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..e1bb81a1c264
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,843 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Exynos4 SoCs.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23/* Exynos4 clock controller register offsets */
24#define SRC_LEFTBUS 0x4200
25#define E4X12_GATE_IP_IMAGE 0x4930
26#define GATE_IP_RIGHTBUS 0x8800
27#define E4X12_GATE_IP_PERIR 0x8960
28#define SRC_TOP0 0xc210
29#define SRC_TOP1 0xc214
30#define SRC_CAM 0xc220
31#define SRC_TV 0xc224
32#define SRC_MFC 0xcc28
33#define SRC_G3D 0xc22c
34#define E4210_SRC_IMAGE 0xc230
35#define SRC_LCD0 0xc234
36#define SRC_LCD1 0xc238
37#define SRC_MAUDIO 0xc23c
38#define SRC_FSYS 0xc240
39#define SRC_PERIL0 0xc250
40#define SRC_PERIL1 0xc254
41#define E4X12_SRC_CAM1 0xc258
42#define SRC_MASK_CAM 0xc320
43#define SRC_MASK_TV 0xc324
44#define SRC_MASK_LCD0 0xc334
45#define SRC_MASK_LCD1 0xc338
46#define SRC_MASK_MAUDIO 0xc33c
47#define SRC_MASK_FSYS 0xc340
48#define SRC_MASK_PERIL0 0xc350
49#define SRC_MASK_PERIL1 0xc354
50#define DIV_TOP 0xc510
51#define DIV_CAM 0xc520
52#define DIV_TV 0xc524
53#define DIV_MFC 0xc528
54#define DIV_G3D 0xc52c
55#define DIV_IMAGE 0xc530
56#define DIV_LCD0 0xc534
57#define E4210_DIV_LCD1 0xc538
58#define E4X12_DIV_ISP 0xc538
59#define DIV_MAUDIO 0xc53c
60#define DIV_FSYS0 0xc540
61#define DIV_FSYS1 0xc544
62#define DIV_FSYS2 0xc548
63#define DIV_FSYS3 0xc54c
64#define DIV_PERIL0 0xc550
65#define DIV_PERIL1 0xc554
66#define DIV_PERIL2 0xc558
67#define DIV_PERIL3 0xc55c
68#define DIV_PERIL4 0xc560
69#define DIV_PERIL5 0xc564
70#define E4X12_DIV_CAM1 0xc568
71#define GATE_SCLK_CAM 0xc820
72#define GATE_IP_CAM 0xc920
73#define GATE_IP_TV 0xc924
74#define GATE_IP_MFC 0xc928
75#define GATE_IP_G3D 0xc92c
76#define E4210_GATE_IP_IMAGE 0xc930
77#define GATE_IP_LCD0 0xc934
78#define GATE_IP_LCD1 0xc938
79#define E4X12_GATE_IP_MAUDIO 0xc93c
80#define GATE_IP_FSYS 0xc940
81#define GATE_IP_GPS 0xc94c
82#define GATE_IP_PERIL 0xc950
83#define GATE_IP_PERIR 0xc960
84#define E4X12_MPLL_CON0 0x10108
85#define E4X12_SRC_DMC 0x10200
86#define APLL_CON0 0x14100
87#define E4210_MPLL_CON0 0x14108
88#define SRC_CPU 0x14200
89#define DIV_CPU0 0x14500
90
91/* the exynos4 soc type */
92enum exynos4_soc {
93 EXYNOS4210,
94 EXYNOS4X12,
95};
96
97/*
98 * Let each supported clock get a unique id. This id is used to lookup the clock
99 * for device tree based platforms. The clocks are categorized into three
100 * sections: core, sclk gate and bus interface gate clocks.
101 *
102 * When adding a new clock to this list, it is advised to choose a clock
103 * category and add it to the end of that category. That is because the the
104 * device tree source file is referring to these ids and any change in the
105 * sequence number of existing clocks will require corresponding change in the
106 * device tree files. This limitation would go away when pre-processor support
107 * for dtc would be available.
108 */
109enum exynos4_clks {
110 none,
111
112 /* core clocks */
113 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
114 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
115 aclk160, aclk133,
116
117 /* gate for special clocks (sclk) */
118 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
119 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
120 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
121 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
122 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
123 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
124 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
125 sclk_i2s2, sclk_mipihsi,
126
127 /* gate clocks */
128 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
129 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
130 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
131 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
132 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
133 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
134 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
135 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
136 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
137 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
138 audss, mipi_hsi, mdma2,
139
140 nr_clks,
141};
142
143/*
144 * list of controller registers to be saved and restored during a
145 * suspend/resume cycle.
146 */
147static __initdata unsigned long exynos4_clk_regs[] = {
148 SRC_LEFTBUS,
149 E4X12_GATE_IP_IMAGE,
150 GATE_IP_RIGHTBUS,
151 E4X12_GATE_IP_PERIR,
152 SRC_TOP0,
153 SRC_TOP1,
154 SRC_CAM,
155 SRC_TV,
156 SRC_MFC,
157 SRC_G3D,
158 E4210_SRC_IMAGE,
159 SRC_LCD0,
160 SRC_LCD1,
161 SRC_MAUDIO,
162 SRC_FSYS,
163 SRC_PERIL0,
164 SRC_PERIL1,
165 E4X12_SRC_CAM1,
166 SRC_MASK_CAM,
167 SRC_MASK_TV,
168 SRC_MASK_LCD0,
169 SRC_MASK_LCD1,
170 SRC_MASK_MAUDIO,
171 SRC_MASK_FSYS,
172 SRC_MASK_PERIL0,
173 SRC_MASK_PERIL1,
174 DIV_TOP,
175 DIV_CAM,
176 DIV_TV,
177 DIV_MFC,
178 DIV_G3D,
179 DIV_IMAGE,
180 DIV_LCD0,
181 E4210_DIV_LCD1,
182 E4X12_DIV_ISP,
183 DIV_MAUDIO,
184 DIV_FSYS0,
185 DIV_FSYS1,
186 DIV_FSYS2,
187 DIV_FSYS3,
188 DIV_PERIL0,
189 DIV_PERIL1,
190 DIV_PERIL2,
191 DIV_PERIL3,
192 DIV_PERIL4,
193 DIV_PERIL5,
194 E4X12_DIV_CAM1,
195 GATE_SCLK_CAM,
196 GATE_IP_CAM,
197 GATE_IP_TV,
198 GATE_IP_MFC,
199 GATE_IP_G3D,
200 E4210_GATE_IP_IMAGE,
201 GATE_IP_LCD0,
202 GATE_IP_LCD1,
203 E4X12_GATE_IP_MAUDIO,
204 GATE_IP_FSYS,
205 GATE_IP_GPS,
206 GATE_IP_PERIL,
207 GATE_IP_PERIR,
208 E4X12_MPLL_CON0,
209 E4X12_SRC_DMC,
210 APLL_CON0,
211 E4210_MPLL_CON0,
212 SRC_CPU,
213 DIV_CPU0,
214};
215
216/* list of all parent clock list */
217PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
218PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
219PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
220PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
221PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
222PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
223PNAME(mout_core_p) = { "mout_apll", "sclk_mpll", };
224PNAME(sclk_ampll_p) = { "sclk_mpll", "sclk_apll", };
225PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll", };
226PNAME(aclk_p4412) = { "mout_mpll_user", "sclk_apll", };
227PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
228PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
229PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
230PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
231PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
232PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
233PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
234PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
235PNAME(group1_p) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
236 "none", "sclk_hdmiphy", "sclk_mpll",
237 "sclk_epll", "sclk_vpll", };
238PNAME(mout_audio0_p) = { "cdclk0", "none", "sclk_hdmi24m", "sclk_usbphy0",
239 "xxti", "xusbxti", "sclk_mpll", "sclk_epll",
240 "sclk_vpll" };
241PNAME(mout_audio1_p) = { "cdclk1", "none", "sclk_hdmi24m", "sclk_usbphy0",
242 "xxti", "xusbxti", "sclk_mpll", "sclk_epll",
243 "sclk_vpll", };
244PNAME(mout_audio2_p) = { "cdclk2", "none", "sclk_hdmi24m", "sclk_usbphy0",
245 "xxti", "xusbxti", "sclk_mpll", "sclk_epll",
246 "sclk_vpll", };
247PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
248 "spdif_extclk", };
249
250/* fixed rate clocks generated outside the soc */
251struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
252 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
253 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
254};
255
256/* fixed rate clocks generated inside the soc */
257struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
258 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
259 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
260 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
261};
262
263struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
264 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
265};
266
267/* list of mux clocks supported in all exynos4 soc's */
268struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
269 MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
270 MUX(none, "mout_core", mout_core_p, SRC_CPU, 16, 1),
271 MUX(none, "mout_fimc0", group1_p, SRC_CAM, 0, 4),
272 MUX(none, "mout_fimc1", group1_p, SRC_CAM, 4, 4),
273 MUX(none, "mout_fimc2", group1_p, SRC_CAM, 8, 4),
274 MUX(none, "mout_fimc3", group1_p, SRC_CAM, 12, 4),
275 MUX(none, "mout_cam0", group1_p, SRC_CAM, 16, 4),
276 MUX(none, "mout_cam1", group1_p, SRC_CAM, 20, 4),
277 MUX(none, "mout_csis0", group1_p, SRC_CAM, 24, 4),
278 MUX(none, "mout_csis1", group1_p, SRC_CAM, 28, 4),
279 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
280 MUX(none, "mout_mfc0", sclk_ampll_p, SRC_MFC, 0, 1),
281 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
282 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
283 MUX(none, "mout_g3d0", sclk_ampll_p, SRC_G3D, 0, 1),
284 MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1),
285 MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
286 MUX(none, "mout_fimd0", group1_p, SRC_LCD0, 0, 4),
287 MUX(none, "mout_mipi0", group1_p, SRC_LCD0, 12, 4),
288 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAUDIO, 0, 4),
289 MUX(none, "mout_mmc0", group1_p, SRC_FSYS, 0, 4),
290 MUX(none, "mout_mmc1", group1_p, SRC_FSYS, 4, 4),
291 MUX(none, "mout_mmc2", group1_p, SRC_FSYS, 8, 4),
292 MUX(none, "mout_mmc3", group1_p, SRC_FSYS, 12, 4),
293 MUX(none, "mout_mmc4", group1_p, SRC_FSYS, 16, 4),
294 MUX(none, "mout_uart0", group1_p, SRC_PERIL0, 0, 4),
295 MUX(none, "mout_uart1", group1_p, SRC_PERIL0, 4, 4),
296 MUX(none, "mout_uart2", group1_p, SRC_PERIL0, 8, 4),
297 MUX(none, "mout_uart3", group1_p, SRC_PERIL0, 12, 4),
298 MUX(none, "mout_uart4", group1_p, SRC_PERIL0, 16, 4),
299 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIL1, 0, 4),
300 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIL1, 4, 4),
301 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
302 MUX(none, "mout_spi0", group1_p, SRC_PERIL1, 16, 4),
303 MUX(none, "mout_spi1", group1_p, SRC_PERIL1, 20, 4),
304 MUX(none, "mout_spi2", group1_p, SRC_PERIL1, 24, 4),
305 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
306};
307
308/* list of mux clocks supported in exynos4210 soc */
309struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
310 MUX(none, "mout_aclk200", sclk_ampll_p, SRC_TOP0, 12, 1),
311 MUX(none, "mout_aclk100", sclk_ampll_p, SRC_TOP0, 16, 1),
312 MUX(none, "mout_aclk160", sclk_ampll_p, SRC_TOP0, 20, 1),
313 MUX(none, "mout_aclk133", sclk_ampll_p, SRC_TOP0, 24, 1),
314 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
315 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
316 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
317 MUX(none, "mout_g2d0", sclk_ampll_p, E4210_SRC_IMAGE, 0, 1),
318 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
319 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
320 MUX(none, "mout_fimd1", group1_p, SRC_LCD1, 0, 4),
321 MUX(none, "mout_mipi1", group1_p, SRC_LCD1, 12, 4),
322 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
323 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
324 SRC_TOP0, 8, 1, "sclk_vpll"),
325};
326
327/* list of mux clocks supported in exynos4x12 soc */
328struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
329 MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_LEFTBUS, 4, 1),
330 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
331 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
332 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
333 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
334 MUX(none, "mout_mdnie0", group1_p, SRC_LCD0, 4, 4),
335 MUX(none, "mout_mdnie_pwm0", group1_p, SRC_LCD0, 8, 4),
336 MUX(none, "mout_sata", sclk_ampll_p, SRC_FSYS, 24, 1),
337 MUX(none, "mout_jpeg0", sclk_ampll_p, E4X12_SRC_CAM1, 0, 1),
338 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
339 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
340 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
341 E4X12_SRC_DMC, 12, 1, "sclk_mpll"),
342 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
343 SRC_TOP0, 8, 1, "sclk_vpll"),
344};
345
346/* list of divider clocks supported in all exynos4 soc's */
347struct samsung_div_clock exynos4_div_clks[] __initdata = {
348 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
349 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
350 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
351 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
352 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
353 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
354 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
355 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
356 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
357 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
358 DIV(none, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
359 DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
360 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
361 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
362 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
363 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
364 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
365 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
366 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
367 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
368 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
369 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
370 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
371 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
372 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
373 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
374 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
375 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
376 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
377 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
378 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
379 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
380 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
381 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
382 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
383 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
384 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
385 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
386 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
387 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
388 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
389 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
390 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
391 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
392 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
393 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
394 DIV_A(sclk_apll, "sclk_apll", "mout_apll",
395 DIV_CPU0, 24, 3, "sclk_apll"),
396 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
397 CLK_SET_RATE_PARENT, 0),
398 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
399 CLK_SET_RATE_PARENT, 0),
400 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
401 CLK_SET_RATE_PARENT, 0),
402 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
403 CLK_SET_RATE_PARENT, 0),
404 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
405 CLK_SET_RATE_PARENT, 0),
406};
407
408/* list of divider clocks supported in exynos4210 soc */
409struct samsung_div_clock exynos4210_div_clks[] __initdata = {
410 DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
411 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
412 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
413 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
414 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
415 CLK_SET_RATE_PARENT, 0),
416};
417
418/* list of divider clocks supported in exynos4x12 soc */
419struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
420 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
421 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
422 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
423 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
424 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
425};
426
427/* list of gate clocks supported in all exynos4 soc's */
428struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
429 /*
430 * After all Exynos4 based platforms are migrated to use device tree,
431 * the device name and clock alias names specified below for some
432 * of the clocks can be removed.
433 */
434 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
435 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
436 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
437 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0),
438 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
439 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
440 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
441 GATE(fimd1, "fimd1", "aclk160", GATE_IP_LCD1, 0, 0, 0),
442 GATE(mie1, "mie1", "aclk160", GATE_IP_LCD1, 1, 0, 0),
443 GATE(dsim1, "dsim1", "aclk160", GATE_IP_LCD1, 3, 0, 0),
444 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0),
445 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
446 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
447 GATE(g3d, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
448 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
449 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
450 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
451 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
452 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
453 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
454 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
455 CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
457 CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
459 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
460 GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
461 CLK_SET_RATE_PARENT, 0),
462 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
463 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
464 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
465 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
466 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
467 GATE_A(usb_host, "usb_host", "aclk133",
468 GATE_IP_FSYS, 12, 0, 0, "usbhost"),
469 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
470 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
471 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
472 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
473 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
474 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
475 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
476 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
477 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
478 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
479 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
480 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
481 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
482 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
483 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
484 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
485 "mmc_busclk.2"),
486 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
487 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
488 "mmc_busclk.2"),
489 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
490 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
491 "mmc_busclk.2"),
492 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
493 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
494 "mmc_busclk.2"),
495 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
496 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
497 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
498 0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
499 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
500 0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
501 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
502 0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
503 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
504 0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
505 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
506 0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
507 GATE(sclk_audio2, "sclk_audio2", "div_audio2", 0xc354, 4,
508 CLK_SET_RATE_PARENT, 0),
509 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
510 0xc354, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
511 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
512 0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
513 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
514 0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
515 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
516 GATE_IP_CAM, 0, 0, 0, "fimc"),
517 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
518 GATE_IP_CAM, 1, 0, 0, "fimc"),
519 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
520 GATE_IP_CAM, 2, 0, 0, "fimc"),
521 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
522 GATE_IP_CAM, 3, 0, 0, "fimc"),
523 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
524 GATE_IP_CAM, 4, 0, 0, "fimc"),
525 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
526 GATE_IP_CAM, 5, 0, 0, "fimc"),
527 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
528 GATE_IP_CAM, 7, 0, 0, "sysmmu"),
529 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
530 GATE_IP_CAM, 8, 0, 0, "sysmmu"),
531 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
532 GATE_IP_CAM, 9, 0, 0, "sysmmu"),
533 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
534 GATE_IP_CAM, 10, 0, 0, "sysmmu"),
535 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
536 GATE_IP_CAM, 11, 0, 0, "sysmmu"),
537 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
538 GATE_IP_TV, 4, 0, 0, "sysmmu"),
539 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
540 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
541 GATE_IP_MFC, 1, 0, 0, "sysmmu"),
542 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
543 GATE_IP_MFC, 2, 0, 0, "sysmmu"),
544 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
545 GATE_IP_LCD0, 0, 0, 0, "fimd"),
546 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
547 GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
548 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
549 GATE_IP_FSYS, 0, 0, 0, "dma"),
550 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
551 GATE_IP_FSYS, 1, 0, 0, "dma"),
552 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
553 GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
554 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
555 GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
556 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
557 GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
558 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
559 GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
560 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
561 GATE_IP_PERIL, 0, 0, 0, "uart"),
562 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
563 GATE_IP_PERIL, 1, 0, 0, "uart"),
564 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
565 GATE_IP_PERIL, 2, 0, 0, "uart"),
566 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
567 GATE_IP_PERIL, 3, 0, 0, "uart"),
568 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
569 GATE_IP_PERIL, 4, 0, 0, "uart"),
570 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
571 GATE_IP_PERIL, 6, 0, 0, "i2c"),
572 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
573 GATE_IP_PERIL, 7, 0, 0, "i2c"),
574 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
575 GATE_IP_PERIL, 8, 0, 0, "i2c"),
576 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
577 GATE_IP_PERIL, 9, 0, 0, "i2c"),
578 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
579 GATE_IP_PERIL, 10, 0, 0, "i2c"),
580 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
581 GATE_IP_PERIL, 11, 0, 0, "i2c"),
582 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
583 GATE_IP_PERIL, 12, 0, 0, "i2c"),
584 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
585 GATE_IP_PERIL, 13, 0, 0, "i2c"),
586 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
587 GATE_IP_PERIL, 14, 0, 0, "i2c"),
588 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
589 GATE_IP_PERIL, 16, 0, 0, "spi"),
590 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
591 GATE_IP_PERIL, 17, 0, 0, "spi"),
592 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
593 GATE_IP_PERIL, 18, 0, 0, "spi"),
594 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
595 GATE_IP_PERIL, 20, 0, 0, "iis"),
596 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
597 GATE_IP_PERIL, 21, 0, 0, "iis"),
598 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
599 GATE_IP_PERIL, 22, 0, 0, "pcm"),
600 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
601 GATE_IP_PERIL, 23, 0, 0, "pcm"),
602 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
603 GATE_IP_PERIL, 26, 0, 0, "spdif"),
604 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
605 GATE_IP_PERIL, 27, 0, 0, "ac97"),
606};
607
608/* list of gate clocks supported in exynos4210 soc */
609struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
610 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
611 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
612 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
613 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
614 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
615 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
616 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
617 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
618 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
619 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
620 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
621 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
622 GATE(chipid, "chipid", "aclk100", GATE_IP_PERIR, 0, 0, 0),
623 GATE(sysreg, "sysreg", "aclk100", GATE_IP_PERIR, 0, 0, 0),
624 GATE(hdmi_cec, "hdmi_cec", "aclk100", GATE_IP_PERIR, 11, 0, 0),
625 GATE(smmu_rotator, "smmu_rotator", "aclk200",
626 E4210_GATE_IP_IMAGE, 4, 0, 0),
627 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
628 SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
629 GATE(sclk_sata, "sclk_sata", "div_sata",
630 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
631 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
632 GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"),
633 GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"),
634 GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"),
635 GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"),
636 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
637 SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
638};
639
640/* list of gate clocks supported in exynos4x12 soc */
641struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
642 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
643 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
644 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
645 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
646 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
647 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
648 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
649 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
650 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
651 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
652 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
653 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
654 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
655 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
656 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
657 GATE(smmu_rotator, "smmu_rotator", "aclk200",
658 E4X12_GATE_IP_IMAGE, 4, 0, 0),
659 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
660 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
661 GATE_A(keyif, "keyif", "aclk100",
662 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
663 GATE_A(wdt, "watchdog", "aclk100",
664 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
665 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
666 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
667 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
668 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
669};
670
671#ifdef CONFIG_OF
672static struct of_device_id exynos4_clk_ids[] __initdata = {
673 { .compatible = "samsung,exynos4210-clock",
674 .data = (void *)EXYNOS4210, },
675 { .compatible = "samsung,exynos4412-clock",
676 .data = (void *)EXYNOS4X12, },
677 { },
678};
679#endif
680
681/*
682 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
683 * resides in chipid register space, outside of the clock controller memory
684 * mapped space. So to determine the parent of fin_pll clock, the chipid
685 * controller is first remapped and the value of XOM[0] bit is read to
686 * determine the parent clock.
687 */
688static void __init exynos4_clk_register_finpll(void)
689{
690 struct samsung_fixed_rate_clock fclk;
691 struct device_node *np;
692 struct clk *clk;
693 void __iomem *chipid_base = S5P_VA_CHIPID;
694 unsigned long xom, finpll_f = 24000000;
695 char *parent_name;
696
697 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
698 if (np)
699 chipid_base = of_iomap(np, 0);
700
701 if (chipid_base) {
702 xom = readl(chipid_base + 8);
703 parent_name = xom & 1 ? "xusbxti" : "xxti";
704 clk = clk_get(NULL, parent_name);
705 if (IS_ERR(clk)) {
706 pr_err("%s: failed to lookup parent clock %s, assuming "
707 "fin_pll clock frequency is 24MHz\n", __func__,
708 parent_name);
709 } else {
710 finpll_f = clk_get_rate(clk);
711 }
712 } else {
713 pr_err("%s: failed to map chipid registers, assuming "
714 "fin_pll clock frequency is 24MHz\n", __func__);
715 }
716
717 fclk.id = fin_pll;
718 fclk.name = "fin_pll";
719 fclk.parent_name = NULL;
720 fclk.flags = CLK_IS_ROOT;
721 fclk.fixed_rate = finpll_f;
722 samsung_clk_register_fixed_rate(&fclk, 1);
723
724 if (np)
725 iounmap(chipid_base);
726}
727
728/*
729 * This function allows non-dt platforms to specify the clock speed of the
730 * xxti and xusbxti clocks. These clocks are then registered with the specified
731 * clock speed.
732 */
733void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
734 unsigned long xusbxti_f)
735{
736 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
737 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
738 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
739 ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
740}
741
742static __initdata struct of_device_id ext_clk_match[] = {
743 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
744 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
745 {},
746};
747
748/* register exynos4 clocks */
749void __init exynos4_clk_init(struct device_node *np)
750{
751 void __iomem *reg_base;
752 struct clk *apll, *mpll, *epll, *vpll;
753 u32 exynos4_soc;
754
755 if (np) {
756 const struct of_device_id *match;
757 match = of_match_node(exynos4_clk_ids, np);
758 exynos4_soc = (u32)match->data;
759
760 reg_base = of_iomap(np, 0);
761 if (!reg_base)
762 panic("%s: failed to map registers\n", __func__);
763 } else {
764 reg_base = S5P_VA_CMU;
765 if (soc_is_exynos4210())
766 exynos4_soc = EXYNOS4210;
767 else if (soc_is_exynos4212() || soc_is_exynos4412())
768 exynos4_soc = EXYNOS4X12;
769 else
770 panic("%s: unable to determine soc\n", __func__);
771 }
772
773 samsung_clk_init(np, reg_base, nr_clks,
774 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs));
775
776 if (np)
777 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
778 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
779 ext_clk_match);
780
781 exynos4_clk_register_finpll();
782
783 if (exynos4_soc == EXYNOS4210) {
784 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
785 reg_base + APLL_CON0, pll_4508);
786 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
787 reg_base + E4210_MPLL_CON0, pll_4508);
788 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
789 reg_base + 0xc110, pll_4600);
790 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
791 reg_base + 0xc120, pll_4650c);
792 } else {
793 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
794 reg_base + APLL_CON0);
795 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
796 reg_base + E4X12_MPLL_CON0);
797 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
798 reg_base + 0xc110);
799 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
800 reg_base + 0xc120);
801 }
802
803 samsung_clk_add_lookup(apll, fout_apll);
804 samsung_clk_add_lookup(mpll, fout_mpll);
805 samsung_clk_add_lookup(epll, fout_epll);
806 samsung_clk_add_lookup(vpll, fout_vpll);
807
808 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
809 ARRAY_SIZE(exynos4_fixed_rate_clks));
810 samsung_clk_register_mux(exynos4_mux_clks,
811 ARRAY_SIZE(exynos4_mux_clks));
812 samsung_clk_register_div(exynos4_div_clks,
813 ARRAY_SIZE(exynos4_div_clks));
814 samsung_clk_register_gate(exynos4_gate_clks,
815 ARRAY_SIZE(exynos4_gate_clks));
816
817 if (exynos4_soc == EXYNOS4210) {
818 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
819 ARRAY_SIZE(exynos4210_fixed_rate_clks));
820 samsung_clk_register_mux(exynos4210_mux_clks,
821 ARRAY_SIZE(exynos4210_mux_clks));
822 samsung_clk_register_div(exynos4210_div_clks,
823 ARRAY_SIZE(exynos4210_div_clks));
824 samsung_clk_register_gate(exynos4210_gate_clks,
825 ARRAY_SIZE(exynos4210_gate_clks));
826 } else {
827 samsung_clk_register_mux(exynos4x12_mux_clks,
828 ARRAY_SIZE(exynos4x12_mux_clks));
829 samsung_clk_register_div(exynos4x12_div_clks,
830 ARRAY_SIZE(exynos4x12_div_clks));
831 samsung_clk_register_gate(exynos4x12_gate_clks,
832 ARRAY_SIZE(exynos4x12_gate_clks));
833 }
834
835 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
836 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
837 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
838 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
839 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
840 _get_rate("arm_clk"));
841}
842CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
843CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);