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authorTomasz Figa <t.figa@samsung.com>2013-08-26 13:09:06 -0400
committerMike Turquette <mturquette@linaro.org>2013-09-06 16:33:43 -0400
commitc50d11f35a021fc357922797a7638d4d6ca70b9e (patch)
treebdc0c3a42b4cb42e10feee7ae8d11f8fcd93b6d0 /drivers/clk/samsung/clk-exynos4.c
parentb4054ac6a26ee94a3a0f18e9ea585545d69e29c2 (diff)
clk: samsung: pll: Use new registration method for PLL46xx
This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c15
1 files changed, 5 insertions, 10 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index fd0215d99c88..779c2069e632 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -985,11 +985,15 @@ static struct of_device_id ext_clk_match[] __initdata = {
985 {}, 985 {},
986}; 986};
987 987
988static struct samsung_pll_clock exynos4210_plls[] __initdata = { 988static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
989 [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 989 [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
990 APLL_CON0, "fout_apll", NULL), 990 APLL_CON0, "fout_apll", NULL),
991 [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", 991 [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll",
992 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 992 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
993 [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
994 EPLL_CON0, "fout_epll", NULL),
995 [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc",
996 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
993}; 997};
994 998
995static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 999static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
@@ -1008,8 +1012,6 @@ static void __init exynos4_clk_init(struct device_node *np,
1008 enum exynos4_soc exynos4_soc, 1012 enum exynos4_soc exynos4_soc,
1009 void __iomem *reg_base, unsigned long xom) 1013 void __iomem *reg_base, unsigned long xom)
1010{ 1014{
1011 struct clk *epll, *vpll;
1012
1013 reg_base = of_iomap(np, 0); 1015 reg_base = of_iomap(np, 0);
1014 if (!reg_base) 1016 if (!reg_base)
1015 panic("%s: failed to map registers\n", __func__); 1017 panic("%s: failed to map registers\n", __func__);
@@ -1032,13 +1034,6 @@ static void __init exynos4_clk_init(struct device_node *np,
1032 if (exynos4_soc == EXYNOS4210) { 1034 if (exynos4_soc == EXYNOS4210) {
1033 samsung_clk_register_pll(exynos4210_plls, 1035 samsung_clk_register_pll(exynos4210_plls,
1034 ARRAY_SIZE(exynos4210_plls), reg_base); 1036 ARRAY_SIZE(exynos4210_plls), reg_base);
1035 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
1036 reg_base + EPLL_CON0, pll_4600);
1037 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
1038 reg_base + VPLL_CON0, pll_4650c);
1039
1040 samsung_clk_add_lookup(epll, fout_epll);
1041 samsung_clk_add_lookup(vpll, fout_vpll);
1042 } else { 1037 } else {
1043 samsung_clk_register_pll(exynos4x12_plls, 1038 samsung_clk_register_pll(exynos4x12_plls,
1044 ARRAY_SIZE(exynos4x12_plls), reg_base); 1039 ARRAY_SIZE(exynos4x12_plls), reg_base);