diff options
author | Heiko Stübner <heiko@sntech.de> | 2014-07-02 19:58:39 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-07-13 15:17:06 -0400 |
commit | a245fecbb8064641d9cc317b347b5bdb2b7a4bb6 (patch) | |
tree | d4573cc7258ecc18e9db839f809960062ee419b0 /drivers/clk/rockchip/clk.c | |
parent | 5a994e151f7c54a5fdeb07fe2fed4ed64b9321b8 (diff) |
clk: rockchip: add basic infrastructure for clock branches
This adds infrastructure for registering clock branches. On Rockchip SoCs
most clock branches are a combination of mux,divider and gate components,
thus a composite clock is used when appropriate.
Clock branches are supposed to be declared in an array using the COMPOSITE*
or MUX, etc makros defined in the header and then registered using
rockchip_clk_register_branches.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
-rw-r--r-- | drivers/clk/rockchip/clk.c | 209 |
1 files changed, 209 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c new file mode 100644 index 000000000000..aa15d5ae51d1 --- /dev/null +++ b/drivers/clk/rockchip/clk.c | |||
@@ -0,0 +1,209 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014 MundoReader S.L. | ||
3 | * Author: Heiko Stuebner <heiko@sntech.de> | ||
4 | * | ||
5 | * based on | ||
6 | * | ||
7 | * samsung/clk.c | ||
8 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
9 | * Copyright (c) 2013 Linaro Ltd. | ||
10 | * Author: Thomas Abraham <thomas.ab@samsung.com> | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License as published by | ||
14 | * the Free Software Foundation; either version 2 of the License, or | ||
15 | * (at your option) any later version. | ||
16 | * | ||
17 | * This program is distributed in the hope that it will be useful, | ||
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
20 | * GNU General Public License for more details. | ||
21 | */ | ||
22 | |||
23 | #include <linux/slab.h> | ||
24 | #include <linux/clk.h> | ||
25 | #include <linux/clk-provider.h> | ||
26 | #include "clk.h" | ||
27 | |||
28 | /** | ||
29 | * Register a clock branch. | ||
30 | * Most clock branches have a form like | ||
31 | * | ||
32 | * src1 --|--\ | ||
33 | * |M |--[GATE]-[DIV]- | ||
34 | * src2 --|--/ | ||
35 | * | ||
36 | * sometimes without one of those components. | ||
37 | */ | ||
38 | struct clk *rockchip_clk_register_branch(const char *name, | ||
39 | const char **parent_names, u8 num_parents, void __iomem *base, | ||
40 | int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, | ||
41 | u8 div_shift, u8 div_width, u8 div_flags, | ||
42 | struct clk_div_table *div_table, int gate_offset, | ||
43 | u8 gate_shift, u8 gate_flags, unsigned long flags, | ||
44 | spinlock_t *lock) | ||
45 | { | ||
46 | struct clk *clk; | ||
47 | struct clk_mux *mux = NULL; | ||
48 | struct clk_gate *gate = NULL; | ||
49 | struct clk_divider *div = NULL; | ||
50 | const struct clk_ops *mux_ops = NULL, *div_ops = NULL, | ||
51 | *gate_ops = NULL; | ||
52 | |||
53 | if (num_parents > 1) { | ||
54 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | ||
55 | if (!mux) | ||
56 | return ERR_PTR(-ENOMEM); | ||
57 | |||
58 | mux->reg = base + muxdiv_offset; | ||
59 | mux->shift = mux_shift; | ||
60 | mux->mask = BIT(mux_width) - 1; | ||
61 | mux->flags = mux_flags; | ||
62 | mux->lock = lock; | ||
63 | mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops | ||
64 | : &clk_mux_ops; | ||
65 | } | ||
66 | |||
67 | if (gate_offset >= 0) { | ||
68 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | ||
69 | if (!gate) | ||
70 | return ERR_PTR(-ENOMEM); | ||
71 | |||
72 | gate->flags = gate_flags; | ||
73 | gate->reg = base + gate_offset; | ||
74 | gate->bit_idx = gate_shift; | ||
75 | gate->lock = lock; | ||
76 | gate_ops = &clk_gate_ops; | ||
77 | } | ||
78 | |||
79 | if (div_width > 0) { | ||
80 | div = kzalloc(sizeof(*div), GFP_KERNEL); | ||
81 | if (!div) | ||
82 | return ERR_PTR(-ENOMEM); | ||
83 | |||
84 | div->flags = div_flags; | ||
85 | div->reg = base + muxdiv_offset; | ||
86 | div->shift = div_shift; | ||
87 | div->width = div_width; | ||
88 | div->lock = lock; | ||
89 | div->table = div_table; | ||
90 | div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) | ||
91 | ? &clk_divider_ro_ops | ||
92 | : &clk_divider_ops; | ||
93 | } | ||
94 | |||
95 | clk = clk_register_composite(NULL, name, parent_names, num_parents, | ||
96 | mux ? &mux->hw : NULL, mux_ops, | ||
97 | div ? &div->hw : NULL, div_ops, | ||
98 | gate ? &gate->hw : NULL, gate_ops, | ||
99 | flags); | ||
100 | |||
101 | return clk; | ||
102 | } | ||
103 | |||
104 | static DEFINE_SPINLOCK(clk_lock); | ||
105 | static struct clk **clk_table; | ||
106 | static void __iomem *reg_base; | ||
107 | static struct clk_onecell_data clk_data; | ||
108 | |||
109 | void __init rockchip_clk_init(struct device_node *np, void __iomem *base, | ||
110 | unsigned long nr_clks) | ||
111 | { | ||
112 | reg_base = base; | ||
113 | |||
114 | clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); | ||
115 | if (!clk_table) | ||
116 | pr_err("%s: could not allocate clock lookup table\n", __func__); | ||
117 | |||
118 | clk_data.clks = clk_table; | ||
119 | clk_data.clk_num = nr_clks; | ||
120 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
121 | } | ||
122 | |||
123 | void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) | ||
124 | { | ||
125 | if (clk_table && id) | ||
126 | clk_table[id] = clk; | ||
127 | } | ||
128 | |||
129 | void __init rockchip_clk_register_branches( | ||
130 | struct rockchip_clk_branch *list, | ||
131 | unsigned int nr_clk) | ||
132 | { | ||
133 | struct clk *clk = NULL; | ||
134 | unsigned int idx; | ||
135 | unsigned long flags; | ||
136 | |||
137 | for (idx = 0; idx < nr_clk; idx++, list++) { | ||
138 | flags = list->flags; | ||
139 | |||
140 | /* catch simple muxes */ | ||
141 | switch (list->branch_type) { | ||
142 | case branch_mux: | ||
143 | clk = clk_register_mux(NULL, list->name, | ||
144 | list->parent_names, list->num_parents, | ||
145 | flags, reg_base + list->muxdiv_offset, | ||
146 | list->mux_shift, list->mux_width, | ||
147 | list->mux_flags, &clk_lock); | ||
148 | break; | ||
149 | case branch_divider: | ||
150 | if (list->div_table) | ||
151 | clk = clk_register_divider_table(NULL, | ||
152 | list->name, list->parent_names[0], | ||
153 | flags, reg_base + list->muxdiv_offset, | ||
154 | list->div_shift, list->div_width, | ||
155 | list->div_flags, list->div_table, | ||
156 | &clk_lock); | ||
157 | else | ||
158 | clk = clk_register_divider(NULL, list->name, | ||
159 | list->parent_names[0], flags, | ||
160 | reg_base + list->muxdiv_offset, | ||
161 | list->div_shift, list->div_width, | ||
162 | list->div_flags, &clk_lock); | ||
163 | break; | ||
164 | case branch_fraction_divider: | ||
165 | /* unimplemented */ | ||
166 | continue; | ||
167 | break; | ||
168 | case branch_gate: | ||
169 | flags |= CLK_SET_RATE_PARENT; | ||
170 | |||
171 | /* keep all gates untouched for now */ | ||
172 | flags |= CLK_IGNORE_UNUSED; | ||
173 | |||
174 | clk = clk_register_gate(NULL, list->name, | ||
175 | list->parent_names[0], flags, | ||
176 | reg_base + list->gate_offset, | ||
177 | list->gate_shift, list->gate_flags, &clk_lock); | ||
178 | break; | ||
179 | case branch_composite: | ||
180 | /* keep all gates untouched for now */ | ||
181 | flags |= CLK_IGNORE_UNUSED; | ||
182 | |||
183 | clk = rockchip_clk_register_branch(list->name, | ||
184 | list->parent_names, list->num_parents, | ||
185 | reg_base, list->muxdiv_offset, list->mux_shift, | ||
186 | list->mux_width, list->mux_flags, | ||
187 | list->div_shift, list->div_width, | ||
188 | list->div_flags, list->div_table, | ||
189 | list->gate_offset, list->gate_shift, | ||
190 | list->gate_flags, flags, &clk_lock); | ||
191 | break; | ||
192 | } | ||
193 | |||
194 | /* none of the cases above matched */ | ||
195 | if (!clk) { | ||
196 | pr_err("%s: unknown clock type %d\n", | ||
197 | __func__, list->branch_type); | ||
198 | continue; | ||
199 | } | ||
200 | |||
201 | if (IS_ERR(clk)) { | ||
202 | pr_err("%s: failed to register clock %s: %ld\n", | ||
203 | __func__, list->name, PTR_ERR(clk)); | ||
204 | continue; | ||
205 | } | ||
206 | |||
207 | rockchip_clk_add_lookup(clk, list->id); | ||
208 | } | ||
209 | } | ||