clk: rockchip: add new clock-type for the cpuclk

When changing the armclk on Rockchip SoCs it is supposed to be reparented
to an alternate parent before changing the underlying pll and back after
the change. Additionally there exist clocks that are very tightly bound to
the armclk whose divider values are set according to the armclk rate.

Add a special clock-type to handle all that. The rate table and divider
values will be supplied from the soc-specific clock controllers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
On a rk3288-board:
Tested-by: Doug Anderson <dianders@chromium.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index ee6b077381e1..bd8514d63634 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -5,6 +5,7 @@
 obj-y   += clk-rockchip.o
 obj-y   += clk.o
 obj-y   += clk-pll.o
+obj-y   += clk-cpu.o
 obj-$(CONFIG_RESET_CONTROLLER)  += softrst.o
 
 obj-y   += clk-rk3188.o