aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/qcom
diff options
context:
space:
mode:
authorMike Turquette <mturquette@linaro.org>2014-07-25 18:41:19 -0400
committerMike Turquette <mturquette@linaro.org>2014-07-25 18:41:19 -0400
commit9ae1400588a114be908bcf650aa57309c1a508ed (patch)
tree71125ed62fc3a202b0c5b69000922221bf9defff /drivers/clk/qcom
parent07761baff028927824292930c181339a53cfbd77 (diff)
parente216ce60a9e05ab399d098f05cd86fd95c9da8d5 (diff)
Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm
qcom clock changes for 3.17 These patches add support for a handful of Qualcomm's SoC clock controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064. There's also a small collection of bug fixes that aren't critical -rc worthy regressions because the consumer drivers aren't present or using the buggy clocks and one optimization for HDMI.
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r--drivers/clk/qcom/Kconfig25
-rw-r--r--drivers/clk/qcom/Makefile3
-rw-r--r--drivers/clk/qcom/clk-pll.c15
-rw-r--r--drivers/clk/qcom/clk-pll.h2
-rw-r--r--drivers/clk/qcom/clk-rcg.c51
-rw-r--r--drivers/clk/qcom/clk-rcg.h1
-rw-r--r--drivers/clk/qcom/common.c39
-rw-r--r--drivers/clk/qcom/common.h6
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c3611
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c2424
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c583
-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c3352
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c526
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c10
14 files changed, 10568 insertions, 80 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7f696b7d4422..1107351ed346 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -4,6 +4,31 @@ config COMMON_CLK_QCOM
4 select REGMAP_MMIO 4 select REGMAP_MMIO
5 select RESET_CONTROLLER 5 select RESET_CONTROLLER
6 6
7config APQ_GCC_8084
8 tristate "APQ8084 Global Clock Controller"
9 depends on COMMON_CLK_QCOM
10 help
11 Support for the global clock controller on apq8084 devices.
12 Say Y if you want to use peripheral devices such as UART, SPI,
13 i2c, USB, SD/eMMC, SATA, PCIe, etc.
14
15config APQ_MMCC_8084
16 tristate "APQ8084 Multimedia Clock Controller"
17 select APQ_GCC_8084
18 depends on COMMON_CLK_QCOM
19 help
20 Support for the multimedia clock controller on apq8084 devices.
21 Say Y if you want to support multimedia devices such as display,
22 graphics, video encode/decode, camera, etc.
23
24config IPQ_GCC_806X
25 tristate "IPQ806x Global Clock Controller"
26 depends on COMMON_CLK_QCOM
27 help
28 Support for the global clock controller on ipq806x devices.
29 Say Y if you want to use peripheral devices such as UART, SPI,
30 i2c, USB, SD/eMMC, etc.
31
7config MSM_GCC_8660 32config MSM_GCC_8660
8 tristate "MSM8660 Global Clock Controller" 33 tristate "MSM8660 Global Clock Controller"
9 depends on COMMON_CLK_QCOM 34 depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 689e05bf4f95..783cfb24faa4 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,6 +8,9 @@ clk-qcom-y += clk-rcg2.o
8clk-qcom-y += clk-branch.o 8clk-qcom-y += clk-branch.o
9clk-qcom-y += reset.o 9clk-qcom-y += reset.o
10 10
11obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
12obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
13obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
11obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 14obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
12obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 15obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
13obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 16obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 0f927c538613..9db03d3b1657 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = {
166EXPORT_SYMBOL_GPL(clk_pll_vote_ops); 166EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
167 167
168static void 168static void
169clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) 169clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
170{ 170{
171 u32 val; 171 u32 val;
172 u32 mask; 172 u32 mask;
@@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); 175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
176 176
177 /* Program bias count and lock count */ 177 /* Program bias count and lock count */
178 val = 1 << PLL_BIAS_COUNT_SHIFT; 178 val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
181 regmap_update_bits(regmap, pll->mode_reg, mask, val); 181 regmap_update_bits(regmap, pll->mode_reg, mask, val);
@@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
212 regmap_update_bits(regmap, pll->config_reg, mask, val); 212 regmap_update_bits(regmap, pll->config_reg, mask, val);
213} 213}
214 214
215void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode)
217{
218 clk_pll_configure(pll, regmap, config);
219 if (fsm_mode)
220 clk_pll_set_fsm_mode(pll, regmap, 8);
221}
222EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
223
215void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, 224void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode) 225 const struct pll_config *config, bool fsm_mode)
217{ 226{
218 clk_pll_configure(pll, regmap, config); 227 clk_pll_configure(pll, regmap, config);
219 if (fsm_mode) 228 if (fsm_mode)
220 clk_pll_set_fsm_mode(pll, regmap); 229 clk_pll_set_fsm_mode(pll, regmap, 0);
221} 230}
222EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); 231EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index 0775a99ca768..3003e9962472 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -60,6 +60,8 @@ struct pll_config {
60 u32 aux_output_mask; 60 u32 aux_output_mask;
61}; 61};
62 62
63void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
64 const struct pll_config *config, bool fsm_mode);
63void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, 65void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
64 const struct pll_config *config, bool fsm_mode); 66 const struct pll_config *config, bool fsm_mode);
65 67
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index abfc2b675aea..b638c5846dbf 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -417,20 +417,25 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
417 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); 417 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
418} 418}
419 419
420static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate, 420static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long parent_rate) 421 unsigned long *p_rate, struct clk **p)
422{ 422{
423 struct clk_rcg *rcg = to_clk_rcg(hw); 423 struct clk_rcg *rcg = to_clk_rcg(hw);
424 const struct freq_tbl *f; 424 const struct freq_tbl *f = rcg->freq_tbl;
425
426 *p = clk_get_parent_by_index(hw->clk, f->src);
427 *p_rate = __clk_round_rate(*p, rate);
428
429 return *p_rate;
430}
431
432static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
433{
425 u32 ns, md, ctl; 434 u32 ns, md, ctl;
426 struct mn *mn = &rcg->mn; 435 struct mn *mn = &rcg->mn;
427 u32 mask = 0; 436 u32 mask = 0;
428 unsigned int reset_reg; 437 unsigned int reset_reg;
429 438
430 f = find_freq(rcg->freq_tbl, rate);
431 if (!f)
432 return -EINVAL;
433
434 if (rcg->mn.reset_in_cc) 439 if (rcg->mn.reset_in_cc)
435 reset_reg = rcg->clkr.enable_reg; 440 reset_reg = rcg->clkr.enable_reg;
436 else 441 else
@@ -466,6 +471,27 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
466 return 0; 471 return 0;
467} 472}
468 473
474static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
475 unsigned long parent_rate)
476{
477 struct clk_rcg *rcg = to_clk_rcg(hw);
478 const struct freq_tbl *f;
479
480 f = find_freq(rcg->freq_tbl, rate);
481 if (!f)
482 return -EINVAL;
483
484 return __clk_rcg_set_rate(rcg, f);
485}
486
487static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
488 unsigned long parent_rate)
489{
490 struct clk_rcg *rcg = to_clk_rcg(hw);
491
492 return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
493}
494
469static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate) 495static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
470{ 496{
471 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); 497 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
@@ -503,6 +529,17 @@ const struct clk_ops clk_rcg_ops = {
503}; 529};
504EXPORT_SYMBOL_GPL(clk_rcg_ops); 530EXPORT_SYMBOL_GPL(clk_rcg_ops);
505 531
532const struct clk_ops clk_rcg_bypass_ops = {
533 .enable = clk_enable_regmap,
534 .disable = clk_disable_regmap,
535 .get_parent = clk_rcg_get_parent,
536 .set_parent = clk_rcg_set_parent,
537 .recalc_rate = clk_rcg_recalc_rate,
538 .determine_rate = clk_rcg_bypass_determine_rate,
539 .set_rate = clk_rcg_bypass_set_rate,
540};
541EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
542
506const struct clk_ops clk_dyn_rcg_ops = { 543const struct clk_ops clk_dyn_rcg_ops = {
507 .enable = clk_enable_regmap, 544 .enable = clk_enable_regmap,
508 .is_enabled = clk_is_enabled_regmap, 545 .is_enabled = clk_is_enabled_regmap,
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index b9ec11dfd1b4..ba0523cefd2e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -95,6 +95,7 @@ struct clk_rcg {
95}; 95};
96 96
97extern const struct clk_ops clk_rcg_ops; 97extern const struct clk_ops clk_rcg_ops;
98extern const struct clk_ops clk_rcg_bypass_ops;
98 99
99#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) 100#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
100 101
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 9b5a1cfc6b91..eeb3eea01f4c 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -27,30 +27,35 @@ struct qcom_cc {
27 struct clk *clks[]; 27 struct clk *clks[];
28}; 28};
29 29
30int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) 30struct regmap *
31qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
31{ 32{
32 void __iomem *base; 33 void __iomem *base;
33 struct resource *res; 34 struct resource *res;
35 struct device *dev = &pdev->dev;
36
37 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
38 base = devm_ioremap_resource(dev, res);
39 if (IS_ERR(base))
40 return ERR_CAST(base);
41
42 return devm_regmap_init_mmio(dev, base, desc->config);
43}
44EXPORT_SYMBOL_GPL(qcom_cc_map);
45
46int qcom_cc_really_probe(struct platform_device *pdev,
47 const struct qcom_cc_desc *desc, struct regmap *regmap)
48{
34 int i, ret; 49 int i, ret;
35 struct device *dev = &pdev->dev; 50 struct device *dev = &pdev->dev;
36 struct clk *clk; 51 struct clk *clk;
37 struct clk_onecell_data *data; 52 struct clk_onecell_data *data;
38 struct clk **clks; 53 struct clk **clks;
39 struct regmap *regmap;
40 struct qcom_reset_controller *reset; 54 struct qcom_reset_controller *reset;
41 struct qcom_cc *cc; 55 struct qcom_cc *cc;
42 size_t num_clks = desc->num_clks; 56 size_t num_clks = desc->num_clks;
43 struct clk_regmap **rclks = desc->clks; 57 struct clk_regmap **rclks = desc->clks;
44 58
45 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
46 base = devm_ioremap_resource(dev, res);
47 if (IS_ERR(base))
48 return PTR_ERR(base);
49
50 regmap = devm_regmap_init_mmio(dev, base, desc->config);
51 if (IS_ERR(regmap))
52 return PTR_ERR(regmap);
53
54 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks, 59 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
55 GFP_KERNEL); 60 GFP_KERNEL);
56 if (!cc) 61 if (!cc)
@@ -91,6 +96,18 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
91 96
92 return ret; 97 return ret;
93} 98}
99EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
100
101int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
102{
103 struct regmap *regmap;
104
105 regmap = qcom_cc_map(pdev, desc);
106 if (IS_ERR(regmap))
107 return PTR_ERR(regmap);
108
109 return qcom_cc_really_probe(pdev, desc, regmap);
110}
94EXPORT_SYMBOL_GPL(qcom_cc_probe); 111EXPORT_SYMBOL_GPL(qcom_cc_probe);
95 112
96void qcom_cc_remove(struct platform_device *pdev) 113void qcom_cc_remove(struct platform_device *pdev)
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 2c3cfc860348..2765e9d3da97 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -17,6 +17,7 @@ struct platform_device;
17struct regmap_config; 17struct regmap_config;
18struct clk_regmap; 18struct clk_regmap;
19struct qcom_reset_map; 19struct qcom_reset_map;
20struct regmap;
20 21
21struct qcom_cc_desc { 22struct qcom_cc_desc {
22 const struct regmap_config *config; 23 const struct regmap_config *config;
@@ -26,6 +27,11 @@ struct qcom_cc_desc {
26 size_t num_resets; 27 size_t num_resets;
27}; 28};
28 29
30extern struct regmap *qcom_cc_map(struct platform_device *pdev,
31 const struct qcom_cc_desc *desc);
32extern int qcom_cc_really_probe(struct platform_device *pdev,
33 const struct qcom_cc_desc *desc,
34 struct regmap *regmap);
29extern int qcom_cc_probe(struct platform_device *pdev, 35extern int qcom_cc_probe(struct platform_device *pdev,
30 const struct qcom_cc_desc *desc); 36 const struct qcom_cc_desc *desc);
31 37
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
new file mode 100644
index 000000000000..ee52eb1c838a
--- /dev/null
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -0,0 +1,3611 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-apq8084.h>
26#include <dt-bindings/reset/qcom,gcc-apq8084.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35#define P_XO 0
36#define P_GPLL0 1
37#define P_GPLL1 1
38#define P_GPLL4 2
39#define P_PCIE_0_1_PIPE_CLK 1
40#define P_SATA_ASIC0_CLK 1
41#define P_SATA_RX_CLK 1
42#define P_SLEEP_CLK 1
43
44static const u8 gcc_xo_gpll0_map[] = {
45 [P_XO] = 0,
46 [P_GPLL0] = 1,
47};
48
49static const char *gcc_xo_gpll0[] = {
50 "xo",
51 "gpll0_vote",
52};
53
54static const u8 gcc_xo_gpll0_gpll4_map[] = {
55 [P_XO] = 0,
56 [P_GPLL0] = 1,
57 [P_GPLL4] = 5,
58};
59
60static const char *gcc_xo_gpll0_gpll4[] = {
61 "xo",
62 "gpll0_vote",
63 "gpll4_vote",
64};
65
66static const u8 gcc_xo_sata_asic0_map[] = {
67 [P_XO] = 0,
68 [P_SATA_ASIC0_CLK] = 2,
69};
70
71static const char *gcc_xo_sata_asic0[] = {
72 "xo",
73 "sata_asic0_clk",
74};
75
76static const u8 gcc_xo_sata_rx_map[] = {
77 [P_XO] = 0,
78 [P_SATA_RX_CLK] = 2,
79};
80
81static const char *gcc_xo_sata_rx[] = {
82 "xo",
83 "sata_rx_clk",
84};
85
86static const u8 gcc_xo_pcie_map[] = {
87 [P_XO] = 0,
88 [P_PCIE_0_1_PIPE_CLK] = 2,
89};
90
91static const char *gcc_xo_pcie[] = {
92 "xo",
93 "pcie_pipe",
94};
95
96static const u8 gcc_xo_pcie_sleep_map[] = {
97 [P_XO] = 0,
98 [P_SLEEP_CLK] = 6,
99};
100
101static const char *gcc_xo_pcie_sleep[] = {
102 "xo",
103 "sleep_clk_src",
104};
105
106#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
107
108static struct clk_pll gpll0 = {
109 .l_reg = 0x0004,
110 .m_reg = 0x0008,
111 .n_reg = 0x000c,
112 .config_reg = 0x0014,
113 .mode_reg = 0x0000,
114 .status_reg = 0x001c,
115 .status_bit = 17,
116 .clkr.hw.init = &(struct clk_init_data){
117 .name = "gpll0",
118 .parent_names = (const char *[]){ "xo" },
119 .num_parents = 1,
120 .ops = &clk_pll_ops,
121 },
122};
123
124static struct clk_regmap gpll0_vote = {
125 .enable_reg = 0x1480,
126 .enable_mask = BIT(0),
127 .hw.init = &(struct clk_init_data){
128 .name = "gpll0_vote",
129 .parent_names = (const char *[]){ "gpll0" },
130 .num_parents = 1,
131 .ops = &clk_pll_vote_ops,
132 },
133};
134
135static struct clk_rcg2 config_noc_clk_src = {
136 .cmd_rcgr = 0x0150,
137 .hid_width = 5,
138 .parent_map = gcc_xo_gpll0_map,
139 .clkr.hw.init = &(struct clk_init_data){
140 .name = "config_noc_clk_src",
141 .parent_names = gcc_xo_gpll0,
142 .num_parents = 2,
143 .ops = &clk_rcg2_ops,
144 },
145};
146
147static struct clk_rcg2 periph_noc_clk_src = {
148 .cmd_rcgr = 0x0190,
149 .hid_width = 5,
150 .parent_map = gcc_xo_gpll0_map,
151 .clkr.hw.init = &(struct clk_init_data){
152 .name = "periph_noc_clk_src",
153 .parent_names = gcc_xo_gpll0,
154 .num_parents = 2,
155 .ops = &clk_rcg2_ops,
156 },
157};
158
159static struct clk_rcg2 system_noc_clk_src = {
160 .cmd_rcgr = 0x0120,
161 .hid_width = 5,
162 .parent_map = gcc_xo_gpll0_map,
163 .clkr.hw.init = &(struct clk_init_data){
164 .name = "system_noc_clk_src",
165 .parent_names = gcc_xo_gpll0,
166 .num_parents = 2,
167 .ops = &clk_rcg2_ops,
168 },
169};
170
171static struct clk_pll gpll1 = {
172 .l_reg = 0x0044,
173 .m_reg = 0x0048,
174 .n_reg = 0x004c,
175 .config_reg = 0x0054,
176 .mode_reg = 0x0040,
177 .status_reg = 0x005c,
178 .status_bit = 17,
179 .clkr.hw.init = &(struct clk_init_data){
180 .name = "gpll1",
181 .parent_names = (const char *[]){ "xo" },
182 .num_parents = 1,
183 .ops = &clk_pll_ops,
184 },
185};
186
187static struct clk_regmap gpll1_vote = {
188 .enable_reg = 0x1480,
189 .enable_mask = BIT(1),
190 .hw.init = &(struct clk_init_data){
191 .name = "gpll1_vote",
192 .parent_names = (const char *[]){ "gpll1" },
193 .num_parents = 1,
194 .ops = &clk_pll_vote_ops,
195 },
196};
197
198static struct clk_pll gpll4 = {
199 .l_reg = 0x1dc4,
200 .m_reg = 0x1dc8,
201 .n_reg = 0x1dcc,
202 .config_reg = 0x1dd4,
203 .mode_reg = 0x1dc0,
204 .status_reg = 0x1ddc,
205 .status_bit = 17,
206 .clkr.hw.init = &(struct clk_init_data){
207 .name = "gpll4",
208 .parent_names = (const char *[]){ "xo" },
209 .num_parents = 1,
210 .ops = &clk_pll_ops,
211 },
212};
213
214static struct clk_regmap gpll4_vote = {
215 .enable_reg = 0x1480,
216 .enable_mask = BIT(4),
217 .hw.init = &(struct clk_init_data){
218 .name = "gpll4_vote",
219 .parent_names = (const char *[]){ "gpll4" },
220 .num_parents = 1,
221 .ops = &clk_pll_vote_ops,
222 },
223};
224
225static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
226 F(100000000, P_GPLL0, 6, 0, 0),
227 F(200000000, P_GPLL0, 3, 0, 0),
228 F(240000000, P_GPLL0, 2.5, 0, 0),
229 { }
230};
231
232static struct clk_rcg2 ufs_axi_clk_src = {
233 .cmd_rcgr = 0x1d64,
234 .mnd_width = 8,
235 .hid_width = 5,
236 .parent_map = gcc_xo_gpll0_map,
237 .freq_tbl = ftbl_gcc_ufs_axi_clk,
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "ufs_axi_clk_src",
240 .parent_names = gcc_xo_gpll0,
241 .num_parents = 2,
242 .ops = &clk_rcg2_ops,
243 },
244};
245
246static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
247 F(125000000, P_GPLL0, 1, 5, 24),
248 { }
249};
250
251static struct clk_rcg2 usb30_master_clk_src = {
252 .cmd_rcgr = 0x03d4,
253 .mnd_width = 8,
254 .hid_width = 5,
255 .parent_map = gcc_xo_gpll0_map,
256 .freq_tbl = ftbl_gcc_usb30_master_clk,
257 .clkr.hw.init = &(struct clk_init_data){
258 .name = "usb30_master_clk_src",
259 .parent_names = gcc_xo_gpll0,
260 .num_parents = 2,
261 .ops = &clk_rcg2_ops,
262 },
263};
264
265static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
266 F(125000000, P_GPLL0, 1, 5, 24),
267 { }
268};
269
270static struct clk_rcg2 usb30_sec_master_clk_src = {
271 .cmd_rcgr = 0x1bd4,
272 .mnd_width = 8,
273 .hid_width = 5,
274 .parent_map = gcc_xo_gpll0_map,
275 .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
276 .clkr.hw.init = &(struct clk_init_data){
277 .name = "usb30_sec_master_clk_src",
278 .parent_names = gcc_xo_gpll0,
279 .num_parents = 2,
280 .ops = &clk_rcg2_ops,
281 },
282};
283
284static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
285 .halt_reg = 0x1bd0,
286 .clkr = {
287 .enable_reg = 0x1bd0,
288 .enable_mask = BIT(0),
289 .hw.init = &(struct clk_init_data){
290 .name = "gcc_usb30_sec_mock_utmi_clk",
291 .parent_names = (const char *[]){
292 "usb30_sec_mock_utmi_clk_src",
293 },
294 .num_parents = 1,
295 .flags = CLK_SET_RATE_PARENT,
296 .ops = &clk_branch2_ops,
297 },
298 },
299};
300
301static struct clk_branch gcc_usb30_sec_sleep_clk = {
302 .halt_reg = 0x1bcc,
303 .clkr = {
304 .enable_reg = 0x1bcc,
305 .enable_mask = BIT(0),
306 .hw.init = &(struct clk_init_data){
307 .name = "gcc_usb30_sec_sleep_clk",
308 .parent_names = (const char *[]){
309 "sleep_clk_src",
310 },
311 .num_parents = 1,
312 .flags = CLK_SET_RATE_PARENT,
313 .ops = &clk_branch2_ops,
314 },
315 },
316};
317
318static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
319 F(19200000, P_XO, 1, 0, 0),
320 F(50000000, P_GPLL0, 12, 0, 0),
321 { }
322};
323
324static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
325 .cmd_rcgr = 0x0660,
326 .hid_width = 5,
327 .parent_map = gcc_xo_gpll0_map,
328 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "blsp1_qup1_i2c_apps_clk_src",
331 .parent_names = gcc_xo_gpll0,
332 .num_parents = 2,
333 .ops = &clk_rcg2_ops,
334 },
335};
336
337static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
338 F(960000, P_XO, 10, 1, 2),
339 F(4800000, P_XO, 4, 0, 0),
340 F(9600000, P_XO, 2, 0, 0),
341 F(15000000, P_GPLL0, 10, 1, 4),
342 F(19200000, P_XO, 1, 0, 0),
343 F(25000000, P_GPLL0, 12, 1, 2),
344 F(50000000, P_GPLL0, 12, 0, 0),
345 { }
346};
347
348static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
349 .cmd_rcgr = 0x064c,
350 .mnd_width = 8,
351 .hid_width = 5,
352 .parent_map = gcc_xo_gpll0_map,
353 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
354 .clkr.hw.init = &(struct clk_init_data){
355 .name = "blsp1_qup1_spi_apps_clk_src",
356 .parent_names = gcc_xo_gpll0,
357 .num_parents = 2,
358 .ops = &clk_rcg2_ops,
359 },
360};
361
362static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
363 .cmd_rcgr = 0x06e0,
364 .hid_width = 5,
365 .parent_map = gcc_xo_gpll0_map,
366 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
367 .clkr.hw.init = &(struct clk_init_data){
368 .name = "blsp1_qup2_i2c_apps_clk_src",
369 .parent_names = gcc_xo_gpll0,
370 .num_parents = 2,
371 .ops = &clk_rcg2_ops,
372 },
373};
374
375static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
376 .cmd_rcgr = 0x06cc,
377 .mnd_width = 8,
378 .hid_width = 5,
379 .parent_map = gcc_xo_gpll0_map,
380 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
381 .clkr.hw.init = &(struct clk_init_data){
382 .name = "blsp1_qup2_spi_apps_clk_src",
383 .parent_names = gcc_xo_gpll0,
384 .num_parents = 2,
385 .ops = &clk_rcg2_ops,
386 },
387};
388
389static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
390 .cmd_rcgr = 0x0760,
391 .hid_width = 5,
392 .parent_map = gcc_xo_gpll0_map,
393 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
394 .clkr.hw.init = &(struct clk_init_data){
395 .name = "blsp1_qup3_i2c_apps_clk_src",
396 .parent_names = gcc_xo_gpll0,
397 .num_parents = 2,
398 .ops = &clk_rcg2_ops,
399 },
400};
401
402static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
403 .cmd_rcgr = 0x074c,
404 .mnd_width = 8,
405 .hid_width = 5,
406 .parent_map = gcc_xo_gpll0_map,
407 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "blsp1_qup3_spi_apps_clk_src",
410 .parent_names = gcc_xo_gpll0,
411 .num_parents = 2,
412 .ops = &clk_rcg2_ops,
413 },
414};
415
416static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
417 .cmd_rcgr = 0x07e0,
418 .hid_width = 5,
419 .parent_map = gcc_xo_gpll0_map,
420 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "blsp1_qup4_i2c_apps_clk_src",
423 .parent_names = gcc_xo_gpll0,
424 .num_parents = 2,
425 .ops = &clk_rcg2_ops,
426 },
427};
428
429static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
430 .cmd_rcgr = 0x07cc,
431 .mnd_width = 8,
432 .hid_width = 5,
433 .parent_map = gcc_xo_gpll0_map,
434 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
435 .clkr.hw.init = &(struct clk_init_data){
436 .name = "blsp1_qup4_spi_apps_clk_src",
437 .parent_names = gcc_xo_gpll0,
438 .num_parents = 2,
439 .ops = &clk_rcg2_ops,
440 },
441};
442
443static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
444 .cmd_rcgr = 0x0860,
445 .hid_width = 5,
446 .parent_map = gcc_xo_gpll0_map,
447 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
448 .clkr.hw.init = &(struct clk_init_data){
449 .name = "blsp1_qup5_i2c_apps_clk_src",
450 .parent_names = gcc_xo_gpll0,
451 .num_parents = 2,
452 .ops = &clk_rcg2_ops,
453 },
454};
455
456static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
457 .cmd_rcgr = 0x084c,
458 .mnd_width = 8,
459 .hid_width = 5,
460 .parent_map = gcc_xo_gpll0_map,
461 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
462 .clkr.hw.init = &(struct clk_init_data){
463 .name = "blsp1_qup5_spi_apps_clk_src",
464 .parent_names = gcc_xo_gpll0,
465 .num_parents = 2,
466 .ops = &clk_rcg2_ops,
467 },
468};
469
470static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
471 .cmd_rcgr = 0x08e0,
472 .hid_width = 5,
473 .parent_map = gcc_xo_gpll0_map,
474 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "blsp1_qup6_i2c_apps_clk_src",
477 .parent_names = gcc_xo_gpll0,
478 .num_parents = 2,
479 .ops = &clk_rcg2_ops,
480 },
481};
482
483static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
484 .cmd_rcgr = 0x08cc,
485 .mnd_width = 8,
486 .hid_width = 5,
487 .parent_map = gcc_xo_gpll0_map,
488 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
489 .clkr.hw.init = &(struct clk_init_data){
490 .name = "blsp1_qup6_spi_apps_clk_src",
491 .parent_names = gcc_xo_gpll0,
492 .num_parents = 2,
493 .ops = &clk_rcg2_ops,
494 },
495};
496
497static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
498 F(3686400, P_GPLL0, 1, 96, 15625),
499 F(7372800, P_GPLL0, 1, 192, 15625),
500 F(14745600, P_GPLL0, 1, 384, 15625),
501 F(16000000, P_GPLL0, 5, 2, 15),
502 F(19200000, P_XO, 1, 0, 0),
503 F(24000000, P_GPLL0, 5, 1, 5),
504 F(32000000, P_GPLL0, 1, 4, 75),
505 F(40000000, P_GPLL0, 15, 0, 0),
506 F(46400000, P_GPLL0, 1, 29, 375),
507 F(48000000, P_GPLL0, 12.5, 0, 0),
508 F(51200000, P_GPLL0, 1, 32, 375),
509 F(56000000, P_GPLL0, 1, 7, 75),
510 F(58982400, P_GPLL0, 1, 1536, 15625),
511 F(60000000, P_GPLL0, 10, 0, 0),
512 F(63160000, P_GPLL0, 9.5, 0, 0),
513 { }
514};
515
516static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
517 .cmd_rcgr = 0x068c,
518 .mnd_width = 16,
519 .hid_width = 5,
520 .parent_map = gcc_xo_gpll0_map,
521 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
522 .clkr.hw.init = &(struct clk_init_data){
523 .name = "blsp1_uart1_apps_clk_src",
524 .parent_names = gcc_xo_gpll0,
525 .num_parents = 2,
526 .ops = &clk_rcg2_ops,
527 },
528};
529
530static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
531 .cmd_rcgr = 0x070c,
532 .mnd_width = 16,
533 .hid_width = 5,
534 .parent_map = gcc_xo_gpll0_map,
535 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
536 .clkr.hw.init = &(struct clk_init_data){
537 .name = "blsp1_uart2_apps_clk_src",
538 .parent_names = gcc_xo_gpll0,
539 .num_parents = 2,
540 .ops = &clk_rcg2_ops,
541 },
542};
543
544static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
545 .cmd_rcgr = 0x078c,
546 .mnd_width = 16,
547 .hid_width = 5,
548 .parent_map = gcc_xo_gpll0_map,
549 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "blsp1_uart3_apps_clk_src",
552 .parent_names = gcc_xo_gpll0,
553 .num_parents = 2,
554 .ops = &clk_rcg2_ops,
555 },
556};
557
558static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
559 .cmd_rcgr = 0x080c,
560 .mnd_width = 16,
561 .hid_width = 5,
562 .parent_map = gcc_xo_gpll0_map,
563 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "blsp1_uart4_apps_clk_src",
566 .parent_names = gcc_xo_gpll0,
567 .num_parents = 2,
568 .ops = &clk_rcg2_ops,
569 },
570};
571
572static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
573 .cmd_rcgr = 0x088c,
574 .mnd_width = 16,
575 .hid_width = 5,
576 .parent_map = gcc_xo_gpll0_map,
577 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "blsp1_uart5_apps_clk_src",
580 .parent_names = gcc_xo_gpll0,
581 .num_parents = 2,
582 .ops = &clk_rcg2_ops,
583 },
584};
585
586static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
587 .cmd_rcgr = 0x090c,
588 .mnd_width = 16,
589 .hid_width = 5,
590 .parent_map = gcc_xo_gpll0_map,
591 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "blsp1_uart6_apps_clk_src",
594 .parent_names = gcc_xo_gpll0,
595 .num_parents = 2,
596 .ops = &clk_rcg2_ops,
597 },
598};
599
600static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
601 .cmd_rcgr = 0x09a0,
602 .hid_width = 5,
603 .parent_map = gcc_xo_gpll0_map,
604 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
605 .clkr.hw.init = &(struct clk_init_data){
606 .name = "blsp2_qup1_i2c_apps_clk_src",
607 .parent_names = gcc_xo_gpll0,
608 .num_parents = 2,
609 .ops = &clk_rcg2_ops,
610 },
611};
612
613static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
614 .cmd_rcgr = 0x098c,
615 .mnd_width = 8,
616 .hid_width = 5,
617 .parent_map = gcc_xo_gpll0_map,
618 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "blsp2_qup1_spi_apps_clk_src",
621 .parent_names = gcc_xo_gpll0,
622 .num_parents = 2,
623 .ops = &clk_rcg2_ops,
624 },
625};
626
627static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
628 .cmd_rcgr = 0x0a20,
629 .hid_width = 5,
630 .parent_map = gcc_xo_gpll0_map,
631 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
632 .clkr.hw.init = &(struct clk_init_data){
633 .name = "blsp2_qup2_i2c_apps_clk_src",
634 .parent_names = gcc_xo_gpll0,
635 .num_parents = 2,
636 .ops = &clk_rcg2_ops,
637 },
638};
639
640static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
641 .cmd_rcgr = 0x0a0c,
642 .mnd_width = 8,
643 .hid_width = 5,
644 .parent_map = gcc_xo_gpll0_map,
645 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
646 .clkr.hw.init = &(struct clk_init_data){
647 .name = "blsp2_qup2_spi_apps_clk_src",
648 .parent_names = gcc_xo_gpll0,
649 .num_parents = 2,
650 .ops = &clk_rcg2_ops,
651 },
652};
653
654static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
655 .cmd_rcgr = 0x0aa0,
656 .hid_width = 5,
657 .parent_map = gcc_xo_gpll0_map,
658 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "blsp2_qup3_i2c_apps_clk_src",
661 .parent_names = gcc_xo_gpll0,
662 .num_parents = 2,
663 .ops = &clk_rcg2_ops,
664 },
665};
666
667static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
668 .cmd_rcgr = 0x0a8c,
669 .mnd_width = 8,
670 .hid_width = 5,
671 .parent_map = gcc_xo_gpll0_map,
672 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "blsp2_qup3_spi_apps_clk_src",
675 .parent_names = gcc_xo_gpll0,
676 .num_parents = 2,
677 .ops = &clk_rcg2_ops,
678 },
679};
680
681static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
682 .cmd_rcgr = 0x0b20,
683 .hid_width = 5,
684 .parent_map = gcc_xo_gpll0_map,
685 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
686 .clkr.hw.init = &(struct clk_init_data){
687 .name = "blsp2_qup4_i2c_apps_clk_src",
688 .parent_names = gcc_xo_gpll0,
689 .num_parents = 2,
690 .ops = &clk_rcg2_ops,
691 },
692};
693
694static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
695 .cmd_rcgr = 0x0b0c,
696 .mnd_width = 8,
697 .hid_width = 5,
698 .parent_map = gcc_xo_gpll0_map,
699 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "blsp2_qup4_spi_apps_clk_src",
702 .parent_names = gcc_xo_gpll0,
703 .num_parents = 2,
704 .ops = &clk_rcg2_ops,
705 },
706};
707
708static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
709 .cmd_rcgr = 0x0ba0,
710 .hid_width = 5,
711 .parent_map = gcc_xo_gpll0_map,
712 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
713 .clkr.hw.init = &(struct clk_init_data){
714 .name = "blsp2_qup5_i2c_apps_clk_src",
715 .parent_names = gcc_xo_gpll0,
716 .num_parents = 2,
717 .ops = &clk_rcg2_ops,
718 },
719};
720
721static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
722 .cmd_rcgr = 0x0b8c,
723 .mnd_width = 8,
724 .hid_width = 5,
725 .parent_map = gcc_xo_gpll0_map,
726 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "blsp2_qup5_spi_apps_clk_src",
729 .parent_names = gcc_xo_gpll0,
730 .num_parents = 2,
731 .ops = &clk_rcg2_ops,
732 },
733};
734
735static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
736 .cmd_rcgr = 0x0c20,
737 .hid_width = 5,
738 .parent_map = gcc_xo_gpll0_map,
739 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
740 .clkr.hw.init = &(struct clk_init_data){
741 .name = "blsp2_qup6_i2c_apps_clk_src",
742 .parent_names = gcc_xo_gpll0,
743 .num_parents = 2,
744 .ops = &clk_rcg2_ops,
745 },
746};
747
748static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
749 .cmd_rcgr = 0x0c0c,
750 .mnd_width = 8,
751 .hid_width = 5,
752 .parent_map = gcc_xo_gpll0_map,
753 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "blsp2_qup6_spi_apps_clk_src",
756 .parent_names = gcc_xo_gpll0,
757 .num_parents = 2,
758 .ops = &clk_rcg2_ops,
759 },
760};
761
762static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
763 .cmd_rcgr = 0x09cc,
764 .mnd_width = 16,
765 .hid_width = 5,
766 .parent_map = gcc_xo_gpll0_map,
767 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "blsp2_uart1_apps_clk_src",
770 .parent_names = gcc_xo_gpll0,
771 .num_parents = 2,
772 .ops = &clk_rcg2_ops,
773 },
774};
775
776static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
777 .cmd_rcgr = 0x0a4c,
778 .mnd_width = 16,
779 .hid_width = 5,
780 .parent_map = gcc_xo_gpll0_map,
781 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "blsp2_uart2_apps_clk_src",
784 .parent_names = gcc_xo_gpll0,
785 .num_parents = 2,
786 .ops = &clk_rcg2_ops,
787 },
788};
789
790static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
791 .cmd_rcgr = 0x0acc,
792 .mnd_width = 16,
793 .hid_width = 5,
794 .parent_map = gcc_xo_gpll0_map,
795 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "blsp2_uart3_apps_clk_src",
798 .parent_names = gcc_xo_gpll0,
799 .num_parents = 2,
800 .ops = &clk_rcg2_ops,
801 },
802};
803
804static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
805 .cmd_rcgr = 0x0b4c,
806 .mnd_width = 16,
807 .hid_width = 5,
808 .parent_map = gcc_xo_gpll0_map,
809 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
810 .clkr.hw.init = &(struct clk_init_data){
811 .name = "blsp2_uart4_apps_clk_src",
812 .parent_names = gcc_xo_gpll0,
813 .num_parents = 2,
814 .ops = &clk_rcg2_ops,
815 },
816};
817
818static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
819 .cmd_rcgr = 0x0bcc,
820 .mnd_width = 16,
821 .hid_width = 5,
822 .parent_map = gcc_xo_gpll0_map,
823 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
824 .clkr.hw.init = &(struct clk_init_data){
825 .name = "blsp2_uart5_apps_clk_src",
826 .parent_names = gcc_xo_gpll0,
827 .num_parents = 2,
828 .ops = &clk_rcg2_ops,
829 },
830};
831
832static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
833 .cmd_rcgr = 0x0c4c,
834 .mnd_width = 16,
835 .hid_width = 5,
836 .parent_map = gcc_xo_gpll0_map,
837 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
838 .clkr.hw.init = &(struct clk_init_data){
839 .name = "blsp2_uart6_apps_clk_src",
840 .parent_names = gcc_xo_gpll0,
841 .num_parents = 2,
842 .ops = &clk_rcg2_ops,
843 },
844};
845
846static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
847 F(50000000, P_GPLL0, 12, 0, 0),
848 F(85710000, P_GPLL0, 7, 0, 0),
849 F(100000000, P_GPLL0, 6, 0, 0),
850 F(171430000, P_GPLL0, 3.5, 0, 0),
851 { }
852};
853
854static struct clk_rcg2 ce1_clk_src = {
855 .cmd_rcgr = 0x1050,
856 .hid_width = 5,
857 .parent_map = gcc_xo_gpll0_map,
858 .freq_tbl = ftbl_gcc_ce1_clk,
859 .clkr.hw.init = &(struct clk_init_data){
860 .name = "ce1_clk_src",
861 .parent_names = gcc_xo_gpll0,
862 .num_parents = 2,
863 .ops = &clk_rcg2_ops,
864 },
865};
866
867static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
868 F(50000000, P_GPLL0, 12, 0, 0),
869 F(85710000, P_GPLL0, 7, 0, 0),
870 F(100000000, P_GPLL0, 6, 0, 0),
871 F(171430000, P_GPLL0, 3.5, 0, 0),
872 { }
873};
874
875static struct clk_rcg2 ce2_clk_src = {
876 .cmd_rcgr = 0x1090,
877 .hid_width = 5,
878 .parent_map = gcc_xo_gpll0_map,
879 .freq_tbl = ftbl_gcc_ce2_clk,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "ce2_clk_src",
882 .parent_names = gcc_xo_gpll0,
883 .num_parents = 2,
884 .ops = &clk_rcg2_ops,
885 },
886};
887
888static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
889 F(50000000, P_GPLL0, 12, 0, 0),
890 F(85710000, P_GPLL0, 7, 0, 0),
891 F(100000000, P_GPLL0, 6, 0, 0),
892 F(171430000, P_GPLL0, 3.5, 0, 0),
893 { }
894};
895
896static struct clk_rcg2 ce3_clk_src = {
897 .cmd_rcgr = 0x1d10,
898 .hid_width = 5,
899 .parent_map = gcc_xo_gpll0_map,
900 .freq_tbl = ftbl_gcc_ce3_clk,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "ce3_clk_src",
903 .parent_names = gcc_xo_gpll0,
904 .num_parents = 2,
905 .ops = &clk_rcg2_ops,
906 },
907};
908
909static const struct freq_tbl ftbl_gcc_gp_clk[] = {
910 F(19200000, P_XO, 1, 0, 0),
911 F(100000000, P_GPLL0, 6, 0, 0),
912 F(200000000, P_GPLL0, 3, 0, 0),
913 { }
914};
915
916static struct clk_rcg2 gp1_clk_src = {
917 .cmd_rcgr = 0x1904,
918 .mnd_width = 8,
919 .hid_width = 5,
920 .parent_map = gcc_xo_gpll0_map,
921 .freq_tbl = ftbl_gcc_gp_clk,
922 .clkr.hw.init = &(struct clk_init_data){
923 .name = "gp1_clk_src",
924 .parent_names = gcc_xo_gpll0,
925 .num_parents = 2,
926 .ops = &clk_rcg2_ops,
927 },
928};
929
930static struct clk_rcg2 gp2_clk_src = {
931 .cmd_rcgr = 0x1944,
932 .mnd_width = 8,
933 .hid_width = 5,
934 .parent_map = gcc_xo_gpll0_map,
935 .freq_tbl = ftbl_gcc_gp_clk,
936 .clkr.hw.init = &(struct clk_init_data){
937 .name = "gp2_clk_src",
938 .parent_names = gcc_xo_gpll0,
939 .num_parents = 2,
940 .ops = &clk_rcg2_ops,
941 },
942};
943
944static struct clk_rcg2 gp3_clk_src = {
945 .cmd_rcgr = 0x1984,
946 .mnd_width = 8,
947 .hid_width = 5,
948 .parent_map = gcc_xo_gpll0_map,
949 .freq_tbl = ftbl_gcc_gp_clk,
950 .clkr.hw.init = &(struct clk_init_data){
951 .name = "gp3_clk_src",
952 .parent_names = gcc_xo_gpll0,
953 .num_parents = 2,
954 .ops = &clk_rcg2_ops,
955 },
956};
957
958static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
959 F(1010000, P_XO, 1, 1, 19),
960 { }
961};
962
963static struct clk_rcg2 pcie_0_aux_clk_src = {
964 .cmd_rcgr = 0x1b2c,
965 .mnd_width = 16,
966 .hid_width = 5,
967 .parent_map = gcc_xo_pcie_sleep_map,
968 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "pcie_0_aux_clk_src",
971 .parent_names = gcc_xo_pcie_sleep,
972 .num_parents = 2,
973 .ops = &clk_rcg2_ops,
974 },
975};
976
977static struct clk_rcg2 pcie_1_aux_clk_src = {
978 .cmd_rcgr = 0x1bac,
979 .mnd_width = 16,
980 .hid_width = 5,
981 .parent_map = gcc_xo_pcie_sleep_map,
982 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
983 .clkr.hw.init = &(struct clk_init_data){
984 .name = "pcie_1_aux_clk_src",
985 .parent_names = gcc_xo_pcie_sleep,
986 .num_parents = 2,
987 .ops = &clk_rcg2_ops,
988 },
989};
990
991static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
992 F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
993 F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
994 { }
995};
996
997static struct clk_rcg2 pcie_0_pipe_clk_src = {
998 .cmd_rcgr = 0x1b18,
999 .hid_width = 5,
1000 .parent_map = gcc_xo_pcie_map,
1001 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1002 .clkr.hw.init = &(struct clk_init_data){
1003 .name = "pcie_0_pipe_clk_src",
1004 .parent_names = gcc_xo_pcie,
1005 .num_parents = 2,
1006 .ops = &clk_rcg2_ops,
1007 },
1008};
1009
1010static struct clk_rcg2 pcie_1_pipe_clk_src = {
1011 .cmd_rcgr = 0x1b98,
1012 .hid_width = 5,
1013 .parent_map = gcc_xo_pcie_map,
1014 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1015 .clkr.hw.init = &(struct clk_init_data){
1016 .name = "pcie_1_pipe_clk_src",
1017 .parent_names = gcc_xo_pcie,
1018 .num_parents = 2,
1019 .ops = &clk_rcg2_ops,
1020 },
1021};
1022
1023static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1024 F(60000000, P_GPLL0, 10, 0, 0),
1025 { }
1026};
1027
1028static struct clk_rcg2 pdm2_clk_src = {
1029 .cmd_rcgr = 0x0cd0,
1030 .hid_width = 5,
1031 .parent_map = gcc_xo_gpll0_map,
1032 .freq_tbl = ftbl_gcc_pdm2_clk,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "pdm2_clk_src",
1035 .parent_names = gcc_xo_gpll0,
1036 .num_parents = 2,
1037 .ops = &clk_rcg2_ops,
1038 },
1039};
1040
1041static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
1042 F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1043 F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1044 F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1045 { }
1046};
1047
1048static struct clk_rcg2 sata_asic0_clk_src = {
1049 .cmd_rcgr = 0x1c94,
1050 .hid_width = 5,
1051 .parent_map = gcc_xo_sata_asic0_map,
1052 .freq_tbl = ftbl_gcc_sata_asic0_clk,
1053 .clkr.hw.init = &(struct clk_init_data){
1054 .name = "sata_asic0_clk_src",
1055 .parent_names = gcc_xo_sata_asic0,
1056 .num_parents = 2,
1057 .ops = &clk_rcg2_ops,
1058 },
1059};
1060
1061static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
1062 F(19200000, P_XO, 1, 0, 0),
1063 F(50000000, P_GPLL0, 12, 0, 0),
1064 F(100000000, P_GPLL0, 6, 0, 0),
1065 { }
1066};
1067
1068static struct clk_rcg2 sata_pmalive_clk_src = {
1069 .cmd_rcgr = 0x1c80,
1070 .hid_width = 5,
1071 .parent_map = gcc_xo_gpll0_map,
1072 .freq_tbl = ftbl_gcc_sata_pmalive_clk,
1073 .clkr.hw.init = &(struct clk_init_data){
1074 .name = "sata_pmalive_clk_src",
1075 .parent_names = gcc_xo_gpll0,
1076 .num_parents = 2,
1077 .ops = &clk_rcg2_ops,
1078 },
1079};
1080
1081static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
1082 F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1083 F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1084 F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1085 { }
1086};
1087
1088static struct clk_rcg2 sata_rx_clk_src = {
1089 .cmd_rcgr = 0x1ca8,
1090 .hid_width = 5,
1091 .parent_map = gcc_xo_sata_rx_map,
1092 .freq_tbl = ftbl_gcc_sata_rx_clk,
1093 .clkr.hw.init = &(struct clk_init_data){
1094 .name = "sata_rx_clk_src",
1095 .parent_names = gcc_xo_sata_rx,
1096 .num_parents = 2,
1097 .ops = &clk_rcg2_ops,
1098 },
1099};
1100
1101static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
1102 F(100000000, P_GPLL0, 6, 0, 0),
1103 { }
1104};
1105
1106static struct clk_rcg2 sata_rx_oob_clk_src = {
1107 .cmd_rcgr = 0x1c5c,
1108 .hid_width = 5,
1109 .parent_map = gcc_xo_gpll0_map,
1110 .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
1111 .clkr.hw.init = &(struct clk_init_data){
1112 .name = "sata_rx_oob_clk_src",
1113 .parent_names = gcc_xo_gpll0,
1114 .num_parents = 2,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
1120 F(144000, P_XO, 16, 3, 25),
1121 F(400000, P_XO, 12, 1, 4),
1122 F(20000000, P_GPLL0, 15, 1, 2),
1123 F(25000000, P_GPLL0, 12, 1, 2),
1124 F(50000000, P_GPLL0, 12, 0, 0),
1125 F(100000000, P_GPLL0, 6, 0, 0),
1126 F(192000000, P_GPLL4, 4, 0, 0),
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(384000000, P_GPLL4, 2, 0, 0),
1129 { }
1130};
1131
1132static struct clk_rcg2 sdcc1_apps_clk_src = {
1133 .cmd_rcgr = 0x04d0,
1134 .mnd_width = 8,
1135 .hid_width = 5,
1136 .parent_map = gcc_xo_gpll0_gpll4_map,
1137 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1138 .clkr.hw.init = &(struct clk_init_data){
1139 .name = "sdcc1_apps_clk_src",
1140 .parent_names = gcc_xo_gpll0_gpll4,
1141 .num_parents = 3,
1142 .ops = &clk_rcg2_ops,
1143 },
1144};
1145
1146static struct clk_rcg2 sdcc2_apps_clk_src = {
1147 .cmd_rcgr = 0x0510,
1148 .mnd_width = 8,
1149 .hid_width = 5,
1150 .parent_map = gcc_xo_gpll0_map,
1151 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1152 .clkr.hw.init = &(struct clk_init_data){
1153 .name = "sdcc2_apps_clk_src",
1154 .parent_names = gcc_xo_gpll0,
1155 .num_parents = 2,
1156 .ops = &clk_rcg2_ops,
1157 },
1158};
1159
1160static struct clk_rcg2 sdcc3_apps_clk_src = {
1161 .cmd_rcgr = 0x0550,
1162 .mnd_width = 8,
1163 .hid_width = 5,
1164 .parent_map = gcc_xo_gpll0_map,
1165 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1166 .clkr.hw.init = &(struct clk_init_data){
1167 .name = "sdcc3_apps_clk_src",
1168 .parent_names = gcc_xo_gpll0,
1169 .num_parents = 2,
1170 .ops = &clk_rcg2_ops,
1171 },
1172};
1173
1174static struct clk_rcg2 sdcc4_apps_clk_src = {
1175 .cmd_rcgr = 0x0590,
1176 .mnd_width = 8,
1177 .hid_width = 5,
1178 .parent_map = gcc_xo_gpll0_map,
1179 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1180 .clkr.hw.init = &(struct clk_init_data){
1181 .name = "sdcc4_apps_clk_src",
1182 .parent_names = gcc_xo_gpll0,
1183 .num_parents = 2,
1184 .ops = &clk_rcg2_ops,
1185 },
1186};
1187
1188static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
1189 F(105000, P_XO, 2, 1, 91),
1190 { }
1191};
1192
1193static struct clk_rcg2 tsif_ref_clk_src = {
1194 .cmd_rcgr = 0x0d90,
1195 .mnd_width = 8,
1196 .hid_width = 5,
1197 .parent_map = gcc_xo_gpll0_map,
1198 .freq_tbl = ftbl_gcc_tsif_ref_clk,
1199 .clkr.hw.init = &(struct clk_init_data){
1200 .name = "tsif_ref_clk_src",
1201 .parent_names = gcc_xo_gpll0,
1202 .num_parents = 2,
1203 .ops = &clk_rcg2_ops,
1204 },
1205};
1206
1207static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1208 F(60000000, P_GPLL0, 10, 0, 0),
1209 { }
1210};
1211
1212static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1213 .cmd_rcgr = 0x03e8,
1214 .hid_width = 5,
1215 .parent_map = gcc_xo_gpll0_map,
1216 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1217 .clkr.hw.init = &(struct clk_init_data){
1218 .name = "usb30_mock_utmi_clk_src",
1219 .parent_names = gcc_xo_gpll0,
1220 .num_parents = 2,
1221 .ops = &clk_rcg2_ops,
1222 },
1223};
1224
1225static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1226 F(125000000, P_GPLL0, 1, 5, 24),
1227 { }
1228};
1229
1230static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1231 .cmd_rcgr = 0x1be8,
1232 .hid_width = 5,
1233 .parent_map = gcc_xo_gpll0_map,
1234 .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1235 .clkr.hw.init = &(struct clk_init_data){
1236 .name = "usb30_sec_mock_utmi_clk_src",
1237 .parent_names = gcc_xo_gpll0,
1238 .num_parents = 2,
1239 .ops = &clk_rcg2_ops,
1240 },
1241};
1242
1243static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1244 F(75000000, P_GPLL0, 8, 0, 0),
1245 { }
1246};
1247
1248static struct clk_rcg2 usb_hs_system_clk_src = {
1249 .cmd_rcgr = 0x0490,
1250 .hid_width = 5,
1251 .parent_map = gcc_xo_gpll0_map,
1252 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1253 .clkr.hw.init = &(struct clk_init_data){
1254 .name = "usb_hs_system_clk_src",
1255 .parent_names = gcc_xo_gpll0,
1256 .num_parents = 2,
1257 .ops = &clk_rcg2_ops,
1258 },
1259};
1260
1261static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1262 F(480000000, P_GPLL1, 1, 0, 0),
1263 { }
1264};
1265
1266static u8 usb_hsic_clk_src_map[] = {
1267 [P_XO] = 0,
1268 [P_GPLL1] = 4,
1269};
1270
1271static struct clk_rcg2 usb_hsic_clk_src = {
1272 .cmd_rcgr = 0x0440,
1273 .hid_width = 5,
1274 .parent_map = usb_hsic_clk_src_map,
1275 .freq_tbl = ftbl_gcc_usb_hsic_clk,
1276 .clkr.hw.init = &(struct clk_init_data){
1277 .name = "usb_hsic_clk_src",
1278 .parent_names = (const char *[]){
1279 "xo",
1280 "gpll1_vote",
1281 },
1282 .num_parents = 2,
1283 .ops = &clk_rcg2_ops,
1284 },
1285};
1286
1287static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1288 F(60000000, P_GPLL1, 8, 0, 0),
1289 { }
1290};
1291
1292static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1293 .cmd_rcgr = 0x046c,
1294 .mnd_width = 8,
1295 .hid_width = 5,
1296 .parent_map = usb_hsic_clk_src_map,
1297 .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1298 .clkr.hw.init = &(struct clk_init_data){
1299 .name = "usb_hsic_ahb_clk_src",
1300 .parent_names = (const char *[]){
1301 "xo",
1302 "gpll1_vote",
1303 },
1304 .num_parents = 2,
1305 .ops = &clk_rcg2_ops,
1306 },
1307};
1308
1309static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1310 F(9600000, P_XO, 2, 0, 0),
1311 { }
1312};
1313
1314static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1315 .cmd_rcgr = 0x0458,
1316 .hid_width = 5,
1317 .parent_map = gcc_xo_gpll0_map,
1318 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1319 .clkr.hw.init = &(struct clk_init_data){
1320 .name = "usb_hsic_io_cal_clk_src",
1321 .parent_names = gcc_xo_gpll0,
1322 .num_parents = 1,
1323 .ops = &clk_rcg2_ops,
1324 },
1325};
1326
1327static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1328 .halt_reg = 0x1f14,
1329 .clkr = {
1330 .enable_reg = 0x1f14,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "gcc_usb_hsic_mock_utmi_clk",
1334 .parent_names = (const char *[]){
1335 "usb_hsic_mock_utmi_clk_src",
1336 },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1345 F(60000000, P_GPLL0, 10, 0, 0),
1346 { }
1347};
1348
1349static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1350 .cmd_rcgr = 0x1f00,
1351 .hid_width = 5,
1352 .parent_map = gcc_xo_gpll0_map,
1353 .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1354 .clkr.hw.init = &(struct clk_init_data){
1355 .name = "usb_hsic_mock_utmi_clk_src",
1356 .parent_names = gcc_xo_gpll0,
1357 .num_parents = 1,
1358 .ops = &clk_rcg2_ops,
1359 },
1360};
1361
1362static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1363 F(75000000, P_GPLL0, 8, 0, 0),
1364 { }
1365};
1366
1367static struct clk_rcg2 usb_hsic_system_clk_src = {
1368 .cmd_rcgr = 0x041c,
1369 .hid_width = 5,
1370 .parent_map = gcc_xo_gpll0_map,
1371 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1372 .clkr.hw.init = &(struct clk_init_data){
1373 .name = "usb_hsic_system_clk_src",
1374 .parent_names = gcc_xo_gpll0,
1375 .num_parents = 2,
1376 .ops = &clk_rcg2_ops,
1377 },
1378};
1379
1380static struct clk_branch gcc_bam_dma_ahb_clk = {
1381 .halt_reg = 0x0d44,
1382 .halt_check = BRANCH_HALT_VOTED,
1383 .clkr = {
1384 .enable_reg = 0x1484,
1385 .enable_mask = BIT(12),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "gcc_bam_dma_ahb_clk",
1388 .parent_names = (const char *[]){
1389 "periph_noc_clk_src",
1390 },
1391 .num_parents = 1,
1392 .ops = &clk_branch2_ops,
1393 },
1394 },
1395};
1396
1397static struct clk_branch gcc_blsp1_ahb_clk = {
1398 .halt_reg = 0x05c4,
1399 .halt_check = BRANCH_HALT_VOTED,
1400 .clkr = {
1401 .enable_reg = 0x1484,
1402 .enable_mask = BIT(17),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gcc_blsp1_ahb_clk",
1405 .parent_names = (const char *[]){
1406 "periph_noc_clk_src",
1407 },
1408 .num_parents = 1,
1409 .ops = &clk_branch2_ops,
1410 },
1411 },
1412};
1413
1414static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1415 .halt_reg = 0x0648,
1416 .clkr = {
1417 .enable_reg = 0x0648,
1418 .enable_mask = BIT(0),
1419 .hw.init = &(struct clk_init_data){
1420 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1421 .parent_names = (const char *[]){
1422 "blsp1_qup1_i2c_apps_clk_src",
1423 },
1424 .num_parents = 1,
1425 .flags = CLK_SET_RATE_PARENT,
1426 .ops = &clk_branch2_ops,
1427 },
1428 },
1429};
1430
1431static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1432 .halt_reg = 0x0644,
1433 .clkr = {
1434 .enable_reg = 0x0644,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "gcc_blsp1_qup1_spi_apps_clk",
1438 .parent_names = (const char *[]){
1439 "blsp1_qup1_spi_apps_clk_src",
1440 },
1441 .num_parents = 1,
1442 .flags = CLK_SET_RATE_PARENT,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446};
1447
1448static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1449 .halt_reg = 0x06c8,
1450 .clkr = {
1451 .enable_reg = 0x06c8,
1452 .enable_mask = BIT(0),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1455 .parent_names = (const char *[]){
1456 "blsp1_qup2_i2c_apps_clk_src",
1457 },
1458 .num_parents = 1,
1459 .flags = CLK_SET_RATE_PARENT,
1460 .ops = &clk_branch2_ops,
1461 },
1462 },
1463};
1464
1465static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1466 .halt_reg = 0x06c4,
1467 .clkr = {
1468 .enable_reg = 0x06c4,
1469 .enable_mask = BIT(0),
1470 .hw.init = &(struct clk_init_data){
1471 .name = "gcc_blsp1_qup2_spi_apps_clk",
1472 .parent_names = (const char *[]){
1473 "blsp1_qup2_spi_apps_clk_src",
1474 },
1475 .num_parents = 1,
1476 .flags = CLK_SET_RATE_PARENT,
1477 .ops = &clk_branch2_ops,
1478 },
1479 },
1480};
1481
1482static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1483 .halt_reg = 0x0748,
1484 .clkr = {
1485 .enable_reg = 0x0748,
1486 .enable_mask = BIT(0),
1487 .hw.init = &(struct clk_init_data){
1488 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1489 .parent_names = (const char *[]){
1490 "blsp1_qup3_i2c_apps_clk_src",
1491 },
1492 .num_parents = 1,
1493 .flags = CLK_SET_RATE_PARENT,
1494 .ops = &clk_branch2_ops,
1495 },
1496 },
1497};
1498
1499static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1500 .halt_reg = 0x0744,
1501 .clkr = {
1502 .enable_reg = 0x0744,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "gcc_blsp1_qup3_spi_apps_clk",
1506 .parent_names = (const char *[]){
1507 "blsp1_qup3_spi_apps_clk_src",
1508 },
1509 .num_parents = 1,
1510 .flags = CLK_SET_RATE_PARENT,
1511 .ops = &clk_branch2_ops,
1512 },
1513 },
1514};
1515
1516static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1517 .halt_reg = 0x07c8,
1518 .clkr = {
1519 .enable_reg = 0x07c8,
1520 .enable_mask = BIT(0),
1521 .hw.init = &(struct clk_init_data){
1522 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1523 .parent_names = (const char *[]){
1524 "blsp1_qup4_i2c_apps_clk_src",
1525 },
1526 .num_parents = 1,
1527 .flags = CLK_SET_RATE_PARENT,
1528 .ops = &clk_branch2_ops,
1529 },
1530 },
1531};
1532
1533static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1534 .halt_reg = 0x07c4,
1535 .clkr = {
1536 .enable_reg = 0x07c4,
1537 .enable_mask = BIT(0),
1538 .hw.init = &(struct clk_init_data){
1539 .name = "gcc_blsp1_qup4_spi_apps_clk",
1540 .parent_names = (const char *[]){
1541 "blsp1_qup4_spi_apps_clk_src",
1542 },
1543 .num_parents = 1,
1544 .flags = CLK_SET_RATE_PARENT,
1545 .ops = &clk_branch2_ops,
1546 },
1547 },
1548};
1549
1550static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1551 .halt_reg = 0x0848,
1552 .clkr = {
1553 .enable_reg = 0x0848,
1554 .enable_mask = BIT(0),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1557 .parent_names = (const char *[]){
1558 "blsp1_qup5_i2c_apps_clk_src",
1559 },
1560 .num_parents = 1,
1561 .flags = CLK_SET_RATE_PARENT,
1562 .ops = &clk_branch2_ops,
1563 },
1564 },
1565};
1566
1567static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1568 .halt_reg = 0x0844,
1569 .clkr = {
1570 .enable_reg = 0x0844,
1571 .enable_mask = BIT(0),
1572 .hw.init = &(struct clk_init_data){
1573 .name = "gcc_blsp1_qup5_spi_apps_clk",
1574 .parent_names = (const char *[]){
1575 "blsp1_qup5_spi_apps_clk_src",
1576 },
1577 .num_parents = 1,
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1580 },
1581 },
1582};
1583
1584static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1585 .halt_reg = 0x08c8,
1586 .clkr = {
1587 .enable_reg = 0x08c8,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1591 .parent_names = (const char *[]){
1592 "blsp1_qup6_i2c_apps_clk_src",
1593 },
1594 .num_parents = 1,
1595 .flags = CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1597 },
1598 },
1599};
1600
1601static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1602 .halt_reg = 0x08c4,
1603 .clkr = {
1604 .enable_reg = 0x08c4,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "gcc_blsp1_qup6_spi_apps_clk",
1608 .parent_names = (const char *[]){
1609 "blsp1_qup6_spi_apps_clk_src",
1610 },
1611 .num_parents = 1,
1612 .flags = CLK_SET_RATE_PARENT,
1613 .ops = &clk_branch2_ops,
1614 },
1615 },
1616};
1617
1618static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1619 .halt_reg = 0x0684,
1620 .clkr = {
1621 .enable_reg = 0x0684,
1622 .enable_mask = BIT(0),
1623 .hw.init = &(struct clk_init_data){
1624 .name = "gcc_blsp1_uart1_apps_clk",
1625 .parent_names = (const char *[]){
1626 "blsp1_uart1_apps_clk_src",
1627 },
1628 .num_parents = 1,
1629 .flags = CLK_SET_RATE_PARENT,
1630 .ops = &clk_branch2_ops,
1631 },
1632 },
1633};
1634
1635static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1636 .halt_reg = 0x0704,
1637 .clkr = {
1638 .enable_reg = 0x0704,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "gcc_blsp1_uart2_apps_clk",
1642 .parent_names = (const char *[]){
1643 "blsp1_uart2_apps_clk_src",
1644 },
1645 .num_parents = 1,
1646 .flags = CLK_SET_RATE_PARENT,
1647 .ops = &clk_branch2_ops,
1648 },
1649 },
1650};
1651
1652static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1653 .halt_reg = 0x0784,
1654 .clkr = {
1655 .enable_reg = 0x0784,
1656 .enable_mask = BIT(0),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "gcc_blsp1_uart3_apps_clk",
1659 .parent_names = (const char *[]){
1660 "blsp1_uart3_apps_clk_src",
1661 },
1662 .num_parents = 1,
1663 .flags = CLK_SET_RATE_PARENT,
1664 .ops = &clk_branch2_ops,
1665 },
1666 },
1667};
1668
1669static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1670 .halt_reg = 0x0804,
1671 .clkr = {
1672 .enable_reg = 0x0804,
1673 .enable_mask = BIT(0),
1674 .hw.init = &(struct clk_init_data){
1675 .name = "gcc_blsp1_uart4_apps_clk",
1676 .parent_names = (const char *[]){
1677 "blsp1_uart4_apps_clk_src",
1678 },
1679 .num_parents = 1,
1680 .flags = CLK_SET_RATE_PARENT,
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684};
1685
1686static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1687 .halt_reg = 0x0884,
1688 .clkr = {
1689 .enable_reg = 0x0884,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "gcc_blsp1_uart5_apps_clk",
1693 .parent_names = (const char *[]){
1694 "blsp1_uart5_apps_clk_src",
1695 },
1696 .num_parents = 1,
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1699 },
1700 },
1701};
1702
1703static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1704 .halt_reg = 0x0904,
1705 .clkr = {
1706 .enable_reg = 0x0904,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(struct clk_init_data){
1709 .name = "gcc_blsp1_uart6_apps_clk",
1710 .parent_names = (const char *[]){
1711 "blsp1_uart6_apps_clk_src",
1712 },
1713 .num_parents = 1,
1714 .flags = CLK_SET_RATE_PARENT,
1715 .ops = &clk_branch2_ops,
1716 },
1717 },
1718};
1719
1720static struct clk_branch gcc_blsp2_ahb_clk = {
1721 .halt_reg = 0x0944,
1722 .halt_check = BRANCH_HALT_VOTED,
1723 .clkr = {
1724 .enable_reg = 0x1484,
1725 .enable_mask = BIT(15),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_blsp2_ahb_clk",
1728 .parent_names = (const char *[]){
1729 "periph_noc_clk_src",
1730 },
1731 .num_parents = 1,
1732 .ops = &clk_branch2_ops,
1733 },
1734 },
1735};
1736
1737static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1738 .halt_reg = 0x0988,
1739 .clkr = {
1740 .enable_reg = 0x0988,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1744 .parent_names = (const char *[]){
1745 "blsp2_qup1_i2c_apps_clk_src",
1746 },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1750 },
1751 },
1752};
1753
1754static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1755 .halt_reg = 0x0984,
1756 .clkr = {
1757 .enable_reg = 0x0984,
1758 .enable_mask = BIT(0),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "gcc_blsp2_qup1_spi_apps_clk",
1761 .parent_names = (const char *[]){
1762 "blsp2_qup1_spi_apps_clk_src",
1763 },
1764 .num_parents = 1,
1765 .flags = CLK_SET_RATE_PARENT,
1766 .ops = &clk_branch2_ops,
1767 },
1768 },
1769};
1770
1771static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1772 .halt_reg = 0x0a08,
1773 .clkr = {
1774 .enable_reg = 0x0a08,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1778 .parent_names = (const char *[]){
1779 "blsp2_qup2_i2c_apps_clk_src",
1780 },
1781 .num_parents = 1,
1782 .flags = CLK_SET_RATE_PARENT,
1783 .ops = &clk_branch2_ops,
1784 },
1785 },
1786};
1787
1788static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1789 .halt_reg = 0x0a04,
1790 .clkr = {
1791 .enable_reg = 0x0a04,
1792 .enable_mask = BIT(0),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "gcc_blsp2_qup2_spi_apps_clk",
1795 .parent_names = (const char *[]){
1796 "blsp2_qup2_spi_apps_clk_src",
1797 },
1798 .num_parents = 1,
1799 .flags = CLK_SET_RATE_PARENT,
1800 .ops = &clk_branch2_ops,
1801 },
1802 },
1803};
1804
1805static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1806 .halt_reg = 0x0a88,
1807 .clkr = {
1808 .enable_reg = 0x0a88,
1809 .enable_mask = BIT(0),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1812 .parent_names = (const char *[]){
1813 "blsp2_qup3_i2c_apps_clk_src",
1814 },
1815 .num_parents = 1,
1816 .flags = CLK_SET_RATE_PARENT,
1817 .ops = &clk_branch2_ops,
1818 },
1819 },
1820};
1821
1822static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1823 .halt_reg = 0x0a84,
1824 .clkr = {
1825 .enable_reg = 0x0a84,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "gcc_blsp2_qup3_spi_apps_clk",
1829 .parent_names = (const char *[]){
1830 "blsp2_qup3_spi_apps_clk_src",
1831 },
1832 .num_parents = 1,
1833 .flags = CLK_SET_RATE_PARENT,
1834 .ops = &clk_branch2_ops,
1835 },
1836 },
1837};
1838
1839static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1840 .halt_reg = 0x0b08,
1841 .clkr = {
1842 .enable_reg = 0x0b08,
1843 .enable_mask = BIT(0),
1844 .hw.init = &(struct clk_init_data){
1845 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1846 .parent_names = (const char *[]){
1847 "blsp2_qup4_i2c_apps_clk_src",
1848 },
1849 .num_parents = 1,
1850 .flags = CLK_SET_RATE_PARENT,
1851 .ops = &clk_branch2_ops,
1852 },
1853 },
1854};
1855
1856static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1857 .halt_reg = 0x0b04,
1858 .clkr = {
1859 .enable_reg = 0x0b04,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_blsp2_qup4_spi_apps_clk",
1863 .parent_names = (const char *[]){
1864 "blsp2_qup4_spi_apps_clk_src",
1865 },
1866 .num_parents = 1,
1867 .flags = CLK_SET_RATE_PARENT,
1868 .ops = &clk_branch2_ops,
1869 },
1870 },
1871};
1872
1873static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1874 .halt_reg = 0x0b88,
1875 .clkr = {
1876 .enable_reg = 0x0b88,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data){
1879 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1880 .parent_names = (const char *[]){
1881 "blsp2_qup5_i2c_apps_clk_src",
1882 },
1883 .num_parents = 1,
1884 .flags = CLK_SET_RATE_PARENT,
1885 .ops = &clk_branch2_ops,
1886 },
1887 },
1888};
1889
1890static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1891 .halt_reg = 0x0b84,
1892 .clkr = {
1893 .enable_reg = 0x0b84,
1894 .enable_mask = BIT(0),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "gcc_blsp2_qup5_spi_apps_clk",
1897 .parent_names = (const char *[]){
1898 "blsp2_qup5_spi_apps_clk_src",
1899 },
1900 .num_parents = 1,
1901 .flags = CLK_SET_RATE_PARENT,
1902 .ops = &clk_branch2_ops,
1903 },
1904 },
1905};
1906
1907static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1908 .halt_reg = 0x0c08,
1909 .clkr = {
1910 .enable_reg = 0x0c08,
1911 .enable_mask = BIT(0),
1912 .hw.init = &(struct clk_init_data){
1913 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1914 .parent_names = (const char *[]){
1915 "blsp2_qup6_i2c_apps_clk_src",
1916 },
1917 .num_parents = 1,
1918 .flags = CLK_SET_RATE_PARENT,
1919 .ops = &clk_branch2_ops,
1920 },
1921 },
1922};
1923
1924static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1925 .halt_reg = 0x0c04,
1926 .clkr = {
1927 .enable_reg = 0x0c04,
1928 .enable_mask = BIT(0),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "gcc_blsp2_qup6_spi_apps_clk",
1931 .parent_names = (const char *[]){
1932 "blsp2_qup6_spi_apps_clk_src",
1933 },
1934 .num_parents = 1,
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1937 },
1938 },
1939};
1940
1941static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1942 .halt_reg = 0x09c4,
1943 .clkr = {
1944 .enable_reg = 0x09c4,
1945 .enable_mask = BIT(0),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "gcc_blsp2_uart1_apps_clk",
1948 .parent_names = (const char *[]){
1949 "blsp2_uart1_apps_clk_src",
1950 },
1951 .num_parents = 1,
1952 .flags = CLK_SET_RATE_PARENT,
1953 .ops = &clk_branch2_ops,
1954 },
1955 },
1956};
1957
1958static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1959 .halt_reg = 0x0a44,
1960 .clkr = {
1961 .enable_reg = 0x0a44,
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "gcc_blsp2_uart2_apps_clk",
1965 .parent_names = (const char *[]){
1966 "blsp2_uart2_apps_clk_src",
1967 },
1968 .num_parents = 1,
1969 .flags = CLK_SET_RATE_PARENT,
1970 .ops = &clk_branch2_ops,
1971 },
1972 },
1973};
1974
1975static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1976 .halt_reg = 0x0ac4,
1977 .clkr = {
1978 .enable_reg = 0x0ac4,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "gcc_blsp2_uart3_apps_clk",
1982 .parent_names = (const char *[]){
1983 "blsp2_uart3_apps_clk_src",
1984 },
1985 .num_parents = 1,
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1988 },
1989 },
1990};
1991
1992static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1993 .halt_reg = 0x0b44,
1994 .clkr = {
1995 .enable_reg = 0x0b44,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "gcc_blsp2_uart4_apps_clk",
1999 .parent_names = (const char *[]){
2000 "blsp2_uart4_apps_clk_src",
2001 },
2002 .num_parents = 1,
2003 .flags = CLK_SET_RATE_PARENT,
2004 .ops = &clk_branch2_ops,
2005 },
2006 },
2007};
2008
2009static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2010 .halt_reg = 0x0bc4,
2011 .clkr = {
2012 .enable_reg = 0x0bc4,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "gcc_blsp2_uart5_apps_clk",
2016 .parent_names = (const char *[]){
2017 "blsp2_uart5_apps_clk_src",
2018 },
2019 .num_parents = 1,
2020 .flags = CLK_SET_RATE_PARENT,
2021 .ops = &clk_branch2_ops,
2022 },
2023 },
2024};
2025
2026static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2027 .halt_reg = 0x0c44,
2028 .clkr = {
2029 .enable_reg = 0x0c44,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_blsp2_uart6_apps_clk",
2033 .parent_names = (const char *[]){
2034 "blsp2_uart6_apps_clk_src",
2035 },
2036 .num_parents = 1,
2037 .flags = CLK_SET_RATE_PARENT,
2038 .ops = &clk_branch2_ops,
2039 },
2040 },
2041};
2042
2043static struct clk_branch gcc_boot_rom_ahb_clk = {
2044 .halt_reg = 0x0e04,
2045 .halt_check = BRANCH_HALT_VOTED,
2046 .clkr = {
2047 .enable_reg = 0x1484,
2048 .enable_mask = BIT(10),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "gcc_boot_rom_ahb_clk",
2051 .parent_names = (const char *[]){
2052 "config_noc_clk_src",
2053 },
2054 .num_parents = 1,
2055 .ops = &clk_branch2_ops,
2056 },
2057 },
2058};
2059
2060static struct clk_branch gcc_ce1_ahb_clk = {
2061 .halt_reg = 0x104c,
2062 .halt_check = BRANCH_HALT_VOTED,
2063 .clkr = {
2064 .enable_reg = 0x1484,
2065 .enable_mask = BIT(3),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "gcc_ce1_ahb_clk",
2068 .parent_names = (const char *[]){
2069 "config_noc_clk_src",
2070 },
2071 .num_parents = 1,
2072 .ops = &clk_branch2_ops,
2073 },
2074 },
2075};
2076
2077static struct clk_branch gcc_ce1_axi_clk = {
2078 .halt_reg = 0x1048,
2079 .halt_check = BRANCH_HALT_VOTED,
2080 .clkr = {
2081 .enable_reg = 0x1484,
2082 .enable_mask = BIT(4),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gcc_ce1_axi_clk",
2085 .parent_names = (const char *[]){
2086 "system_noc_clk_src",
2087 },
2088 .num_parents = 1,
2089 .ops = &clk_branch2_ops,
2090 },
2091 },
2092};
2093
2094static struct clk_branch gcc_ce1_clk = {
2095 .halt_reg = 0x1050,
2096 .halt_check = BRANCH_HALT_VOTED,
2097 .clkr = {
2098 .enable_reg = 0x1484,
2099 .enable_mask = BIT(5),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "gcc_ce1_clk",
2102 .parent_names = (const char *[]){
2103 "ce1_clk_src",
2104 },
2105 .num_parents = 1,
2106 .ops = &clk_branch2_ops,
2107 },
2108 },
2109};
2110
2111static struct clk_branch gcc_ce2_ahb_clk = {
2112 .halt_reg = 0x108c,
2113 .halt_check = BRANCH_HALT_VOTED,
2114 .clkr = {
2115 .enable_reg = 0x1484,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gcc_ce2_ahb_clk",
2119 .parent_names = (const char *[]){
2120 "config_noc_clk_src",
2121 },
2122 .num_parents = 1,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_ce2_axi_clk = {
2129 .halt_reg = 0x1088,
2130 .halt_check = BRANCH_HALT_VOTED,
2131 .clkr = {
2132 .enable_reg = 0x1484,
2133 .enable_mask = BIT(1),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_ce2_axi_clk",
2136 .parent_names = (const char *[]){
2137 "system_noc_clk_src",
2138 },
2139 .num_parents = 1,
2140 .ops = &clk_branch2_ops,
2141 },
2142 },
2143};
2144
2145static struct clk_branch gcc_ce2_clk = {
2146 .halt_reg = 0x1090,
2147 .halt_check = BRANCH_HALT_VOTED,
2148 .clkr = {
2149 .enable_reg = 0x1484,
2150 .enable_mask = BIT(2),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_ce2_clk",
2153 .parent_names = (const char *[]){
2154 "ce2_clk_src",
2155 },
2156 .num_parents = 1,
2157 .flags = CLK_SET_RATE_PARENT,
2158 .ops = &clk_branch2_ops,
2159 },
2160 },
2161};
2162
2163static struct clk_branch gcc_ce3_ahb_clk = {
2164 .halt_reg = 0x1d0c,
2165 .halt_check = BRANCH_HALT_VOTED,
2166 .clkr = {
2167 .enable_reg = 0x1d0c,
2168 .enable_mask = BIT(0),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "gcc_ce3_ahb_clk",
2171 .parent_names = (const char *[]){
2172 "config_noc_clk_src",
2173 },
2174 .num_parents = 1,
2175 .ops = &clk_branch2_ops,
2176 },
2177 },
2178};
2179
2180static struct clk_branch gcc_ce3_axi_clk = {
2181 .halt_reg = 0x1088,
2182 .halt_check = BRANCH_HALT_VOTED,
2183 .clkr = {
2184 .enable_reg = 0x1d08,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "gcc_ce3_axi_clk",
2188 .parent_names = (const char *[]){
2189 "system_noc_clk_src",
2190 },
2191 .num_parents = 1,
2192 .ops = &clk_branch2_ops,
2193 },
2194 },
2195};
2196
2197static struct clk_branch gcc_ce3_clk = {
2198 .halt_reg = 0x1090,
2199 .halt_check = BRANCH_HALT_VOTED,
2200 .clkr = {
2201 .enable_reg = 0x1d04,
2202 .enable_mask = BIT(0),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "gcc_ce3_clk",
2205 .parent_names = (const char *[]){
2206 "ce3_clk_src",
2207 },
2208 .num_parents = 1,
2209 .flags = CLK_SET_RATE_PARENT,
2210 .ops = &clk_branch2_ops,
2211 },
2212 },
2213};
2214
2215static struct clk_branch gcc_gp1_clk = {
2216 .halt_reg = 0x1900,
2217 .clkr = {
2218 .enable_reg = 0x1900,
2219 .enable_mask = BIT(0),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "gcc_gp1_clk",
2222 .parent_names = (const char *[]){
2223 "gp1_clk_src",
2224 },
2225 .num_parents = 1,
2226 .flags = CLK_SET_RATE_PARENT,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230};
2231
2232static struct clk_branch gcc_gp2_clk = {
2233 .halt_reg = 0x1940,
2234 .clkr = {
2235 .enable_reg = 0x1940,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_gp2_clk",
2239 .parent_names = (const char *[]){
2240 "gp2_clk_src",
2241 },
2242 .num_parents = 1,
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247};
2248
2249static struct clk_branch gcc_gp3_clk = {
2250 .halt_reg = 0x1980,
2251 .clkr = {
2252 .enable_reg = 0x1980,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_gp3_clk",
2256 .parent_names = (const char *[]){
2257 "gp3_clk_src",
2258 },
2259 .num_parents = 1,
2260 .flags = CLK_SET_RATE_PARENT,
2261 .ops = &clk_branch2_ops,
2262 },
2263 },
2264};
2265
2266static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2267 .halt_reg = 0x0248,
2268 .clkr = {
2269 .enable_reg = 0x0248,
2270 .enable_mask = BIT(0),
2271 .hw.init = &(struct clk_init_data){
2272 .name = "gcc_ocmem_noc_cfg_ahb_clk",
2273 .parent_names = (const char *[]){
2274 "config_noc_clk_src",
2275 },
2276 .num_parents = 1,
2277 .ops = &clk_branch2_ops,
2278 },
2279 },
2280};
2281
2282static struct clk_branch gcc_pcie_0_aux_clk = {
2283 .halt_reg = 0x1b10,
2284 .clkr = {
2285 .enable_reg = 0x1b10,
2286 .enable_mask = BIT(0),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_pcie_0_aux_clk",
2289 .parent_names = (const char *[]){
2290 "pcie_0_aux_clk_src",
2291 },
2292 .num_parents = 1,
2293 .flags = CLK_SET_RATE_PARENT,
2294 .ops = &clk_branch2_ops,
2295 },
2296 },
2297};
2298
2299static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2300 .halt_reg = 0x1b0c,
2301 .clkr = {
2302 .enable_reg = 0x1b0c,
2303 .enable_mask = BIT(0),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_pcie_0_cfg_ahb_clk",
2306 .parent_names = (const char *[]){
2307 "config_noc_clk_src",
2308 },
2309 .num_parents = 1,
2310 .flags = CLK_SET_RATE_PARENT,
2311 .ops = &clk_branch2_ops,
2312 },
2313 },
2314};
2315
2316static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2317 .halt_reg = 0x1b08,
2318 .clkr = {
2319 .enable_reg = 0x1b08,
2320 .enable_mask = BIT(0),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gcc_pcie_0_mstr_axi_clk",
2323 .parent_names = (const char *[]){
2324 "config_noc_clk_src",
2325 },
2326 .num_parents = 1,
2327 .flags = CLK_SET_RATE_PARENT,
2328 .ops = &clk_branch2_ops,
2329 },
2330 },
2331};
2332
2333static struct clk_branch gcc_pcie_0_pipe_clk = {
2334 .halt_reg = 0x1b14,
2335 .clkr = {
2336 .enable_reg = 0x1b14,
2337 .enable_mask = BIT(0),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gcc_pcie_0_pipe_clk",
2340 .parent_names = (const char *[]){
2341 "pcie_0_pipe_clk_src",
2342 },
2343 .num_parents = 1,
2344 .flags = CLK_SET_RATE_PARENT,
2345 .ops = &clk_branch2_ops,
2346 },
2347 },
2348};
2349
2350static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2351 .halt_reg = 0x1b04,
2352 .clkr = {
2353 .enable_reg = 0x1b04,
2354 .enable_mask = BIT(0),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_pcie_0_slv_axi_clk",
2357 .parent_names = (const char *[]){
2358 "config_noc_clk_src",
2359 },
2360 .num_parents = 1,
2361 .flags = CLK_SET_RATE_PARENT,
2362 .ops = &clk_branch2_ops,
2363 },
2364 },
2365};
2366
2367static struct clk_branch gcc_pcie_1_aux_clk = {
2368 .halt_reg = 0x1b90,
2369 .clkr = {
2370 .enable_reg = 0x1b90,
2371 .enable_mask = BIT(0),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_pcie_1_aux_clk",
2374 .parent_names = (const char *[]){
2375 "pcie_1_aux_clk_src",
2376 },
2377 .num_parents = 1,
2378 .flags = CLK_SET_RATE_PARENT,
2379 .ops = &clk_branch2_ops,
2380 },
2381 },
2382};
2383
2384static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2385 .halt_reg = 0x1b8c,
2386 .clkr = {
2387 .enable_reg = 0x1b8c,
2388 .enable_mask = BIT(0),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_pcie_1_cfg_ahb_clk",
2391 .parent_names = (const char *[]){
2392 "config_noc_clk_src",
2393 },
2394 .num_parents = 1,
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2397 },
2398 },
2399};
2400
2401static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2402 .halt_reg = 0x1b88,
2403 .clkr = {
2404 .enable_reg = 0x1b88,
2405 .enable_mask = BIT(0),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_pcie_1_mstr_axi_clk",
2408 .parent_names = (const char *[]){
2409 "config_noc_clk_src",
2410 },
2411 .num_parents = 1,
2412 .flags = CLK_SET_RATE_PARENT,
2413 .ops = &clk_branch2_ops,
2414 },
2415 },
2416};
2417
2418static struct clk_branch gcc_pcie_1_pipe_clk = {
2419 .halt_reg = 0x1b94,
2420 .clkr = {
2421 .enable_reg = 0x1b94,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_pcie_1_pipe_clk",
2425 .parent_names = (const char *[]){
2426 "pcie_1_pipe_clk_src",
2427 },
2428 .num_parents = 1,
2429 .flags = CLK_SET_RATE_PARENT,
2430 .ops = &clk_branch2_ops,
2431 },
2432 },
2433};
2434
2435static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2436 .halt_reg = 0x1b84,
2437 .clkr = {
2438 .enable_reg = 0x1b84,
2439 .enable_mask = BIT(0),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "gcc_pcie_1_slv_axi_clk",
2442 .parent_names = (const char *[]){
2443 "config_noc_clk_src",
2444 },
2445 .num_parents = 1,
2446 .flags = CLK_SET_RATE_PARENT,
2447 .ops = &clk_branch2_ops,
2448 },
2449 },
2450};
2451
2452static struct clk_branch gcc_pdm2_clk = {
2453 .halt_reg = 0x0ccc,
2454 .clkr = {
2455 .enable_reg = 0x0ccc,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_pdm2_clk",
2459 .parent_names = (const char *[]){
2460 "pdm2_clk_src",
2461 },
2462 .num_parents = 1,
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2465 },
2466 },
2467};
2468
2469static struct clk_branch gcc_pdm_ahb_clk = {
2470 .halt_reg = 0x0cc4,
2471 .clkr = {
2472 .enable_reg = 0x0cc4,
2473 .enable_mask = BIT(0),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "gcc_pdm_ahb_clk",
2476 .parent_names = (const char *[]){
2477 "periph_noc_clk_src",
2478 },
2479 .num_parents = 1,
2480 .ops = &clk_branch2_ops,
2481 },
2482 },
2483};
2484
2485static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2486 .halt_reg = 0x01a4,
2487 .clkr = {
2488 .enable_reg = 0x01a4,
2489 .enable_mask = BIT(0),
2490 .hw.init = &(struct clk_init_data){
2491 .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2492 .parent_names = (const char *[]){
2493 "usb_hsic_ahb_clk_src",
2494 },
2495 .num_parents = 1,
2496 .flags = CLK_SET_RATE_PARENT,
2497 .ops = &clk_branch2_ops,
2498 },
2499 },
2500};
2501
2502static struct clk_branch gcc_prng_ahb_clk = {
2503 .halt_reg = 0x0d04,
2504 .halt_check = BRANCH_HALT_VOTED,
2505 .clkr = {
2506 .enable_reg = 0x1484,
2507 .enable_mask = BIT(13),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "gcc_prng_ahb_clk",
2510 .parent_names = (const char *[]){
2511 "periph_noc_clk_src",
2512 },
2513 .num_parents = 1,
2514 .ops = &clk_branch2_ops,
2515 },
2516 },
2517};
2518
2519static struct clk_branch gcc_sata_asic0_clk = {
2520 .halt_reg = 0x1c54,
2521 .clkr = {
2522 .enable_reg = 0x1c54,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "gcc_sata_asic0_clk",
2526 .parent_names = (const char *[]){
2527 "sata_asic0_clk_src",
2528 },
2529 .num_parents = 1,
2530 .flags = CLK_SET_RATE_PARENT,
2531 .ops = &clk_branch2_ops,
2532 },
2533 },
2534};
2535
2536static struct clk_branch gcc_sata_axi_clk = {
2537 .halt_reg = 0x1c44,
2538 .clkr = {
2539 .enable_reg = 0x1c44,
2540 .enable_mask = BIT(0),
2541 .hw.init = &(struct clk_init_data){
2542 .name = "gcc_sata_axi_clk",
2543 .parent_names = (const char *[]){
2544 "config_noc_clk_src",
2545 },
2546 .num_parents = 1,
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2549 },
2550 },
2551};
2552
2553static struct clk_branch gcc_sata_cfg_ahb_clk = {
2554 .halt_reg = 0x1c48,
2555 .clkr = {
2556 .enable_reg = 0x1c48,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_sata_cfg_ahb_clk",
2560 .parent_names = (const char *[]){
2561 "config_noc_clk_src",
2562 },
2563 .num_parents = 1,
2564 .flags = CLK_SET_RATE_PARENT,
2565 .ops = &clk_branch2_ops,
2566 },
2567 },
2568};
2569
2570static struct clk_branch gcc_sata_pmalive_clk = {
2571 .halt_reg = 0x1c50,
2572 .clkr = {
2573 .enable_reg = 0x1c50,
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "gcc_sata_pmalive_clk",
2577 .parent_names = (const char *[]){
2578 "sata_pmalive_clk_src",
2579 },
2580 .num_parents = 1,
2581 .flags = CLK_SET_RATE_PARENT,
2582 .ops = &clk_branch2_ops,
2583 },
2584 },
2585};
2586
2587static struct clk_branch gcc_sata_rx_clk = {
2588 .halt_reg = 0x1c58,
2589 .clkr = {
2590 .enable_reg = 0x1c58,
2591 .enable_mask = BIT(0),
2592 .hw.init = &(struct clk_init_data){
2593 .name = "gcc_sata_rx_clk",
2594 .parent_names = (const char *[]){
2595 "sata_rx_clk_src",
2596 },
2597 .num_parents = 1,
2598 .flags = CLK_SET_RATE_PARENT,
2599 .ops = &clk_branch2_ops,
2600 },
2601 },
2602};
2603
2604static struct clk_branch gcc_sata_rx_oob_clk = {
2605 .halt_reg = 0x1c4c,
2606 .clkr = {
2607 .enable_reg = 0x1c4c,
2608 .enable_mask = BIT(0),
2609 .hw.init = &(struct clk_init_data){
2610 .name = "gcc_sata_rx_oob_clk",
2611 .parent_names = (const char *[]){
2612 "sata_rx_oob_clk_src",
2613 },
2614 .num_parents = 1,
2615 .flags = CLK_SET_RATE_PARENT,
2616 .ops = &clk_branch2_ops,
2617 },
2618 },
2619};
2620
2621static struct clk_branch gcc_sdcc1_ahb_clk = {
2622 .halt_reg = 0x04c8,
2623 .clkr = {
2624 .enable_reg = 0x04c8,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(struct clk_init_data){
2627 .name = "gcc_sdcc1_ahb_clk",
2628 .parent_names = (const char *[]){
2629 "periph_noc_clk_src",
2630 },
2631 .num_parents = 1,
2632 .ops = &clk_branch2_ops,
2633 },
2634 },
2635};
2636
2637static struct clk_branch gcc_sdcc1_apps_clk = {
2638 .halt_reg = 0x04c4,
2639 .clkr = {
2640 .enable_reg = 0x04c4,
2641 .enable_mask = BIT(0),
2642 .hw.init = &(struct clk_init_data){
2643 .name = "gcc_sdcc1_apps_clk",
2644 .parent_names = (const char *[]){
2645 "sdcc1_apps_clk_src",
2646 },
2647 .num_parents = 1,
2648 .flags = CLK_SET_RATE_PARENT,
2649 .ops = &clk_branch2_ops,
2650 },
2651 },
2652};
2653
2654static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2655 .halt_reg = 0x04e8,
2656 .clkr = {
2657 .enable_reg = 0x04e8,
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data){
2660 .name = "gcc_sdcc1_cdccal_ff_clk",
2661 .parent_names = (const char *[]){
2662 "xo"
2663 },
2664 .num_parents = 1,
2665 .ops = &clk_branch2_ops,
2666 },
2667 },
2668};
2669
2670static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2671 .halt_reg = 0x04e4,
2672 .clkr = {
2673 .enable_reg = 0x04e4,
2674 .enable_mask = BIT(0),
2675 .hw.init = &(struct clk_init_data){
2676 .name = "gcc_sdcc1_cdccal_sleep_clk",
2677 .parent_names = (const char *[]){
2678 "sleep_clk_src"
2679 },
2680 .num_parents = 1,
2681 .ops = &clk_branch2_ops,
2682 },
2683 },
2684};
2685
2686static struct clk_branch gcc_sdcc2_ahb_clk = {
2687 .halt_reg = 0x0508,
2688 .clkr = {
2689 .enable_reg = 0x0508,
2690 .enable_mask = BIT(0),
2691 .hw.init = &(struct clk_init_data){
2692 .name = "gcc_sdcc2_ahb_clk",
2693 .parent_names = (const char *[]){
2694 "periph_noc_clk_src",
2695 },
2696 .num_parents = 1,
2697 .ops = &clk_branch2_ops,
2698 },
2699 },
2700};
2701
2702static struct clk_branch gcc_sdcc2_apps_clk = {
2703 .halt_reg = 0x0504,
2704 .clkr = {
2705 .enable_reg = 0x0504,
2706 .enable_mask = BIT(0),
2707 .hw.init = &(struct clk_init_data){
2708 .name = "gcc_sdcc2_apps_clk",
2709 .parent_names = (const char *[]){
2710 "sdcc2_apps_clk_src",
2711 },
2712 .num_parents = 1,
2713 .flags = CLK_SET_RATE_PARENT,
2714 .ops = &clk_branch2_ops,
2715 },
2716 },
2717};
2718
2719static struct clk_branch gcc_sdcc3_ahb_clk = {
2720 .halt_reg = 0x0548,
2721 .clkr = {
2722 .enable_reg = 0x0548,
2723 .enable_mask = BIT(0),
2724 .hw.init = &(struct clk_init_data){
2725 .name = "gcc_sdcc3_ahb_clk",
2726 .parent_names = (const char *[]){
2727 "periph_noc_clk_src",
2728 },
2729 .num_parents = 1,
2730 .ops = &clk_branch2_ops,
2731 },
2732 },
2733};
2734
2735static struct clk_branch gcc_sdcc3_apps_clk = {
2736 .halt_reg = 0x0544,
2737 .clkr = {
2738 .enable_reg = 0x0544,
2739 .enable_mask = BIT(0),
2740 .hw.init = &(struct clk_init_data){
2741 .name = "gcc_sdcc3_apps_clk",
2742 .parent_names = (const char *[]){
2743 "sdcc3_apps_clk_src",
2744 },
2745 .num_parents = 1,
2746 .flags = CLK_SET_RATE_PARENT,
2747 .ops = &clk_branch2_ops,
2748 },
2749 },
2750};
2751
2752static struct clk_branch gcc_sdcc4_ahb_clk = {
2753 .halt_reg = 0x0588,
2754 .clkr = {
2755 .enable_reg = 0x0588,
2756 .enable_mask = BIT(0),
2757 .hw.init = &(struct clk_init_data){
2758 .name = "gcc_sdcc4_ahb_clk",
2759 .parent_names = (const char *[]){
2760 "periph_noc_clk_src",
2761 },
2762 .num_parents = 1,
2763 .ops = &clk_branch2_ops,
2764 },
2765 },
2766};
2767
2768static struct clk_branch gcc_sdcc4_apps_clk = {
2769 .halt_reg = 0x0584,
2770 .clkr = {
2771 .enable_reg = 0x0584,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_sdcc4_apps_clk",
2775 .parent_names = (const char *[]){
2776 "sdcc4_apps_clk_src",
2777 },
2778 .num_parents = 1,
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2781 },
2782 },
2783};
2784
2785static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2786 .halt_reg = 0x013c,
2787 .clkr = {
2788 .enable_reg = 0x013c,
2789 .enable_mask = BIT(0),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "gcc_sys_noc_ufs_axi_clk",
2792 .parent_names = (const char *[]){
2793 "ufs_axi_clk_src",
2794 },
2795 .num_parents = 1,
2796 .flags = CLK_SET_RATE_PARENT,
2797 .ops = &clk_branch2_ops,
2798 },
2799 },
2800};
2801
2802static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2803 .halt_reg = 0x0108,
2804 .clkr = {
2805 .enable_reg = 0x0108,
2806 .enable_mask = BIT(0),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "gcc_sys_noc_usb3_axi_clk",
2809 .parent_names = (const char *[]){
2810 "usb30_master_clk_src",
2811 },
2812 .num_parents = 1,
2813 .flags = CLK_SET_RATE_PARENT,
2814 .ops = &clk_branch2_ops,
2815 },
2816 },
2817};
2818
2819static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2820 .halt_reg = 0x0138,
2821 .clkr = {
2822 .enable_reg = 0x0138,
2823 .enable_mask = BIT(0),
2824 .hw.init = &(struct clk_init_data){
2825 .name = "gcc_sys_noc_usb3_sec_axi_clk",
2826 .parent_names = (const char *[]){
2827 "usb30_sec_master_clk_src",
2828 },
2829 .num_parents = 1,
2830 .flags = CLK_SET_RATE_PARENT,
2831 .ops = &clk_branch2_ops,
2832 },
2833 },
2834};
2835
2836static struct clk_branch gcc_tsif_ahb_clk = {
2837 .halt_reg = 0x0d84,
2838 .clkr = {
2839 .enable_reg = 0x0d84,
2840 .enable_mask = BIT(0),
2841 .hw.init = &(struct clk_init_data){
2842 .name = "gcc_tsif_ahb_clk",
2843 .parent_names = (const char *[]){
2844 "periph_noc_clk_src",
2845 },
2846 .num_parents = 1,
2847 .ops = &clk_branch2_ops,
2848 },
2849 },
2850};
2851
2852static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2853 .halt_reg = 0x0d8c,
2854 .clkr = {
2855 .enable_reg = 0x0d8c,
2856 .enable_mask = BIT(0),
2857 .hw.init = &(struct clk_init_data){
2858 .name = "gcc_tsif_inactivity_timers_clk",
2859 .parent_names = (const char *[]){
2860 "sleep_clk_src",
2861 },
2862 .num_parents = 1,
2863 .flags = CLK_SET_RATE_PARENT,
2864 .ops = &clk_branch2_ops,
2865 },
2866 },
2867};
2868
2869static struct clk_branch gcc_tsif_ref_clk = {
2870 .halt_reg = 0x0d88,
2871 .clkr = {
2872 .enable_reg = 0x0d88,
2873 .enable_mask = BIT(0),
2874 .hw.init = &(struct clk_init_data){
2875 .name = "gcc_tsif_ref_clk",
2876 .parent_names = (const char *[]){
2877 "tsif_ref_clk_src",
2878 },
2879 .num_parents = 1,
2880 .flags = CLK_SET_RATE_PARENT,
2881 .ops = &clk_branch2_ops,
2882 },
2883 },
2884};
2885
2886static struct clk_branch gcc_ufs_ahb_clk = {
2887 .halt_reg = 0x1d48,
2888 .clkr = {
2889 .enable_reg = 0x1d48,
2890 .enable_mask = BIT(0),
2891 .hw.init = &(struct clk_init_data){
2892 .name = "gcc_ufs_ahb_clk",
2893 .parent_names = (const char *[]){
2894 "config_noc_clk_src",
2895 },
2896 .num_parents = 1,
2897 .flags = CLK_SET_RATE_PARENT,
2898 .ops = &clk_branch2_ops,
2899 },
2900 },
2901};
2902
2903static struct clk_branch gcc_ufs_axi_clk = {
2904 .halt_reg = 0x1d44,
2905 .clkr = {
2906 .enable_reg = 0x1d44,
2907 .enable_mask = BIT(0),
2908 .hw.init = &(struct clk_init_data){
2909 .name = "gcc_ufs_axi_clk",
2910 .parent_names = (const char *[]){
2911 "ufs_axi_clk_src",
2912 },
2913 .num_parents = 1,
2914 .flags = CLK_SET_RATE_PARENT,
2915 .ops = &clk_branch2_ops,
2916 },
2917 },
2918};
2919
2920static struct clk_branch gcc_ufs_rx_cfg_clk = {
2921 .halt_reg = 0x1d50,
2922 .clkr = {
2923 .enable_reg = 0x1d50,
2924 .enable_mask = BIT(0),
2925 .hw.init = &(struct clk_init_data){
2926 .name = "gcc_ufs_rx_cfg_clk",
2927 .parent_names = (const char *[]){
2928 "ufs_axi_clk_src",
2929 },
2930 .num_parents = 1,
2931 .flags = CLK_SET_RATE_PARENT,
2932 .ops = &clk_branch2_ops,
2933 },
2934 },
2935};
2936
2937static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2938 .halt_reg = 0x1d5c,
2939 .clkr = {
2940 .enable_reg = 0x1d5c,
2941 .enable_mask = BIT(0),
2942 .hw.init = &(struct clk_init_data){
2943 .name = "gcc_ufs_rx_symbol_0_clk",
2944 .parent_names = (const char *[]){
2945 "ufs_rx_symbol_0_clk_src",
2946 },
2947 .num_parents = 1,
2948 .flags = CLK_SET_RATE_PARENT,
2949 .ops = &clk_branch2_ops,
2950 },
2951 },
2952};
2953
2954static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2955 .halt_reg = 0x1d60,
2956 .clkr = {
2957 .enable_reg = 0x1d60,
2958 .enable_mask = BIT(0),
2959 .hw.init = &(struct clk_init_data){
2960 .name = "gcc_ufs_rx_symbol_1_clk",
2961 .parent_names = (const char *[]){
2962 "ufs_rx_symbol_1_clk_src",
2963 },
2964 .num_parents = 1,
2965 .flags = CLK_SET_RATE_PARENT,
2966 .ops = &clk_branch2_ops,
2967 },
2968 },
2969};
2970
2971static struct clk_branch gcc_ufs_tx_cfg_clk = {
2972 .halt_reg = 0x1d4c,
2973 .clkr = {
2974 .enable_reg = 0x1d4c,
2975 .enable_mask = BIT(0),
2976 .hw.init = &(struct clk_init_data){
2977 .name = "gcc_ufs_tx_cfg_clk",
2978 .parent_names = (const char *[]){
2979 "ufs_axi_clk_src",
2980 },
2981 .num_parents = 1,
2982 .flags = CLK_SET_RATE_PARENT,
2983 .ops = &clk_branch2_ops,
2984 },
2985 },
2986};
2987
2988static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2989 .halt_reg = 0x1d54,
2990 .clkr = {
2991 .enable_reg = 0x1d54,
2992 .enable_mask = BIT(0),
2993 .hw.init = &(struct clk_init_data){
2994 .name = "gcc_ufs_tx_symbol_0_clk",
2995 .parent_names = (const char *[]){
2996 "ufs_tx_symbol_0_clk_src",
2997 },
2998 .num_parents = 1,
2999 .flags = CLK_SET_RATE_PARENT,
3000 .ops = &clk_branch2_ops,
3001 },
3002 },
3003};
3004
3005static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
3006 .halt_reg = 0x1d58,
3007 .clkr = {
3008 .enable_reg = 0x1d58,
3009 .enable_mask = BIT(0),
3010 .hw.init = &(struct clk_init_data){
3011 .name = "gcc_ufs_tx_symbol_1_clk",
3012 .parent_names = (const char *[]){
3013 "ufs_tx_symbol_1_clk_src",
3014 },
3015 .num_parents = 1,
3016 .flags = CLK_SET_RATE_PARENT,
3017 .ops = &clk_branch2_ops,
3018 },
3019 },
3020};
3021
3022static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3023 .halt_reg = 0x04ac,
3024 .clkr = {
3025 .enable_reg = 0x04ac,
3026 .enable_mask = BIT(0),
3027 .hw.init = &(struct clk_init_data){
3028 .name = "gcc_usb2a_phy_sleep_clk",
3029 .parent_names = (const char *[]){
3030 "sleep_clk_src",
3031 },
3032 .num_parents = 1,
3033 .ops = &clk_branch2_ops,
3034 },
3035 },
3036};
3037
3038static struct clk_branch gcc_usb2b_phy_sleep_clk = {
3039 .halt_reg = 0x04b4,
3040 .clkr = {
3041 .enable_reg = 0x04b4,
3042 .enable_mask = BIT(0),
3043 .hw.init = &(struct clk_init_data){
3044 .name = "gcc_usb2b_phy_sleep_clk",
3045 .parent_names = (const char *[]){
3046 "sleep_clk_src",
3047 },
3048 .num_parents = 1,
3049 .ops = &clk_branch2_ops,
3050 },
3051 },
3052};
3053
3054static struct clk_branch gcc_usb30_master_clk = {
3055 .halt_reg = 0x03c8,
3056 .clkr = {
3057 .enable_reg = 0x03c8,
3058 .enable_mask = BIT(0),
3059 .hw.init = &(struct clk_init_data){
3060 .name = "gcc_usb30_master_clk",
3061 .parent_names = (const char *[]){
3062 "usb30_master_clk_src",
3063 },
3064 .num_parents = 1,
3065 .flags = CLK_SET_RATE_PARENT,
3066 .ops = &clk_branch2_ops,
3067 },
3068 },
3069};
3070
3071static struct clk_branch gcc_usb30_sec_master_clk = {
3072 .halt_reg = 0x1bc8,
3073 .clkr = {
3074 .enable_reg = 0x1bc8,
3075 .enable_mask = BIT(0),
3076 .hw.init = &(struct clk_init_data){
3077 .name = "gcc_usb30_sec_master_clk",
3078 .parent_names = (const char *[]){
3079 "usb30_sec_master_clk_src",
3080 },
3081 .num_parents = 1,
3082 .flags = CLK_SET_RATE_PARENT,
3083 .ops = &clk_branch2_ops,
3084 },
3085 },
3086};
3087
3088static struct clk_branch gcc_usb30_mock_utmi_clk = {
3089 .halt_reg = 0x03d0,
3090 .clkr = {
3091 .enable_reg = 0x03d0,
3092 .enable_mask = BIT(0),
3093 .hw.init = &(struct clk_init_data){
3094 .name = "gcc_usb30_mock_utmi_clk",
3095 .parent_names = (const char *[]){
3096 "usb30_mock_utmi_clk_src",
3097 },
3098 .num_parents = 1,
3099 .flags = CLK_SET_RATE_PARENT,
3100 .ops = &clk_branch2_ops,
3101 },
3102 },
3103};
3104
3105static struct clk_branch gcc_usb30_sleep_clk = {
3106 .halt_reg = 0x03cc,
3107 .clkr = {
3108 .enable_reg = 0x03cc,
3109 .enable_mask = BIT(0),
3110 .hw.init = &(struct clk_init_data){
3111 .name = "gcc_usb30_sleep_clk",
3112 .parent_names = (const char *[]){
3113 "sleep_clk_src",
3114 },
3115 .num_parents = 1,
3116 .ops = &clk_branch2_ops,
3117 },
3118 },
3119};
3120
3121static struct clk_branch gcc_usb_hs_ahb_clk = {
3122 .halt_reg = 0x0488,
3123 .clkr = {
3124 .enable_reg = 0x0488,
3125 .enable_mask = BIT(0),
3126 .hw.init = &(struct clk_init_data){
3127 .name = "gcc_usb_hs_ahb_clk",
3128 .parent_names = (const char *[]){
3129 "periph_noc_clk_src",
3130 },
3131 .num_parents = 1,
3132 .ops = &clk_branch2_ops,
3133 },
3134 },
3135};
3136
3137static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
3138 .halt_reg = 0x048c,
3139 .clkr = {
3140 .enable_reg = 0x048c,
3141 .enable_mask = BIT(0),
3142 .hw.init = &(struct clk_init_data){
3143 .name = "gcc_usb_hs_inactivity_timers_clk",
3144 .parent_names = (const char *[]){
3145 "sleep_clk_src",
3146 },
3147 .num_parents = 1,
3148 .flags = CLK_SET_RATE_PARENT,
3149 .ops = &clk_branch2_ops,
3150 },
3151 },
3152};
3153
3154static struct clk_branch gcc_usb_hs_system_clk = {
3155 .halt_reg = 0x0484,
3156 .clkr = {
3157 .enable_reg = 0x0484,
3158 .enable_mask = BIT(0),
3159 .hw.init = &(struct clk_init_data){
3160 .name = "gcc_usb_hs_system_clk",
3161 .parent_names = (const char *[]){
3162 "usb_hs_system_clk_src",
3163 },
3164 .num_parents = 1,
3165 .flags = CLK_SET_RATE_PARENT,
3166 .ops = &clk_branch2_ops,
3167 },
3168 },
3169};
3170
3171static struct clk_branch gcc_usb_hsic_ahb_clk = {
3172 .halt_reg = 0x0408,
3173 .clkr = {
3174 .enable_reg = 0x0408,
3175 .enable_mask = BIT(0),
3176 .hw.init = &(struct clk_init_data){
3177 .name = "gcc_usb_hsic_ahb_clk",
3178 .parent_names = (const char *[]){
3179 "periph_noc_clk_src",
3180 },
3181 .num_parents = 1,
3182 .ops = &clk_branch2_ops,
3183 },
3184 },
3185};
3186
3187static struct clk_branch gcc_usb_hsic_clk = {
3188 .halt_reg = 0x0410,
3189 .clkr = {
3190 .enable_reg = 0x0410,
3191 .enable_mask = BIT(0),
3192 .hw.init = &(struct clk_init_data){
3193 .name = "gcc_usb_hsic_clk",
3194 .parent_names = (const char *[]){
3195 "usb_hsic_clk_src",
3196 },
3197 .num_parents = 1,
3198 .flags = CLK_SET_RATE_PARENT,
3199 .ops = &clk_branch2_ops,
3200 },
3201 },
3202};
3203
3204static struct clk_branch gcc_usb_hsic_io_cal_clk = {
3205 .halt_reg = 0x0414,
3206 .clkr = {
3207 .enable_reg = 0x0414,
3208 .enable_mask = BIT(0),
3209 .hw.init = &(struct clk_init_data){
3210 .name = "gcc_usb_hsic_io_cal_clk",
3211 .parent_names = (const char *[]){
3212 "usb_hsic_io_cal_clk_src",
3213 },
3214 .num_parents = 1,
3215 .flags = CLK_SET_RATE_PARENT,
3216 .ops = &clk_branch2_ops,
3217 },
3218 },
3219};
3220
3221static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
3222 .halt_reg = 0x0418,
3223 .clkr = {
3224 .enable_reg = 0x0418,
3225 .enable_mask = BIT(0),
3226 .hw.init = &(struct clk_init_data){
3227 .name = "gcc_usb_hsic_io_cal_sleep_clk",
3228 .parent_names = (const char *[]){
3229 "sleep_clk_src",
3230 },
3231 .num_parents = 1,
3232 .ops = &clk_branch2_ops,
3233 },
3234 },
3235};
3236
3237static struct clk_branch gcc_usb_hsic_system_clk = {
3238 .halt_reg = 0x040c,
3239 .clkr = {
3240 .enable_reg = 0x040c,
3241 .enable_mask = BIT(0),
3242 .hw.init = &(struct clk_init_data){
3243 .name = "gcc_usb_hsic_system_clk",
3244 .parent_names = (const char *[]){
3245 "usb_hsic_system_clk_src",
3246 },
3247 .num_parents = 1,
3248 .flags = CLK_SET_RATE_PARENT,
3249 .ops = &clk_branch2_ops,
3250 },
3251 },
3252};
3253
3254static struct clk_regmap *gcc_apq8084_clocks[] = {
3255 [GPLL0] = &gpll0.clkr,
3256 [GPLL0_VOTE] = &gpll0_vote,
3257 [GPLL1] = &gpll1.clkr,
3258 [GPLL1_VOTE] = &gpll1_vote,
3259 [GPLL4] = &gpll4.clkr,
3260 [GPLL4_VOTE] = &gpll4_vote,
3261 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3262 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3263 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3264 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3265 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3266 [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
3267 [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
3268 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3269 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3270 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3271 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3272 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3273 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3274 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3275 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3276 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3277 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3278 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3279 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3280 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3281 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3282 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3283 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3284 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3285 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3286 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3287 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3288 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3289 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3290 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3291 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3292 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3293 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3294 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3295 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3296 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3297 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3298 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3299 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3300 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3301 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3302 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3303 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3304 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
3305 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
3306 [CE3_CLK_SRC] = &ce3_clk_src.clkr,
3307 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3308 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3309 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3310 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
3311 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
3312 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
3313 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
3314 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3315 [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
3316 [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
3317 [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
3318 [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
3319 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3320 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3321 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3322 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3323 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3324 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3325 [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
3326 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3327 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
3328 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
3329 [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
3330 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
3331 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
3332 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3333 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3334 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3335 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3336 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3337 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3338 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3339 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3340 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3341 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3342 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3343 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3344 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3345 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3346 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3347 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3348 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3349 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3350 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3351 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3352 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3353 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3354 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3355 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3356 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3357 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3358 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3359 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3360 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3361 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3362 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3363 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3364 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3365 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3366 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3367 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3368 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3369 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3370 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3371 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3372 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3373 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3374 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
3375 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
3376 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
3377 [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
3378 [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
3379 [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
3380 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3381 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3382 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3383 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
3384 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3385 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3386 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3387 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3388 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3389 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3390 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3391 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3392 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3393 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3394 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3395 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3396 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
3397 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3398 [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
3399 [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
3400 [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
3401 [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
3402 [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
3403 [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
3404 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3405 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3406 [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
3407 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
3408 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3409 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3410 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3411 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3412 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3413 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3414 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3415 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3416 [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
3417 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3418 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3419 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3420 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3421 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3422 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3423 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3424 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3425 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3426 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3427 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
3428 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3429 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
3430 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3431 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3432 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3433 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3434 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3435 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3436 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3437 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
3438 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3439 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
3440 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
3441 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
3442 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
3443 [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
3444 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
3445};
3446
3447static const struct qcom_reset_map gcc_apq8084_resets[] = {
3448 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3449 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3450 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3451 [GCC_IMEM_BCR] = { 0x0200 },
3452 [GCC_MMSS_BCR] = { 0x0240 },
3453 [GCC_QDSS_BCR] = { 0x0300 },
3454 [GCC_USB_30_BCR] = { 0x03c0 },
3455 [GCC_USB3_PHY_BCR] = { 0x03fc },
3456 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3457 [GCC_USB_HS_BCR] = { 0x0480 },
3458 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3459 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3460 [GCC_SDCC1_BCR] = { 0x04c0 },
3461 [GCC_SDCC2_BCR] = { 0x0500 },
3462 [GCC_SDCC3_BCR] = { 0x0540 },
3463 [GCC_SDCC4_BCR] = { 0x0580 },
3464 [GCC_BLSP1_BCR] = { 0x05c0 },
3465 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3466 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3467 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3468 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3469 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3470 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3471 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3472 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3473 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3474 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3475 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3476 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3477 [GCC_BLSP2_BCR] = { 0x0940 },
3478 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3479 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3480 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3481 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3482 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3483 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3484 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3485 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3486 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3487 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3488 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3489 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3490 [GCC_PDM_BCR] = { 0x0cc0 },
3491 [GCC_PRNG_BCR] = { 0x0d00 },
3492 [GCC_BAM_DMA_BCR] = { 0x0d40 },
3493 [GCC_TSIF_BCR] = { 0x0d80 },
3494 [GCC_TCSR_BCR] = { 0x0dc0 },
3495 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3496 [GCC_MSG_RAM_BCR] = { 0x0e40 },
3497 [GCC_TLMM_BCR] = { 0x0e80 },
3498 [GCC_MPM_BCR] = { 0x0ec0 },
3499 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3500 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3501 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3502 [GCC_SPMI_BCR] = { 0x0fc0 },
3503 [GCC_SPDM_BCR] = { 0x1000 },
3504 [GCC_CE1_BCR] = { 0x1040 },
3505 [GCC_CE2_BCR] = { 0x1080 },
3506 [GCC_BIMC_BCR] = { 0x1100 },
3507 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3508 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3509 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3510 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3511 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3512 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3513 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3514 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3515 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3516 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3517 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3518 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3519 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3520 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3521 [GCC_DEHR_BCR] = { 0x1300 },
3522 [GCC_RBCPR_BCR] = { 0x1380 },
3523 [GCC_MSS_RESTART] = { 0x1680 },
3524 [GCC_LPASS_RESTART] = { 0x16c0 },
3525 [GCC_WCSS_RESTART] = { 0x1700 },
3526 [GCC_VENUS_RESTART] = { 0x1740 },
3527 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3528 [GCC_SPSS_BCR] = { 0x1a80 },
3529 [GCC_PCIE_0_BCR] = { 0x1ac0 },
3530 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3531 [GCC_PCIE_1_BCR] = { 0x1b40 },
3532 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3533 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3534 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3535 [GCC_SATA_BCR] = { 0x1c40 },
3536 [GCC_CE3_BCR] = { 0x1d00 },
3537 [GCC_UFS_BCR] = { 0x1d40 },
3538 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3539};
3540
3541static const struct regmap_config gcc_apq8084_regmap_config = {
3542 .reg_bits = 32,
3543 .reg_stride = 4,
3544 .val_bits = 32,
3545 .max_register = 0x1fc0,
3546 .fast_io = true,
3547};
3548
3549static const struct qcom_cc_desc gcc_apq8084_desc = {
3550 .config = &gcc_apq8084_regmap_config,
3551 .clks = gcc_apq8084_clocks,
3552 .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
3553 .resets = gcc_apq8084_resets,
3554 .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
3555};
3556
3557static const struct of_device_id gcc_apq8084_match_table[] = {
3558 { .compatible = "qcom,gcc-apq8084" },
3559 { }
3560};
3561MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3562
3563static int gcc_apq8084_probe(struct platform_device *pdev)
3564{
3565 struct clk *clk;
3566 struct device *dev = &pdev->dev;
3567
3568 /* Temporary until RPM clocks supported */
3569 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
3570 if (IS_ERR(clk))
3571 return PTR_ERR(clk);
3572
3573 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
3574 CLK_IS_ROOT, 32768);
3575 if (IS_ERR(clk))
3576 return PTR_ERR(clk);
3577
3578 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3579}
3580
3581static int gcc_apq8084_remove(struct platform_device *pdev)
3582{
3583 qcom_cc_remove(pdev);
3584 return 0;
3585}
3586
3587static struct platform_driver gcc_apq8084_driver = {
3588 .probe = gcc_apq8084_probe,
3589 .remove = gcc_apq8084_remove,
3590 .driver = {
3591 .name = "gcc-apq8084",
3592 .owner = THIS_MODULE,
3593 .of_match_table = gcc_apq8084_match_table,
3594 },
3595};
3596
3597static int __init gcc_apq8084_init(void)
3598{
3599 return platform_driver_register(&gcc_apq8084_driver);
3600}
3601core_initcall(gcc_apq8084_init);
3602
3603static void __exit gcc_apq8084_exit(void)
3604{
3605 platform_driver_unregister(&gcc_apq8084_driver);
3606}
3607module_exit(gcc_apq8084_exit);
3608
3609MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3610MODULE_LICENSE("GPL v2");
3611MODULE_ALIAS("platform:gcc-apq8084");
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
new file mode 100644
index 000000000000..4032e510d9aa
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -0,0 +1,2424 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35static struct clk_pll pll3 = {
36 .l_reg = 0x3164,
37 .m_reg = 0x3168,
38 .n_reg = 0x316c,
39 .config_reg = 0x3174,
40 .mode_reg = 0x3160,
41 .status_reg = 0x3178,
42 .status_bit = 16,
43 .clkr.hw.init = &(struct clk_init_data){
44 .name = "pll3",
45 .parent_names = (const char *[]){ "pxo" },
46 .num_parents = 1,
47 .ops = &clk_pll_ops,
48 },
49};
50
51static struct clk_pll pll8 = {
52 .l_reg = 0x3144,
53 .m_reg = 0x3148,
54 .n_reg = 0x314c,
55 .config_reg = 0x3154,
56 .mode_reg = 0x3140,
57 .status_reg = 0x3158,
58 .status_bit = 16,
59 .clkr.hw.init = &(struct clk_init_data){
60 .name = "pll8",
61 .parent_names = (const char *[]){ "pxo" },
62 .num_parents = 1,
63 .ops = &clk_pll_ops,
64 },
65};
66
67static struct clk_regmap pll8_vote = {
68 .enable_reg = 0x34c0,
69 .enable_mask = BIT(8),
70 .hw.init = &(struct clk_init_data){
71 .name = "pll8_vote",
72 .parent_names = (const char *[]){ "pll8" },
73 .num_parents = 1,
74 .ops = &clk_pll_vote_ops,
75 },
76};
77
78static struct clk_pll pll14 = {
79 .l_reg = 0x31c4,
80 .m_reg = 0x31c8,
81 .n_reg = 0x31cc,
82 .config_reg = 0x31d4,
83 .mode_reg = 0x31c0,
84 .status_reg = 0x31d8,
85 .status_bit = 16,
86 .clkr.hw.init = &(struct clk_init_data){
87 .name = "pll14",
88 .parent_names = (const char *[]){ "pxo" },
89 .num_parents = 1,
90 .ops = &clk_pll_ops,
91 },
92};
93
94static struct clk_regmap pll14_vote = {
95 .enable_reg = 0x34c0,
96 .enable_mask = BIT(14),
97 .hw.init = &(struct clk_init_data){
98 .name = "pll14_vote",
99 .parent_names = (const char *[]){ "pll14" },
100 .num_parents = 1,
101 .ops = &clk_pll_vote_ops,
102 },
103};
104
105#define P_PXO 0
106#define P_PLL8 1
107#define P_PLL3 1
108#define P_PLL0 2
109#define P_CXO 2
110
111static const u8 gcc_pxo_pll8_map[] = {
112 [P_PXO] = 0,
113 [P_PLL8] = 3,
114};
115
116static const char *gcc_pxo_pll8[] = {
117 "pxo",
118 "pll8_vote",
119};
120
121static const u8 gcc_pxo_pll8_cxo_map[] = {
122 [P_PXO] = 0,
123 [P_PLL8] = 3,
124 [P_CXO] = 5,
125};
126
127static const char *gcc_pxo_pll8_cxo[] = {
128 "pxo",
129 "pll8_vote",
130 "cxo",
131};
132
133static const u8 gcc_pxo_pll3_map[] = {
134 [P_PXO] = 0,
135 [P_PLL3] = 1,
136};
137
138static const u8 gcc_pxo_pll3_sata_map[] = {
139 [P_PXO] = 0,
140 [P_PLL3] = 6,
141};
142
143static const char *gcc_pxo_pll3[] = {
144 "pxo",
145 "pll3",
146};
147
148static const u8 gcc_pxo_pll8_pll0[] = {
149 [P_PXO] = 0,
150 [P_PLL8] = 3,
151 [P_PLL0] = 2,
152};
153
154static const char *gcc_pxo_pll8_pll0_map[] = {
155 "pxo",
156 "pll8_vote",
157 "pll0",
158};
159
160static struct freq_tbl clk_tbl_gsbi_uart[] = {
161 { 1843200, P_PLL8, 2, 6, 625 },
162 { 3686400, P_PLL8, 2, 12, 625 },
163 { 7372800, P_PLL8, 2, 24, 625 },
164 { 14745600, P_PLL8, 2, 48, 625 },
165 { 16000000, P_PLL8, 4, 1, 6 },
166 { 24000000, P_PLL8, 4, 1, 4 },
167 { 32000000, P_PLL8, 4, 1, 3 },
168 { 40000000, P_PLL8, 1, 5, 48 },
169 { 46400000, P_PLL8, 1, 29, 240 },
170 { 48000000, P_PLL8, 4, 1, 2 },
171 { 51200000, P_PLL8, 1, 2, 15 },
172 { 56000000, P_PLL8, 1, 7, 48 },
173 { 58982400, P_PLL8, 1, 96, 625 },
174 { 64000000, P_PLL8, 2, 1, 3 },
175 { }
176};
177
178static struct clk_rcg gsbi1_uart_src = {
179 .ns_reg = 0x29d4,
180 .md_reg = 0x29d0,
181 .mn = {
182 .mnctr_en_bit = 8,
183 .mnctr_reset_bit = 7,
184 .mnctr_mode_shift = 5,
185 .n_val_shift = 16,
186 .m_val_shift = 16,
187 .width = 16,
188 },
189 .p = {
190 .pre_div_shift = 3,
191 .pre_div_width = 2,
192 },
193 .s = {
194 .src_sel_shift = 0,
195 .parent_map = gcc_pxo_pll8_map,
196 },
197 .freq_tbl = clk_tbl_gsbi_uart,
198 .clkr = {
199 .enable_reg = 0x29d4,
200 .enable_mask = BIT(11),
201 .hw.init = &(struct clk_init_data){
202 .name = "gsbi1_uart_src",
203 .parent_names = gcc_pxo_pll8,
204 .num_parents = 2,
205 .ops = &clk_rcg_ops,
206 .flags = CLK_SET_PARENT_GATE,
207 },
208 },
209};
210
211static struct clk_branch gsbi1_uart_clk = {
212 .halt_reg = 0x2fcc,
213 .halt_bit = 12,
214 .clkr = {
215 .enable_reg = 0x29d4,
216 .enable_mask = BIT(9),
217 .hw.init = &(struct clk_init_data){
218 .name = "gsbi1_uart_clk",
219 .parent_names = (const char *[]){
220 "gsbi1_uart_src",
221 },
222 .num_parents = 1,
223 .ops = &clk_branch_ops,
224 .flags = CLK_SET_RATE_PARENT,
225 },
226 },
227};
228
229static struct clk_rcg gsbi2_uart_src = {
230 .ns_reg = 0x29f4,
231 .md_reg = 0x29f0,
232 .mn = {
233 .mnctr_en_bit = 8,
234 .mnctr_reset_bit = 7,
235 .mnctr_mode_shift = 5,
236 .n_val_shift = 16,
237 .m_val_shift = 16,
238 .width = 16,
239 },
240 .p = {
241 .pre_div_shift = 3,
242 .pre_div_width = 2,
243 },
244 .s = {
245 .src_sel_shift = 0,
246 .parent_map = gcc_pxo_pll8_map,
247 },
248 .freq_tbl = clk_tbl_gsbi_uart,
249 .clkr = {
250 .enable_reg = 0x29f4,
251 .enable_mask = BIT(11),
252 .hw.init = &(struct clk_init_data){
253 .name = "gsbi2_uart_src",
254 .parent_names = gcc_pxo_pll8,
255 .num_parents = 2,
256 .ops = &clk_rcg_ops,
257 .flags = CLK_SET_PARENT_GATE,
258 },
259 },
260};
261
262static struct clk_branch gsbi2_uart_clk = {
263 .halt_reg = 0x2fcc,
264 .halt_bit = 8,
265 .clkr = {
266 .enable_reg = 0x29f4,
267 .enable_mask = BIT(9),
268 .hw.init = &(struct clk_init_data){
269 .name = "gsbi2_uart_clk",
270 .parent_names = (const char *[]){
271 "gsbi2_uart_src",
272 },
273 .num_parents = 1,
274 .ops = &clk_branch_ops,
275 .flags = CLK_SET_RATE_PARENT,
276 },
277 },
278};
279
280static struct clk_rcg gsbi4_uart_src = {
281 .ns_reg = 0x2a34,
282 .md_reg = 0x2a30,
283 .mn = {
284 .mnctr_en_bit = 8,
285 .mnctr_reset_bit = 7,
286 .mnctr_mode_shift = 5,
287 .n_val_shift = 16,
288 .m_val_shift = 16,
289 .width = 16,
290 },
291 .p = {
292 .pre_div_shift = 3,
293 .pre_div_width = 2,
294 },
295 .s = {
296 .src_sel_shift = 0,
297 .parent_map = gcc_pxo_pll8_map,
298 },
299 .freq_tbl = clk_tbl_gsbi_uart,
300 .clkr = {
301 .enable_reg = 0x2a34,
302 .enable_mask = BIT(11),
303 .hw.init = &(struct clk_init_data){
304 .name = "gsbi4_uart_src",
305 .parent_names = gcc_pxo_pll8,
306 .num_parents = 2,
307 .ops = &clk_rcg_ops,
308 .flags = CLK_SET_PARENT_GATE,
309 },
310 },
311};
312
313static struct clk_branch gsbi4_uart_clk = {
314 .halt_reg = 0x2fd0,
315 .halt_bit = 26,
316 .clkr = {
317 .enable_reg = 0x2a34,
318 .enable_mask = BIT(9),
319 .hw.init = &(struct clk_init_data){
320 .name = "gsbi4_uart_clk",
321 .parent_names = (const char *[]){
322 "gsbi4_uart_src",
323 },
324 .num_parents = 1,
325 .ops = &clk_branch_ops,
326 .flags = CLK_SET_RATE_PARENT,
327 },
328 },
329};
330
331static struct clk_rcg gsbi5_uart_src = {
332 .ns_reg = 0x2a54,
333 .md_reg = 0x2a50,
334 .mn = {
335 .mnctr_en_bit = 8,
336 .mnctr_reset_bit = 7,
337 .mnctr_mode_shift = 5,
338 .n_val_shift = 16,
339 .m_val_shift = 16,
340 .width = 16,
341 },
342 .p = {
343 .pre_div_shift = 3,
344 .pre_div_width = 2,
345 },
346 .s = {
347 .src_sel_shift = 0,
348 .parent_map = gcc_pxo_pll8_map,
349 },
350 .freq_tbl = clk_tbl_gsbi_uart,
351 .clkr = {
352 .enable_reg = 0x2a54,
353 .enable_mask = BIT(11),
354 .hw.init = &(struct clk_init_data){
355 .name = "gsbi5_uart_src",
356 .parent_names = gcc_pxo_pll8,
357 .num_parents = 2,
358 .ops = &clk_rcg_ops,
359 .flags = CLK_SET_PARENT_GATE,
360 },
361 },
362};
363
364static struct clk_branch gsbi5_uart_clk = {
365 .halt_reg = 0x2fd0,
366 .halt_bit = 22,
367 .clkr = {
368 .enable_reg = 0x2a54,
369 .enable_mask = BIT(9),
370 .hw.init = &(struct clk_init_data){
371 .name = "gsbi5_uart_clk",
372 .parent_names = (const char *[]){
373 "gsbi5_uart_src",
374 },
375 .num_parents = 1,
376 .ops = &clk_branch_ops,
377 .flags = CLK_SET_RATE_PARENT,
378 },
379 },
380};
381
382static struct clk_rcg gsbi6_uart_src = {
383 .ns_reg = 0x2a74,
384 .md_reg = 0x2a70,
385 .mn = {
386 .mnctr_en_bit = 8,
387 .mnctr_reset_bit = 7,
388 .mnctr_mode_shift = 5,
389 .n_val_shift = 16,
390 .m_val_shift = 16,
391 .width = 16,
392 },
393 .p = {
394 .pre_div_shift = 3,
395 .pre_div_width = 2,
396 },
397 .s = {
398 .src_sel_shift = 0,
399 .parent_map = gcc_pxo_pll8_map,
400 },
401 .freq_tbl = clk_tbl_gsbi_uart,
402 .clkr = {
403 .enable_reg = 0x2a74,
404 .enable_mask = BIT(11),
405 .hw.init = &(struct clk_init_data){
406 .name = "gsbi6_uart_src",
407 .parent_names = gcc_pxo_pll8,
408 .num_parents = 2,
409 .ops = &clk_rcg_ops,
410 .flags = CLK_SET_PARENT_GATE,
411 },
412 },
413};
414
415static struct clk_branch gsbi6_uart_clk = {
416 .halt_reg = 0x2fd0,
417 .halt_bit = 18,
418 .clkr = {
419 .enable_reg = 0x2a74,
420 .enable_mask = BIT(9),
421 .hw.init = &(struct clk_init_data){
422 .name = "gsbi6_uart_clk",
423 .parent_names = (const char *[]){
424 "gsbi6_uart_src",
425 },
426 .num_parents = 1,
427 .ops = &clk_branch_ops,
428 .flags = CLK_SET_RATE_PARENT,
429 },
430 },
431};
432
433static struct clk_rcg gsbi7_uart_src = {
434 .ns_reg = 0x2a94,
435 .md_reg = 0x2a90,
436 .mn = {
437 .mnctr_en_bit = 8,
438 .mnctr_reset_bit = 7,
439 .mnctr_mode_shift = 5,
440 .n_val_shift = 16,
441 .m_val_shift = 16,
442 .width = 16,
443 },
444 .p = {
445 .pre_div_shift = 3,
446 .pre_div_width = 2,
447 },
448 .s = {
449 .src_sel_shift = 0,
450 .parent_map = gcc_pxo_pll8_map,
451 },
452 .freq_tbl = clk_tbl_gsbi_uart,
453 .clkr = {
454 .enable_reg = 0x2a94,
455 .enable_mask = BIT(11),
456 .hw.init = &(struct clk_init_data){
457 .name = "gsbi7_uart_src",
458 .parent_names = gcc_pxo_pll8,
459 .num_parents = 2,
460 .ops = &clk_rcg_ops,
461 .flags = CLK_SET_PARENT_GATE,
462 },
463 },
464};
465
466static struct clk_branch gsbi7_uart_clk = {
467 .halt_reg = 0x2fd0,
468 .halt_bit = 14,
469 .clkr = {
470 .enable_reg = 0x2a94,
471 .enable_mask = BIT(9),
472 .hw.init = &(struct clk_init_data){
473 .name = "gsbi7_uart_clk",
474 .parent_names = (const char *[]){
475 "gsbi7_uart_src",
476 },
477 .num_parents = 1,
478 .ops = &clk_branch_ops,
479 .flags = CLK_SET_RATE_PARENT,
480 },
481 },
482};
483
484static struct freq_tbl clk_tbl_gsbi_qup[] = {
485 { 1100000, P_PXO, 1, 2, 49 },
486 { 5400000, P_PXO, 1, 1, 5 },
487 { 10800000, P_PXO, 1, 2, 5 },
488 { 15060000, P_PLL8, 1, 2, 51 },
489 { 24000000, P_PLL8, 4, 1, 4 },
490 { 25600000, P_PLL8, 1, 1, 15 },
491 { 27000000, P_PXO, 1, 0, 0 },
492 { 48000000, P_PLL8, 4, 1, 2 },
493 { 51200000, P_PLL8, 1, 2, 15 },
494 { }
495};
496
497static struct clk_rcg gsbi1_qup_src = {
498 .ns_reg = 0x29cc,
499 .md_reg = 0x29c8,
500 .mn = {
501 .mnctr_en_bit = 8,
502 .mnctr_reset_bit = 7,
503 .mnctr_mode_shift = 5,
504 .n_val_shift = 16,
505 .m_val_shift = 16,
506 .width = 8,
507 },
508 .p = {
509 .pre_div_shift = 3,
510 .pre_div_width = 2,
511 },
512 .s = {
513 .src_sel_shift = 0,
514 .parent_map = gcc_pxo_pll8_map,
515 },
516 .freq_tbl = clk_tbl_gsbi_qup,
517 .clkr = {
518 .enable_reg = 0x29cc,
519 .enable_mask = BIT(11),
520 .hw.init = &(struct clk_init_data){
521 .name = "gsbi1_qup_src",
522 .parent_names = gcc_pxo_pll8,
523 .num_parents = 2,
524 .ops = &clk_rcg_ops,
525 .flags = CLK_SET_PARENT_GATE,
526 },
527 },
528};
529
530static struct clk_branch gsbi1_qup_clk = {
531 .halt_reg = 0x2fcc,
532 .halt_bit = 11,
533 .clkr = {
534 .enable_reg = 0x29cc,
535 .enable_mask = BIT(9),
536 .hw.init = &(struct clk_init_data){
537 .name = "gsbi1_qup_clk",
538 .parent_names = (const char *[]){ "gsbi1_qup_src" },
539 .num_parents = 1,
540 .ops = &clk_branch_ops,
541 .flags = CLK_SET_RATE_PARENT,
542 },
543 },
544};
545
546static struct clk_rcg gsbi2_qup_src = {
547 .ns_reg = 0x29ec,
548 .md_reg = 0x29e8,
549 .mn = {
550 .mnctr_en_bit = 8,
551 .mnctr_reset_bit = 7,
552 .mnctr_mode_shift = 5,
553 .n_val_shift = 16,
554 .m_val_shift = 16,
555 .width = 8,
556 },
557 .p = {
558 .pre_div_shift = 3,
559 .pre_div_width = 2,
560 },
561 .s = {
562 .src_sel_shift = 0,
563 .parent_map = gcc_pxo_pll8_map,
564 },
565 .freq_tbl = clk_tbl_gsbi_qup,
566 .clkr = {
567 .enable_reg = 0x29ec,
568 .enable_mask = BIT(11),
569 .hw.init = &(struct clk_init_data){
570 .name = "gsbi2_qup_src",
571 .parent_names = gcc_pxo_pll8,
572 .num_parents = 2,
573 .ops = &clk_rcg_ops,
574 .flags = CLK_SET_PARENT_GATE,
575 },
576 },
577};
578
579static struct clk_branch gsbi2_qup_clk = {
580 .halt_reg = 0x2fcc,
581 .halt_bit = 6,
582 .clkr = {
583 .enable_reg = 0x29ec,
584 .enable_mask = BIT(9),
585 .hw.init = &(struct clk_init_data){
586 .name = "gsbi2_qup_clk",
587 .parent_names = (const char *[]){ "gsbi2_qup_src" },
588 .num_parents = 1,
589 .ops = &clk_branch_ops,
590 .flags = CLK_SET_RATE_PARENT,
591 },
592 },
593};
594
595static struct clk_rcg gsbi4_qup_src = {
596 .ns_reg = 0x2a2c,
597 .md_reg = 0x2a28,
598 .mn = {
599 .mnctr_en_bit = 8,
600 .mnctr_reset_bit = 7,
601 .mnctr_mode_shift = 5,
602 .n_val_shift = 16,
603 .m_val_shift = 16,
604 .width = 8,
605 },
606 .p = {
607 .pre_div_shift = 3,
608 .pre_div_width = 2,
609 },
610 .s = {
611 .src_sel_shift = 0,
612 .parent_map = gcc_pxo_pll8_map,
613 },
614 .freq_tbl = clk_tbl_gsbi_qup,
615 .clkr = {
616 .enable_reg = 0x2a2c,
617 .enable_mask = BIT(11),
618 .hw.init = &(struct clk_init_data){
619 .name = "gsbi4_qup_src",
620 .parent_names = gcc_pxo_pll8,
621 .num_parents = 2,
622 .ops = &clk_rcg_ops,
623 .flags = CLK_SET_PARENT_GATE,
624 },
625 },
626};
627
628static struct clk_branch gsbi4_qup_clk = {
629 .halt_reg = 0x2fd0,
630 .halt_bit = 24,
631 .clkr = {
632 .enable_reg = 0x2a2c,
633 .enable_mask = BIT(9),
634 .hw.init = &(struct clk_init_data){
635 .name = "gsbi4_qup_clk",
636 .parent_names = (const char *[]){ "gsbi4_qup_src" },
637 .num_parents = 1,
638 .ops = &clk_branch_ops,
639 .flags = CLK_SET_RATE_PARENT,
640 },
641 },
642};
643
644static struct clk_rcg gsbi5_qup_src = {
645 .ns_reg = 0x2a4c,
646 .md_reg = 0x2a48,
647 .mn = {
648 .mnctr_en_bit = 8,
649 .mnctr_reset_bit = 7,
650 .mnctr_mode_shift = 5,
651 .n_val_shift = 16,
652 .m_val_shift = 16,
653 .width = 8,
654 },
655 .p = {
656 .pre_div_shift = 3,
657 .pre_div_width = 2,
658 },
659 .s = {
660 .src_sel_shift = 0,
661 .parent_map = gcc_pxo_pll8_map,
662 },
663 .freq_tbl = clk_tbl_gsbi_qup,
664 .clkr = {
665 .enable_reg = 0x2a4c,
666 .enable_mask = BIT(11),
667 .hw.init = &(struct clk_init_data){
668 .name = "gsbi5_qup_src",
669 .parent_names = gcc_pxo_pll8,
670 .num_parents = 2,
671 .ops = &clk_rcg_ops,
672 .flags = CLK_SET_PARENT_GATE,
673 },
674 },
675};
676
677static struct clk_branch gsbi5_qup_clk = {
678 .halt_reg = 0x2fd0,
679 .halt_bit = 20,
680 .clkr = {
681 .enable_reg = 0x2a4c,
682 .enable_mask = BIT(9),
683 .hw.init = &(struct clk_init_data){
684 .name = "gsbi5_qup_clk",
685 .parent_names = (const char *[]){ "gsbi5_qup_src" },
686 .num_parents = 1,
687 .ops = &clk_branch_ops,
688 .flags = CLK_SET_RATE_PARENT,
689 },
690 },
691};
692
693static struct clk_rcg gsbi6_qup_src = {
694 .ns_reg = 0x2a6c,
695 .md_reg = 0x2a68,
696 .mn = {
697 .mnctr_en_bit = 8,
698 .mnctr_reset_bit = 7,
699 .mnctr_mode_shift = 5,
700 .n_val_shift = 16,
701 .m_val_shift = 16,
702 .width = 8,
703 },
704 .p = {
705 .pre_div_shift = 3,
706 .pre_div_width = 2,
707 },
708 .s = {
709 .src_sel_shift = 0,
710 .parent_map = gcc_pxo_pll8_map,
711 },
712 .freq_tbl = clk_tbl_gsbi_qup,
713 .clkr = {
714 .enable_reg = 0x2a6c,
715 .enable_mask = BIT(11),
716 .hw.init = &(struct clk_init_data){
717 .name = "gsbi6_qup_src",
718 .parent_names = gcc_pxo_pll8,
719 .num_parents = 2,
720 .ops = &clk_rcg_ops,
721 .flags = CLK_SET_PARENT_GATE,
722 },
723 },
724};
725
726static struct clk_branch gsbi6_qup_clk = {
727 .halt_reg = 0x2fd0,
728 .halt_bit = 16,
729 .clkr = {
730 .enable_reg = 0x2a6c,
731 .enable_mask = BIT(9),
732 .hw.init = &(struct clk_init_data){
733 .name = "gsbi6_qup_clk",
734 .parent_names = (const char *[]){ "gsbi6_qup_src" },
735 .num_parents = 1,
736 .ops = &clk_branch_ops,
737 .flags = CLK_SET_RATE_PARENT,
738 },
739 },
740};
741
742static struct clk_rcg gsbi7_qup_src = {
743 .ns_reg = 0x2a8c,
744 .md_reg = 0x2a88,
745 .mn = {
746 .mnctr_en_bit = 8,
747 .mnctr_reset_bit = 7,
748 .mnctr_mode_shift = 5,
749 .n_val_shift = 16,
750 .m_val_shift = 16,
751 .width = 8,
752 },
753 .p = {
754 .pre_div_shift = 3,
755 .pre_div_width = 2,
756 },
757 .s = {
758 .src_sel_shift = 0,
759 .parent_map = gcc_pxo_pll8_map,
760 },
761 .freq_tbl = clk_tbl_gsbi_qup,
762 .clkr = {
763 .enable_reg = 0x2a8c,
764 .enable_mask = BIT(11),
765 .hw.init = &(struct clk_init_data){
766 .name = "gsbi7_qup_src",
767 .parent_names = gcc_pxo_pll8,
768 .num_parents = 2,
769 .ops = &clk_rcg_ops,
770 .flags = CLK_SET_PARENT_GATE,
771 },
772 },
773};
774
775static struct clk_branch gsbi7_qup_clk = {
776 .halt_reg = 0x2fd0,
777 .halt_bit = 12,
778 .clkr = {
779 .enable_reg = 0x2a8c,
780 .enable_mask = BIT(9),
781 .hw.init = &(struct clk_init_data){
782 .name = "gsbi7_qup_clk",
783 .parent_names = (const char *[]){ "gsbi7_qup_src" },
784 .num_parents = 1,
785 .ops = &clk_branch_ops,
786 .flags = CLK_SET_RATE_PARENT,
787 },
788 },
789};
790
791static struct clk_branch gsbi1_h_clk = {
792 .hwcg_reg = 0x29c0,
793 .hwcg_bit = 6,
794 .halt_reg = 0x2fcc,
795 .halt_bit = 13,
796 .clkr = {
797 .enable_reg = 0x29c0,
798 .enable_mask = BIT(4),
799 .hw.init = &(struct clk_init_data){
800 .name = "gsbi1_h_clk",
801 .ops = &clk_branch_ops,
802 .flags = CLK_IS_ROOT,
803 },
804 },
805};
806
807static struct clk_branch gsbi2_h_clk = {
808 .hwcg_reg = 0x29e0,
809 .hwcg_bit = 6,
810 .halt_reg = 0x2fcc,
811 .halt_bit = 9,
812 .clkr = {
813 .enable_reg = 0x29e0,
814 .enable_mask = BIT(4),
815 .hw.init = &(struct clk_init_data){
816 .name = "gsbi2_h_clk",
817 .ops = &clk_branch_ops,
818 .flags = CLK_IS_ROOT,
819 },
820 },
821};
822
823static struct clk_branch gsbi4_h_clk = {
824 .hwcg_reg = 0x2a20,
825 .hwcg_bit = 6,
826 .halt_reg = 0x2fd0,
827 .halt_bit = 27,
828 .clkr = {
829 .enable_reg = 0x2a20,
830 .enable_mask = BIT(4),
831 .hw.init = &(struct clk_init_data){
832 .name = "gsbi4_h_clk",
833 .ops = &clk_branch_ops,
834 .flags = CLK_IS_ROOT,
835 },
836 },
837};
838
839static struct clk_branch gsbi5_h_clk = {
840 .hwcg_reg = 0x2a40,
841 .hwcg_bit = 6,
842 .halt_reg = 0x2fd0,
843 .halt_bit = 23,
844 .clkr = {
845 .enable_reg = 0x2a40,
846 .enable_mask = BIT(4),
847 .hw.init = &(struct clk_init_data){
848 .name = "gsbi5_h_clk",
849 .ops = &clk_branch_ops,
850 .flags = CLK_IS_ROOT,
851 },
852 },
853};
854
855static struct clk_branch gsbi6_h_clk = {
856 .hwcg_reg = 0x2a60,
857 .hwcg_bit = 6,
858 .halt_reg = 0x2fd0,
859 .halt_bit = 19,
860 .clkr = {
861 .enable_reg = 0x2a60,
862 .enable_mask = BIT(4),
863 .hw.init = &(struct clk_init_data){
864 .name = "gsbi6_h_clk",
865 .ops = &clk_branch_ops,
866 .flags = CLK_IS_ROOT,
867 },
868 },
869};
870
871static struct clk_branch gsbi7_h_clk = {
872 .hwcg_reg = 0x2a80,
873 .hwcg_bit = 6,
874 .halt_reg = 0x2fd0,
875 .halt_bit = 15,
876 .clkr = {
877 .enable_reg = 0x2a80,
878 .enable_mask = BIT(4),
879 .hw.init = &(struct clk_init_data){
880 .name = "gsbi7_h_clk",
881 .ops = &clk_branch_ops,
882 .flags = CLK_IS_ROOT,
883 },
884 },
885};
886
887static const struct freq_tbl clk_tbl_gp[] = {
888 { 12500000, P_PXO, 2, 0, 0 },
889 { 25000000, P_PXO, 1, 0, 0 },
890 { 64000000, P_PLL8, 2, 1, 3 },
891 { 76800000, P_PLL8, 1, 1, 5 },
892 { 96000000, P_PLL8, 4, 0, 0 },
893 { 128000000, P_PLL8, 3, 0, 0 },
894 { 192000000, P_PLL8, 2, 0, 0 },
895 { }
896};
897
898static struct clk_rcg gp0_src = {
899 .ns_reg = 0x2d24,
900 .md_reg = 0x2d00,
901 .mn = {
902 .mnctr_en_bit = 8,
903 .mnctr_reset_bit = 7,
904 .mnctr_mode_shift = 5,
905 .n_val_shift = 16,
906 .m_val_shift = 16,
907 .width = 8,
908 },
909 .p = {
910 .pre_div_shift = 3,
911 .pre_div_width = 2,
912 },
913 .s = {
914 .src_sel_shift = 0,
915 .parent_map = gcc_pxo_pll8_cxo_map,
916 },
917 .freq_tbl = clk_tbl_gp,
918 .clkr = {
919 .enable_reg = 0x2d24,
920 .enable_mask = BIT(11),
921 .hw.init = &(struct clk_init_data){
922 .name = "gp0_src",
923 .parent_names = gcc_pxo_pll8_cxo,
924 .num_parents = 3,
925 .ops = &clk_rcg_ops,
926 .flags = CLK_SET_PARENT_GATE,
927 },
928 }
929};
930
931static struct clk_branch gp0_clk = {
932 .halt_reg = 0x2fd8,
933 .halt_bit = 7,
934 .clkr = {
935 .enable_reg = 0x2d24,
936 .enable_mask = BIT(9),
937 .hw.init = &(struct clk_init_data){
938 .name = "gp0_clk",
939 .parent_names = (const char *[]){ "gp0_src" },
940 .num_parents = 1,
941 .ops = &clk_branch_ops,
942 .flags = CLK_SET_RATE_PARENT,
943 },
944 },
945};
946
947static struct clk_rcg gp1_src = {
948 .ns_reg = 0x2d44,
949 .md_reg = 0x2d40,
950 .mn = {
951 .mnctr_en_bit = 8,
952 .mnctr_reset_bit = 7,
953 .mnctr_mode_shift = 5,
954 .n_val_shift = 16,
955 .m_val_shift = 16,
956 .width = 8,
957 },
958 .p = {
959 .pre_div_shift = 3,
960 .pre_div_width = 2,
961 },
962 .s = {
963 .src_sel_shift = 0,
964 .parent_map = gcc_pxo_pll8_cxo_map,
965 },
966 .freq_tbl = clk_tbl_gp,
967 .clkr = {
968 .enable_reg = 0x2d44,
969 .enable_mask = BIT(11),
970 .hw.init = &(struct clk_init_data){
971 .name = "gp1_src",
972 .parent_names = gcc_pxo_pll8_cxo,
973 .num_parents = 3,
974 .ops = &clk_rcg_ops,
975 .flags = CLK_SET_RATE_GATE,
976 },
977 }
978};
979
980static struct clk_branch gp1_clk = {
981 .halt_reg = 0x2fd8,
982 .halt_bit = 6,
983 .clkr = {
984 .enable_reg = 0x2d44,
985 .enable_mask = BIT(9),
986 .hw.init = &(struct clk_init_data){
987 .name = "gp1_clk",
988 .parent_names = (const char *[]){ "gp1_src" },
989 .num_parents = 1,
990 .ops = &clk_branch_ops,
991 .flags = CLK_SET_RATE_PARENT,
992 },
993 },
994};
995
996static struct clk_rcg gp2_src = {
997 .ns_reg = 0x2d64,
998 .md_reg = 0x2d60,
999 .mn = {
1000 .mnctr_en_bit = 8,
1001 .mnctr_reset_bit = 7,
1002 .mnctr_mode_shift = 5,
1003 .n_val_shift = 16,
1004 .m_val_shift = 16,
1005 .width = 8,
1006 },
1007 .p = {
1008 .pre_div_shift = 3,
1009 .pre_div_width = 2,
1010 },
1011 .s = {
1012 .src_sel_shift = 0,
1013 .parent_map = gcc_pxo_pll8_cxo_map,
1014 },
1015 .freq_tbl = clk_tbl_gp,
1016 .clkr = {
1017 .enable_reg = 0x2d64,
1018 .enable_mask = BIT(11),
1019 .hw.init = &(struct clk_init_data){
1020 .name = "gp2_src",
1021 .parent_names = gcc_pxo_pll8_cxo,
1022 .num_parents = 3,
1023 .ops = &clk_rcg_ops,
1024 .flags = CLK_SET_RATE_GATE,
1025 },
1026 }
1027};
1028
1029static struct clk_branch gp2_clk = {
1030 .halt_reg = 0x2fd8,
1031 .halt_bit = 5,
1032 .clkr = {
1033 .enable_reg = 0x2d64,
1034 .enable_mask = BIT(9),
1035 .hw.init = &(struct clk_init_data){
1036 .name = "gp2_clk",
1037 .parent_names = (const char *[]){ "gp2_src" },
1038 .num_parents = 1,
1039 .ops = &clk_branch_ops,
1040 .flags = CLK_SET_RATE_PARENT,
1041 },
1042 },
1043};
1044
1045static struct clk_branch pmem_clk = {
1046 .hwcg_reg = 0x25a0,
1047 .hwcg_bit = 6,
1048 .halt_reg = 0x2fc8,
1049 .halt_bit = 20,
1050 .clkr = {
1051 .enable_reg = 0x25a0,
1052 .enable_mask = BIT(4),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "pmem_clk",
1055 .ops = &clk_branch_ops,
1056 .flags = CLK_IS_ROOT,
1057 },
1058 },
1059};
1060
1061static struct clk_rcg prng_src = {
1062 .ns_reg = 0x2e80,
1063 .p = {
1064 .pre_div_shift = 3,
1065 .pre_div_width = 4,
1066 },
1067 .s = {
1068 .src_sel_shift = 0,
1069 .parent_map = gcc_pxo_pll8_map,
1070 },
1071 .clkr = {
1072 .hw.init = &(struct clk_init_data){
1073 .name = "prng_src",
1074 .parent_names = gcc_pxo_pll8,
1075 .num_parents = 2,
1076 .ops = &clk_rcg_ops,
1077 },
1078 },
1079};
1080
1081static struct clk_branch prng_clk = {
1082 .halt_reg = 0x2fd8,
1083 .halt_check = BRANCH_HALT_VOTED,
1084 .halt_bit = 10,
1085 .clkr = {
1086 .enable_reg = 0x3080,
1087 .enable_mask = BIT(10),
1088 .hw.init = &(struct clk_init_data){
1089 .name = "prng_clk",
1090 .parent_names = (const char *[]){ "prng_src" },
1091 .num_parents = 1,
1092 .ops = &clk_branch_ops,
1093 },
1094 },
1095};
1096
1097static const struct freq_tbl clk_tbl_sdc[] = {
1098 { 144000, P_PXO, 5, 18,625 },
1099 { 400000, P_PLL8, 4, 1, 240 },
1100 { 16000000, P_PLL8, 4, 1, 6 },
1101 { 17070000, P_PLL8, 1, 2, 45 },
1102 { 20210000, P_PLL8, 1, 1, 19 },
1103 { 24000000, P_PLL8, 4, 1, 4 },
1104 { 48000000, P_PLL8, 4, 1, 2 },
1105 { 64000000, P_PLL8, 3, 1, 2 },
1106 { 96000000, P_PLL8, 4, 0, 0 },
1107 { 192000000, P_PLL8, 2, 0, 0 },
1108 { }
1109};
1110
1111static struct clk_rcg sdc1_src = {
1112 .ns_reg = 0x282c,
1113 .md_reg = 0x2828,
1114 .mn = {
1115 .mnctr_en_bit = 8,
1116 .mnctr_reset_bit = 7,
1117 .mnctr_mode_shift = 5,
1118 .n_val_shift = 16,
1119 .m_val_shift = 16,
1120 .width = 8,
1121 },
1122 .p = {
1123 .pre_div_shift = 3,
1124 .pre_div_width = 2,
1125 },
1126 .s = {
1127 .src_sel_shift = 0,
1128 .parent_map = gcc_pxo_pll8_map,
1129 },
1130 .freq_tbl = clk_tbl_sdc,
1131 .clkr = {
1132 .enable_reg = 0x282c,
1133 .enable_mask = BIT(11),
1134 .hw.init = &(struct clk_init_data){
1135 .name = "sdc1_src",
1136 .parent_names = gcc_pxo_pll8,
1137 .num_parents = 2,
1138 .ops = &clk_rcg_ops,
1139 .flags = CLK_SET_RATE_GATE,
1140 },
1141 }
1142};
1143
1144static struct clk_branch sdc1_clk = {
1145 .halt_reg = 0x2fc8,
1146 .halt_bit = 6,
1147 .clkr = {
1148 .enable_reg = 0x282c,
1149 .enable_mask = BIT(9),
1150 .hw.init = &(struct clk_init_data){
1151 .name = "sdc1_clk",
1152 .parent_names = (const char *[]){ "sdc1_src" },
1153 .num_parents = 1,
1154 .ops = &clk_branch_ops,
1155 .flags = CLK_SET_RATE_PARENT,
1156 },
1157 },
1158};
1159
1160static struct clk_rcg sdc3_src = {
1161 .ns_reg = 0x286c,
1162 .md_reg = 0x2868,
1163 .mn = {
1164 .mnctr_en_bit = 8,
1165 .mnctr_reset_bit = 7,
1166 .mnctr_mode_shift = 5,
1167 .n_val_shift = 16,
1168 .m_val_shift = 16,
1169 .width = 8,
1170 },
1171 .p = {
1172 .pre_div_shift = 3,
1173 .pre_div_width = 2,
1174 },
1175 .s = {
1176 .src_sel_shift = 0,
1177 .parent_map = gcc_pxo_pll8_map,
1178 },
1179 .freq_tbl = clk_tbl_sdc,
1180 .clkr = {
1181 .enable_reg = 0x286c,
1182 .enable_mask = BIT(11),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "sdc3_src",
1185 .parent_names = gcc_pxo_pll8,
1186 .num_parents = 2,
1187 .ops = &clk_rcg_ops,
1188 .flags = CLK_SET_RATE_GATE,
1189 },
1190 }
1191};
1192
1193static struct clk_branch sdc3_clk = {
1194 .halt_reg = 0x2fc8,
1195 .halt_bit = 4,
1196 .clkr = {
1197 .enable_reg = 0x286c,
1198 .enable_mask = BIT(9),
1199 .hw.init = &(struct clk_init_data){
1200 .name = "sdc3_clk",
1201 .parent_names = (const char *[]){ "sdc3_src" },
1202 .num_parents = 1,
1203 .ops = &clk_branch_ops,
1204 .flags = CLK_SET_RATE_PARENT,
1205 },
1206 },
1207};
1208
1209static struct clk_branch sdc1_h_clk = {
1210 .hwcg_reg = 0x2820,
1211 .hwcg_bit = 6,
1212 .halt_reg = 0x2fc8,
1213 .halt_bit = 11,
1214 .clkr = {
1215 .enable_reg = 0x2820,
1216 .enable_mask = BIT(4),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "sdc1_h_clk",
1219 .ops = &clk_branch_ops,
1220 .flags = CLK_IS_ROOT,
1221 },
1222 },
1223};
1224
1225static struct clk_branch sdc3_h_clk = {
1226 .hwcg_reg = 0x2860,
1227 .hwcg_bit = 6,
1228 .halt_reg = 0x2fc8,
1229 .halt_bit = 9,
1230 .clkr = {
1231 .enable_reg = 0x2860,
1232 .enable_mask = BIT(4),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "sdc3_h_clk",
1235 .ops = &clk_branch_ops,
1236 .flags = CLK_IS_ROOT,
1237 },
1238 },
1239};
1240
1241static const struct freq_tbl clk_tbl_tsif_ref[] = {
1242 { 105000, P_PXO, 1, 1, 256 },
1243 { }
1244};
1245
1246static struct clk_rcg tsif_ref_src = {
1247 .ns_reg = 0x2710,
1248 .md_reg = 0x270c,
1249 .mn = {
1250 .mnctr_en_bit = 8,
1251 .mnctr_reset_bit = 7,
1252 .mnctr_mode_shift = 5,
1253 .n_val_shift = 16,
1254 .m_val_shift = 16,
1255 .width = 16,
1256 },
1257 .p = {
1258 .pre_div_shift = 3,
1259 .pre_div_width = 2,
1260 },
1261 .s = {
1262 .src_sel_shift = 0,
1263 .parent_map = gcc_pxo_pll8_map,
1264 },
1265 .freq_tbl = clk_tbl_tsif_ref,
1266 .clkr = {
1267 .enable_reg = 0x2710,
1268 .enable_mask = BIT(11),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "tsif_ref_src",
1271 .parent_names = gcc_pxo_pll8,
1272 .num_parents = 2,
1273 .ops = &clk_rcg_ops,
1274 .flags = CLK_SET_RATE_GATE,
1275 },
1276 }
1277};
1278
1279static struct clk_branch tsif_ref_clk = {
1280 .halt_reg = 0x2fd4,
1281 .halt_bit = 5,
1282 .clkr = {
1283 .enable_reg = 0x2710,
1284 .enable_mask = BIT(9),
1285 .hw.init = &(struct clk_init_data){
1286 .name = "tsif_ref_clk",
1287 .parent_names = (const char *[]){ "tsif_ref_src" },
1288 .num_parents = 1,
1289 .ops = &clk_branch_ops,
1290 .flags = CLK_SET_RATE_PARENT,
1291 },
1292 },
1293};
1294
1295static struct clk_branch tsif_h_clk = {
1296 .hwcg_reg = 0x2700,
1297 .hwcg_bit = 6,
1298 .halt_reg = 0x2fd4,
1299 .halt_bit = 7,
1300 .clkr = {
1301 .enable_reg = 0x2700,
1302 .enable_mask = BIT(4),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "tsif_h_clk",
1305 .ops = &clk_branch_ops,
1306 .flags = CLK_IS_ROOT,
1307 },
1308 },
1309};
1310
1311static struct clk_branch dma_bam_h_clk = {
1312 .hwcg_reg = 0x25c0,
1313 .hwcg_bit = 6,
1314 .halt_reg = 0x2fc8,
1315 .halt_bit = 12,
1316 .clkr = {
1317 .enable_reg = 0x25c0,
1318 .enable_mask = BIT(4),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "dma_bam_h_clk",
1321 .ops = &clk_branch_ops,
1322 .flags = CLK_IS_ROOT,
1323 },
1324 },
1325};
1326
1327static struct clk_branch adm0_clk = {
1328 .halt_reg = 0x2fdc,
1329 .halt_check = BRANCH_HALT_VOTED,
1330 .halt_bit = 12,
1331 .clkr = {
1332 .enable_reg = 0x3080,
1333 .enable_mask = BIT(2),
1334 .hw.init = &(struct clk_init_data){
1335 .name = "adm0_clk",
1336 .ops = &clk_branch_ops,
1337 .flags = CLK_IS_ROOT,
1338 },
1339 },
1340};
1341
1342static struct clk_branch adm0_pbus_clk = {
1343 .hwcg_reg = 0x2208,
1344 .hwcg_bit = 6,
1345 .halt_reg = 0x2fdc,
1346 .halt_check = BRANCH_HALT_VOTED,
1347 .halt_bit = 11,
1348 .clkr = {
1349 .enable_reg = 0x3080,
1350 .enable_mask = BIT(3),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "adm0_pbus_clk",
1353 .ops = &clk_branch_ops,
1354 .flags = CLK_IS_ROOT,
1355 },
1356 },
1357};
1358
1359static struct clk_branch pmic_arb0_h_clk = {
1360 .halt_reg = 0x2fd8,
1361 .halt_check = BRANCH_HALT_VOTED,
1362 .halt_bit = 22,
1363 .clkr = {
1364 .enable_reg = 0x3080,
1365 .enable_mask = BIT(8),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "pmic_arb0_h_clk",
1368 .ops = &clk_branch_ops,
1369 .flags = CLK_IS_ROOT,
1370 },
1371 },
1372};
1373
1374static struct clk_branch pmic_arb1_h_clk = {
1375 .halt_reg = 0x2fd8,
1376 .halt_check = BRANCH_HALT_VOTED,
1377 .halt_bit = 21,
1378 .clkr = {
1379 .enable_reg = 0x3080,
1380 .enable_mask = BIT(9),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "pmic_arb1_h_clk",
1383 .ops = &clk_branch_ops,
1384 .flags = CLK_IS_ROOT,
1385 },
1386 },
1387};
1388
1389static struct clk_branch pmic_ssbi2_clk = {
1390 .halt_reg = 0x2fd8,
1391 .halt_check = BRANCH_HALT_VOTED,
1392 .halt_bit = 23,
1393 .clkr = {
1394 .enable_reg = 0x3080,
1395 .enable_mask = BIT(7),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "pmic_ssbi2_clk",
1398 .ops = &clk_branch_ops,
1399 .flags = CLK_IS_ROOT,
1400 },
1401 },
1402};
1403
1404static struct clk_branch rpm_msg_ram_h_clk = {
1405 .hwcg_reg = 0x27e0,
1406 .hwcg_bit = 6,
1407 .halt_reg = 0x2fd8,
1408 .halt_check = BRANCH_HALT_VOTED,
1409 .halt_bit = 12,
1410 .clkr = {
1411 .enable_reg = 0x3080,
1412 .enable_mask = BIT(6),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "rpm_msg_ram_h_clk",
1415 .ops = &clk_branch_ops,
1416 .flags = CLK_IS_ROOT,
1417 },
1418 },
1419};
1420
1421static const struct freq_tbl clk_tbl_pcie_ref[] = {
1422 { 100000000, P_PLL3, 12, 0, 0 },
1423 { }
1424};
1425
1426static struct clk_rcg pcie_ref_src = {
1427 .ns_reg = 0x3860,
1428 .p = {
1429 .pre_div_shift = 3,
1430 .pre_div_width = 4,
1431 },
1432 .s = {
1433 .src_sel_shift = 0,
1434 .parent_map = gcc_pxo_pll3_map,
1435 },
1436 .freq_tbl = clk_tbl_pcie_ref,
1437 .clkr = {
1438 .enable_reg = 0x3860,
1439 .enable_mask = BIT(11),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "pcie_ref_src",
1442 .parent_names = gcc_pxo_pll3,
1443 .num_parents = 2,
1444 .ops = &clk_rcg_ops,
1445 .flags = CLK_SET_RATE_GATE,
1446 },
1447 },
1448};
1449
1450static struct clk_branch pcie_ref_src_clk = {
1451 .halt_reg = 0x2fdc,
1452 .halt_bit = 30,
1453 .clkr = {
1454 .enable_reg = 0x3860,
1455 .enable_mask = BIT(9),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "pcie_ref_src_clk",
1458 .parent_names = (const char *[]){ "pcie_ref_src" },
1459 .num_parents = 1,
1460 .ops = &clk_branch_ops,
1461 .flags = CLK_SET_RATE_PARENT,
1462 },
1463 },
1464};
1465
1466static struct clk_branch pcie_a_clk = {
1467 .halt_reg = 0x2fc0,
1468 .halt_bit = 13,
1469 .clkr = {
1470 .enable_reg = 0x22c0,
1471 .enable_mask = BIT(4),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "pcie_a_clk",
1474 .ops = &clk_branch_ops,
1475 .flags = CLK_IS_ROOT,
1476 },
1477 },
1478};
1479
1480static struct clk_branch pcie_aux_clk = {
1481 .halt_reg = 0x2fdc,
1482 .halt_bit = 31,
1483 .clkr = {
1484 .enable_reg = 0x22c8,
1485 .enable_mask = BIT(4),
1486 .hw.init = &(struct clk_init_data){
1487 .name = "pcie_aux_clk",
1488 .ops = &clk_branch_ops,
1489 .flags = CLK_IS_ROOT,
1490 },
1491 },
1492};
1493
1494static struct clk_branch pcie_h_clk = {
1495 .halt_reg = 0x2fd4,
1496 .halt_bit = 8,
1497 .clkr = {
1498 .enable_reg = 0x22cc,
1499 .enable_mask = BIT(4),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "pcie_h_clk",
1502 .ops = &clk_branch_ops,
1503 .flags = CLK_IS_ROOT,
1504 },
1505 },
1506};
1507
1508static struct clk_branch pcie_phy_clk = {
1509 .halt_reg = 0x2fdc,
1510 .halt_bit = 29,
1511 .clkr = {
1512 .enable_reg = 0x22d0,
1513 .enable_mask = BIT(4),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "pcie_phy_clk",
1516 .ops = &clk_branch_ops,
1517 .flags = CLK_IS_ROOT,
1518 },
1519 },
1520};
1521
1522static struct clk_rcg pcie1_ref_src = {
1523 .ns_reg = 0x3aa0,
1524 .p = {
1525 .pre_div_shift = 3,
1526 .pre_div_width = 4,
1527 },
1528 .s = {
1529 .src_sel_shift = 0,
1530 .parent_map = gcc_pxo_pll3_map,
1531 },
1532 .freq_tbl = clk_tbl_pcie_ref,
1533 .clkr = {
1534 .enable_reg = 0x3aa0,
1535 .enable_mask = BIT(11),
1536 .hw.init = &(struct clk_init_data){
1537 .name = "pcie1_ref_src",
1538 .parent_names = gcc_pxo_pll3,
1539 .num_parents = 2,
1540 .ops = &clk_rcg_ops,
1541 .flags = CLK_SET_RATE_GATE,
1542 },
1543 },
1544};
1545
1546static struct clk_branch pcie1_ref_src_clk = {
1547 .halt_reg = 0x2fdc,
1548 .halt_bit = 27,
1549 .clkr = {
1550 .enable_reg = 0x3aa0,
1551 .enable_mask = BIT(9),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "pcie1_ref_src_clk",
1554 .parent_names = (const char *[]){ "pcie1_ref_src" },
1555 .num_parents = 1,
1556 .ops = &clk_branch_ops,
1557 .flags = CLK_SET_RATE_PARENT,
1558 },
1559 },
1560};
1561
1562static struct clk_branch pcie1_a_clk = {
1563 .halt_reg = 0x2fc0,
1564 .halt_bit = 10,
1565 .clkr = {
1566 .enable_reg = 0x3a80,
1567 .enable_mask = BIT(4),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "pcie1_a_clk",
1570 .ops = &clk_branch_ops,
1571 .flags = CLK_IS_ROOT,
1572 },
1573 },
1574};
1575
1576static struct clk_branch pcie1_aux_clk = {
1577 .halt_reg = 0x2fdc,
1578 .halt_bit = 28,
1579 .clkr = {
1580 .enable_reg = 0x3a88,
1581 .enable_mask = BIT(4),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "pcie1_aux_clk",
1584 .ops = &clk_branch_ops,
1585 .flags = CLK_IS_ROOT,
1586 },
1587 },
1588};
1589
1590static struct clk_branch pcie1_h_clk = {
1591 .halt_reg = 0x2fd4,
1592 .halt_bit = 9,
1593 .clkr = {
1594 .enable_reg = 0x3a8c,
1595 .enable_mask = BIT(4),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "pcie1_h_clk",
1598 .ops = &clk_branch_ops,
1599 .flags = CLK_IS_ROOT,
1600 },
1601 },
1602};
1603
1604static struct clk_branch pcie1_phy_clk = {
1605 .halt_reg = 0x2fdc,
1606 .halt_bit = 26,
1607 .clkr = {
1608 .enable_reg = 0x3a90,
1609 .enable_mask = BIT(4),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "pcie1_phy_clk",
1612 .ops = &clk_branch_ops,
1613 .flags = CLK_IS_ROOT,
1614 },
1615 },
1616};
1617
1618static struct clk_rcg pcie2_ref_src = {
1619 .ns_reg = 0x3ae0,
1620 .p = {
1621 .pre_div_shift = 3,
1622 .pre_div_width = 4,
1623 },
1624 .s = {
1625 .src_sel_shift = 0,
1626 .parent_map = gcc_pxo_pll3_map,
1627 },
1628 .freq_tbl = clk_tbl_pcie_ref,
1629 .clkr = {
1630 .enable_reg = 0x3ae0,
1631 .enable_mask = BIT(11),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "pcie2_ref_src",
1634 .parent_names = gcc_pxo_pll3,
1635 .num_parents = 2,
1636 .ops = &clk_rcg_ops,
1637 .flags = CLK_SET_RATE_GATE,
1638 },
1639 },
1640};
1641
1642static struct clk_branch pcie2_ref_src_clk = {
1643 .halt_reg = 0x2fdc,
1644 .halt_bit = 24,
1645 .clkr = {
1646 .enable_reg = 0x3ae0,
1647 .enable_mask = BIT(9),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "pcie2_ref_src_clk",
1650 .parent_names = (const char *[]){ "pcie2_ref_src" },
1651 .num_parents = 1,
1652 .ops = &clk_branch_ops,
1653 .flags = CLK_SET_RATE_PARENT,
1654 },
1655 },
1656};
1657
1658static struct clk_branch pcie2_a_clk = {
1659 .halt_reg = 0x2fc0,
1660 .halt_bit = 9,
1661 .clkr = {
1662 .enable_reg = 0x3ac0,
1663 .enable_mask = BIT(4),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "pcie2_a_clk",
1666 .ops = &clk_branch_ops,
1667 .flags = CLK_IS_ROOT,
1668 },
1669 },
1670};
1671
1672static struct clk_branch pcie2_aux_clk = {
1673 .halt_reg = 0x2fdc,
1674 .halt_bit = 25,
1675 .clkr = {
1676 .enable_reg = 0x3ac8,
1677 .enable_mask = BIT(4),
1678 .hw.init = &(struct clk_init_data){
1679 .name = "pcie2_aux_clk",
1680 .ops = &clk_branch_ops,
1681 .flags = CLK_IS_ROOT,
1682 },
1683 },
1684};
1685
1686static struct clk_branch pcie2_h_clk = {
1687 .halt_reg = 0x2fd4,
1688 .halt_bit = 10,
1689 .clkr = {
1690 .enable_reg = 0x3acc,
1691 .enable_mask = BIT(4),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "pcie2_h_clk",
1694 .ops = &clk_branch_ops,
1695 .flags = CLK_IS_ROOT,
1696 },
1697 },
1698};
1699
1700static struct clk_branch pcie2_phy_clk = {
1701 .halt_reg = 0x2fdc,
1702 .halt_bit = 23,
1703 .clkr = {
1704 .enable_reg = 0x3ad0,
1705 .enable_mask = BIT(4),
1706 .hw.init = &(struct clk_init_data){
1707 .name = "pcie2_phy_clk",
1708 .ops = &clk_branch_ops,
1709 .flags = CLK_IS_ROOT,
1710 },
1711 },
1712};
1713
1714static const struct freq_tbl clk_tbl_sata_ref[] = {
1715 { 100000000, P_PLL3, 12, 0, 0 },
1716 { }
1717};
1718
1719static struct clk_rcg sata_ref_src = {
1720 .ns_reg = 0x2c08,
1721 .p = {
1722 .pre_div_shift = 3,
1723 .pre_div_width = 4,
1724 },
1725 .s = {
1726 .src_sel_shift = 0,
1727 .parent_map = gcc_pxo_pll3_sata_map,
1728 },
1729 .freq_tbl = clk_tbl_sata_ref,
1730 .clkr = {
1731 .enable_reg = 0x2c08,
1732 .enable_mask = BIT(7),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "sata_ref_src",
1735 .parent_names = gcc_pxo_pll3,
1736 .num_parents = 2,
1737 .ops = &clk_rcg_ops,
1738 .flags = CLK_SET_RATE_GATE,
1739 },
1740 },
1741};
1742
1743static struct clk_branch sata_rxoob_clk = {
1744 .halt_reg = 0x2fdc,
1745 .halt_bit = 20,
1746 .clkr = {
1747 .enable_reg = 0x2c0c,
1748 .enable_mask = BIT(4),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "sata_rxoob_clk",
1751 .parent_names = (const char *[]){ "sata_ref_src" },
1752 .num_parents = 1,
1753 .ops = &clk_branch_ops,
1754 .flags = CLK_SET_RATE_PARENT,
1755 },
1756 },
1757};
1758
1759static struct clk_branch sata_pmalive_clk = {
1760 .halt_reg = 0x2fdc,
1761 .halt_bit = 19,
1762 .clkr = {
1763 .enable_reg = 0x2c10,
1764 .enable_mask = BIT(4),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "sata_pmalive_clk",
1767 .parent_names = (const char *[]){ "sata_ref_src" },
1768 .num_parents = 1,
1769 .ops = &clk_branch_ops,
1770 .flags = CLK_SET_RATE_PARENT,
1771 },
1772 },
1773};
1774
1775static struct clk_branch sata_phy_ref_clk = {
1776 .halt_reg = 0x2fdc,
1777 .halt_bit = 18,
1778 .clkr = {
1779 .enable_reg = 0x2c14,
1780 .enable_mask = BIT(4),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "sata_phy_ref_clk",
1783 .parent_names = (const char *[]){ "pxo" },
1784 .num_parents = 1,
1785 .ops = &clk_branch_ops,
1786 },
1787 },
1788};
1789
1790static struct clk_branch sata_a_clk = {
1791 .halt_reg = 0x2fc0,
1792 .halt_bit = 12,
1793 .clkr = {
1794 .enable_reg = 0x2c20,
1795 .enable_mask = BIT(4),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "sata_a_clk",
1798 .ops = &clk_branch_ops,
1799 .flags = CLK_IS_ROOT,
1800 },
1801 },
1802};
1803
1804static struct clk_branch sata_h_clk = {
1805 .halt_reg = 0x2fdc,
1806 .halt_bit = 21,
1807 .clkr = {
1808 .enable_reg = 0x2c00,
1809 .enable_mask = BIT(4),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "sata_h_clk",
1812 .ops = &clk_branch_ops,
1813 .flags = CLK_IS_ROOT,
1814 },
1815 },
1816};
1817
1818static struct clk_branch sfab_sata_s_h_clk = {
1819 .halt_reg = 0x2fc4,
1820 .halt_bit = 14,
1821 .clkr = {
1822 .enable_reg = 0x2480,
1823 .enable_mask = BIT(4),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "sfab_sata_s_h_clk",
1826 .ops = &clk_branch_ops,
1827 .flags = CLK_IS_ROOT,
1828 },
1829 },
1830};
1831
1832static struct clk_branch sata_phy_cfg_clk = {
1833 .halt_reg = 0x2fcc,
1834 .halt_bit = 14,
1835 .clkr = {
1836 .enable_reg = 0x2c40,
1837 .enable_mask = BIT(4),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "sata_phy_cfg_clk",
1840 .ops = &clk_branch_ops,
1841 .flags = CLK_IS_ROOT,
1842 },
1843 },
1844};
1845
1846static const struct freq_tbl clk_tbl_usb30_master[] = {
1847 { 125000000, P_PLL0, 1, 5, 32 },
1848 { }
1849};
1850
1851static struct clk_rcg usb30_master_clk_src = {
1852 .ns_reg = 0x3b2c,
1853 .md_reg = 0x3b28,
1854 .mn = {
1855 .mnctr_en_bit = 8,
1856 .mnctr_reset_bit = 7,
1857 .mnctr_mode_shift = 5,
1858 .n_val_shift = 16,
1859 .m_val_shift = 16,
1860 .width = 8,
1861 },
1862 .p = {
1863 .pre_div_shift = 3,
1864 .pre_div_width = 2,
1865 },
1866 .s = {
1867 .src_sel_shift = 0,
1868 .parent_map = gcc_pxo_pll8_pll0,
1869 },
1870 .freq_tbl = clk_tbl_usb30_master,
1871 .clkr = {
1872 .enable_reg = 0x3b2c,
1873 .enable_mask = BIT(11),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "usb30_master_ref_src",
1876 .parent_names = gcc_pxo_pll8_pll0_map,
1877 .num_parents = 3,
1878 .ops = &clk_rcg_ops,
1879 .flags = CLK_SET_RATE_GATE,
1880 },
1881 },
1882};
1883
1884static struct clk_branch usb30_0_branch_clk = {
1885 .halt_reg = 0x2fc4,
1886 .halt_bit = 22,
1887 .clkr = {
1888 .enable_reg = 0x3b24,
1889 .enable_mask = BIT(4),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "usb30_0_branch_clk",
1892 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1893 .num_parents = 1,
1894 .ops = &clk_branch_ops,
1895 .flags = CLK_SET_RATE_PARENT,
1896 },
1897 },
1898};
1899
1900static struct clk_branch usb30_1_branch_clk = {
1901 .halt_reg = 0x2fc4,
1902 .halt_bit = 17,
1903 .clkr = {
1904 .enable_reg = 0x3b34,
1905 .enable_mask = BIT(4),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "usb30_1_branch_clk",
1908 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1909 .num_parents = 1,
1910 .ops = &clk_branch_ops,
1911 .flags = CLK_SET_RATE_PARENT,
1912 },
1913 },
1914};
1915
1916static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1917 { 60000000, P_PLL8, 1, 5, 32 },
1918 { }
1919};
1920
1921static struct clk_rcg usb30_utmi_clk = {
1922 .ns_reg = 0x3b44,
1923 .md_reg = 0x3b40,
1924 .mn = {
1925 .mnctr_en_bit = 8,
1926 .mnctr_reset_bit = 7,
1927 .mnctr_mode_shift = 5,
1928 .n_val_shift = 16,
1929 .m_val_shift = 16,
1930 .width = 8,
1931 },
1932 .p = {
1933 .pre_div_shift = 3,
1934 .pre_div_width = 2,
1935 },
1936 .s = {
1937 .src_sel_shift = 0,
1938 .parent_map = gcc_pxo_pll8_pll0,
1939 },
1940 .freq_tbl = clk_tbl_usb30_utmi,
1941 .clkr = {
1942 .enable_reg = 0x3b44,
1943 .enable_mask = BIT(11),
1944 .hw.init = &(struct clk_init_data){
1945 .name = "usb30_utmi_clk",
1946 .parent_names = gcc_pxo_pll8_pll0_map,
1947 .num_parents = 3,
1948 .ops = &clk_rcg_ops,
1949 .flags = CLK_SET_RATE_GATE,
1950 },
1951 },
1952};
1953
1954static struct clk_branch usb30_0_utmi_clk_ctl = {
1955 .halt_reg = 0x2fc4,
1956 .halt_bit = 21,
1957 .clkr = {
1958 .enable_reg = 0x3b48,
1959 .enable_mask = BIT(4),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "usb30_0_utmi_clk_ctl",
1962 .parent_names = (const char *[]){ "usb30_utmi_clk", },
1963 .num_parents = 1,
1964 .ops = &clk_branch_ops,
1965 .flags = CLK_SET_RATE_PARENT,
1966 },
1967 },
1968};
1969
1970static struct clk_branch usb30_1_utmi_clk_ctl = {
1971 .halt_reg = 0x2fc4,
1972 .halt_bit = 15,
1973 .clkr = {
1974 .enable_reg = 0x3b4c,
1975 .enable_mask = BIT(4),
1976 .hw.init = &(struct clk_init_data){
1977 .name = "usb30_1_utmi_clk_ctl",
1978 .parent_names = (const char *[]){ "usb30_utmi_clk", },
1979 .num_parents = 1,
1980 .ops = &clk_branch_ops,
1981 .flags = CLK_SET_RATE_PARENT,
1982 },
1983 },
1984};
1985
1986static const struct freq_tbl clk_tbl_usb[] = {
1987 { 60000000, P_PLL8, 1, 5, 32 },
1988 { }
1989};
1990
1991static struct clk_rcg usb_hs1_xcvr_clk_src = {
1992 .ns_reg = 0x290C,
1993 .md_reg = 0x2908,
1994 .mn = {
1995 .mnctr_en_bit = 8,
1996 .mnctr_reset_bit = 7,
1997 .mnctr_mode_shift = 5,
1998 .n_val_shift = 16,
1999 .m_val_shift = 16,
2000 .width = 8,
2001 },
2002 .p = {
2003 .pre_div_shift = 3,
2004 .pre_div_width = 2,
2005 },
2006 .s = {
2007 .src_sel_shift = 0,
2008 .parent_map = gcc_pxo_pll8_pll0,
2009 },
2010 .freq_tbl = clk_tbl_usb,
2011 .clkr = {
2012 .enable_reg = 0x2968,
2013 .enable_mask = BIT(11),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "usb_hs1_xcvr_src",
2016 .parent_names = gcc_pxo_pll8_pll0_map,
2017 .num_parents = 3,
2018 .ops = &clk_rcg_ops,
2019 .flags = CLK_SET_RATE_GATE,
2020 },
2021 },
2022};
2023
2024static struct clk_branch usb_hs1_xcvr_clk = {
2025 .halt_reg = 0x2fcc,
2026 .halt_bit = 17,
2027 .clkr = {
2028 .enable_reg = 0x290c,
2029 .enable_mask = BIT(9),
2030 .hw.init = &(struct clk_init_data){
2031 .name = "usb_hs1_xcvr_clk",
2032 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2033 .num_parents = 1,
2034 .ops = &clk_branch_ops,
2035 .flags = CLK_SET_RATE_PARENT,
2036 },
2037 },
2038};
2039
2040static struct clk_branch usb_hs1_h_clk = {
2041 .hwcg_reg = 0x2900,
2042 .hwcg_bit = 6,
2043 .halt_reg = 0x2fc8,
2044 .halt_bit = 1,
2045 .clkr = {
2046 .enable_reg = 0x2900,
2047 .enable_mask = BIT(4),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "usb_hs1_h_clk",
2050 .ops = &clk_branch_ops,
2051 .flags = CLK_IS_ROOT,
2052 },
2053 },
2054};
2055
2056static struct clk_rcg usb_fs1_xcvr_clk_src = {
2057 .ns_reg = 0x2968,
2058 .md_reg = 0x2964,
2059 .mn = {
2060 .mnctr_en_bit = 8,
2061 .mnctr_reset_bit = 7,
2062 .mnctr_mode_shift = 5,
2063 .n_val_shift = 16,
2064 .m_val_shift = 16,
2065 .width = 8,
2066 },
2067 .p = {
2068 .pre_div_shift = 3,
2069 .pre_div_width = 2,
2070 },
2071 .s = {
2072 .src_sel_shift = 0,
2073 .parent_map = gcc_pxo_pll8_pll0,
2074 },
2075 .freq_tbl = clk_tbl_usb,
2076 .clkr = {
2077 .enable_reg = 0x2968,
2078 .enable_mask = BIT(11),
2079 .hw.init = &(struct clk_init_data){
2080 .name = "usb_fs1_xcvr_src",
2081 .parent_names = gcc_pxo_pll8_pll0_map,
2082 .num_parents = 3,
2083 .ops = &clk_rcg_ops,
2084 .flags = CLK_SET_RATE_GATE,
2085 },
2086 },
2087};
2088
2089static struct clk_branch usb_fs1_xcvr_clk = {
2090 .halt_reg = 0x2fcc,
2091 .halt_bit = 17,
2092 .clkr = {
2093 .enable_reg = 0x2968,
2094 .enable_mask = BIT(9),
2095 .hw.init = &(struct clk_init_data){
2096 .name = "usb_fs1_xcvr_clk",
2097 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2098 .num_parents = 1,
2099 .ops = &clk_branch_ops,
2100 .flags = CLK_SET_RATE_PARENT,
2101 },
2102 },
2103};
2104
2105static struct clk_branch usb_fs1_sys_clk = {
2106 .halt_reg = 0x2fcc,
2107 .halt_bit = 18,
2108 .clkr = {
2109 .enable_reg = 0x296c,
2110 .enable_mask = BIT(4),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "usb_fs1_sys_clk",
2113 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2114 .num_parents = 1,
2115 .ops = &clk_branch_ops,
2116 .flags = CLK_SET_RATE_PARENT,
2117 },
2118 },
2119};
2120
2121static struct clk_branch usb_fs1_h_clk = {
2122 .halt_reg = 0x2fcc,
2123 .halt_bit = 19,
2124 .clkr = {
2125 .enable_reg = 0x2960,
2126 .enable_mask = BIT(4),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "usb_fs1_h_clk",
2129 .ops = &clk_branch_ops,
2130 .flags = CLK_IS_ROOT,
2131 },
2132 },
2133};
2134
2135static struct clk_regmap *gcc_ipq806x_clks[] = {
2136 [PLL3] = &pll3.clkr,
2137 [PLL8] = &pll8.clkr,
2138 [PLL8_VOTE] = &pll8_vote,
2139 [PLL14] = &pll14.clkr,
2140 [PLL14_VOTE] = &pll14_vote,
2141 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2142 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2143 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2144 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2145 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2146 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2147 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2148 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2149 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2150 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2151 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2152 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2153 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2154 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2155 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2156 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2157 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2158 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2159 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2160 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2161 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2162 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2163 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2164 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2165 [GP0_SRC] = &gp0_src.clkr,
2166 [GP0_CLK] = &gp0_clk.clkr,
2167 [GP1_SRC] = &gp1_src.clkr,
2168 [GP1_CLK] = &gp1_clk.clkr,
2169 [GP2_SRC] = &gp2_src.clkr,
2170 [GP2_CLK] = &gp2_clk.clkr,
2171 [PMEM_A_CLK] = &pmem_clk.clkr,
2172 [PRNG_SRC] = &prng_src.clkr,
2173 [PRNG_CLK] = &prng_clk.clkr,
2174 [SDC1_SRC] = &sdc1_src.clkr,
2175 [SDC1_CLK] = &sdc1_clk.clkr,
2176 [SDC3_SRC] = &sdc3_src.clkr,
2177 [SDC3_CLK] = &sdc3_clk.clkr,
2178 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2179 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2180 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2181 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2182 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2183 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2184 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2185 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2186 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2187 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2188 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2189 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2190 [ADM0_CLK] = &adm0_clk.clkr,
2191 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2192 [PCIE_A_CLK] = &pcie_a_clk.clkr,
2193 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2194 [PCIE_H_CLK] = &pcie_h_clk.clkr,
2195 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2196 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2197 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2198 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2199 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2200 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2201 [SATA_H_CLK] = &sata_h_clk.clkr,
2202 [SATA_CLK_SRC] = &sata_ref_src.clkr,
2203 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2204 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2205 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2206 [SATA_A_CLK] = &sata_a_clk.clkr,
2207 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2208 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2209 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2210 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2211 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2212 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2213 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2214 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2215 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2216 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2217 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2218 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2219 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2220 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2221 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2222 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2223 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2224 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2225 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2226 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2227 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2228 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2229 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2230 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2231 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2232 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2233 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2234 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2235};
2236
2237static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2238 [QDSS_STM_RESET] = { 0x2060, 6 },
2239 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2240 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2241 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2242 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2243 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2244 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2245 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2246 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2247 [ADM0_C2_RESET] = { 0x220c, 4 },
2248 [ADM0_C1_RESET] = { 0x220c, 3 },
2249 [ADM0_C0_RESET] = { 0x220c, 2 },
2250 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2251 [ADM0_RESET] = { 0x220c, 0 },
2252 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2253 [QDSS_POR_RESET] = { 0x2260, 4 },
2254 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2255 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2256 [QDSS_AXI_RESET] = { 0x2260, 1 },
2257 [QDSS_DBG_RESET] = { 0x2260, 0 },
2258 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2259 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2260 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2261 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2262 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2263 [PCIE_POR_RESET] = { 0x22dc, 3 },
2264 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2265 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2266 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2267 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2268 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2269 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2270 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2271 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2272 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2273 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2274 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2275 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2276 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2277 [PPSS_PROC_RESET] = { 0x2594, 1 },
2278 [PPSS_RESET] = { 0x2594, 0 },
2279 [DMA_BAM_RESET] = { 0x25c0, 7 },
2280 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2281 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2282 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2283 [TSIF_H_RESET] = { 0x2700, 7 },
2284 [CE1_H_RESET] = { 0x2720, 7 },
2285 [CE1_CORE_RESET] = { 0x2724, 7 },
2286 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2287 [CE2_H_RESET] = { 0x2740, 7 },
2288 [CE2_CORE_RESET] = { 0x2744, 7 },
2289 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2290 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2291 [RPM_PROC_RESET] = { 0x27c0, 7 },
2292 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2293 [SDC1_RESET] = { 0x2830, 0 },
2294 [SDC2_RESET] = { 0x2850, 0 },
2295 [SDC3_RESET] = { 0x2870, 0 },
2296 [SDC4_RESET] = { 0x2890, 0 },
2297 [USB_HS1_RESET] = { 0x2910, 0 },
2298 [USB_HSIC_RESET] = { 0x2934, 0 },
2299 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2300 [USB_FS1_RESET] = { 0x2974, 0 },
2301 [GSBI1_RESET] = { 0x29dc, 0 },
2302 [GSBI2_RESET] = { 0x29fc, 0 },
2303 [GSBI3_RESET] = { 0x2a1c, 0 },
2304 [GSBI4_RESET] = { 0x2a3c, 0 },
2305 [GSBI5_RESET] = { 0x2a5c, 0 },
2306 [GSBI6_RESET] = { 0x2a7c, 0 },
2307 [GSBI7_RESET] = { 0x2a9c, 0 },
2308 [SPDM_RESET] = { 0x2b6c, 0 },
2309 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2310 [TLMM_H_RESET] = { 0x2ba0, 7 },
2311 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2312 [SATA_RESET] = { 0x2c1c, 0 },
2313 [TSSC_RESET] = { 0x2ca0, 7 },
2314 [PDM_RESET] = { 0x2cc0, 12 },
2315 [MPM_H_RESET] = { 0x2da0, 7 },
2316 [MPM_RESET] = { 0x2da4, 0 },
2317 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2318 [PRNG_RESET] = { 0x2e80, 12 },
2319 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2320 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2321 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2322 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2323 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2324 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2325 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2326 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2327 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2328 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2329 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2330 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2331 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2332 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2333 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2334 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2335 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2336 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2337 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2338 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2339 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2340 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2341 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2342 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2343 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2344 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2345 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2346 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2347 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2348 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2349 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2350 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2351 [NSSFB0_RESET] = { 0x3b60, 6 },
2352 [NSSFB1_RESET] = { 0x3b60, 7 },
2353};
2354
2355static const struct regmap_config gcc_ipq806x_regmap_config = {
2356 .reg_bits = 32,
2357 .reg_stride = 4,
2358 .val_bits = 32,
2359 .max_register = 0x3e40,
2360 .fast_io = true,
2361};
2362
2363static const struct qcom_cc_desc gcc_ipq806x_desc = {
2364 .config = &gcc_ipq806x_regmap_config,
2365 .clks = gcc_ipq806x_clks,
2366 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2367 .resets = gcc_ipq806x_resets,
2368 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2369};
2370
2371static const struct of_device_id gcc_ipq806x_match_table[] = {
2372 { .compatible = "qcom,gcc-ipq8064" },
2373 { }
2374};
2375MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2376
2377static int gcc_ipq806x_probe(struct platform_device *pdev)
2378{
2379 struct clk *clk;
2380 struct device *dev = &pdev->dev;
2381
2382 /* Temporary until RPM clocks supported */
2383 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2384 if (IS_ERR(clk))
2385 return PTR_ERR(clk);
2386
2387 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2388 if (IS_ERR(clk))
2389 return PTR_ERR(clk);
2390
2391 return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2392}
2393
2394static int gcc_ipq806x_remove(struct platform_device *pdev)
2395{
2396 qcom_cc_remove(pdev);
2397 return 0;
2398}
2399
2400static struct platform_driver gcc_ipq806x_driver = {
2401 .probe = gcc_ipq806x_probe,
2402 .remove = gcc_ipq806x_remove,
2403 .driver = {
2404 .name = "gcc-ipq806x",
2405 .owner = THIS_MODULE,
2406 .of_match_table = gcc_ipq806x_match_table,
2407 },
2408};
2409
2410static int __init gcc_ipq806x_init(void)
2411{
2412 return platform_driver_register(&gcc_ipq806x_driver);
2413}
2414core_initcall(gcc_ipq806x_init);
2415
2416static void __exit gcc_ipq806x_exit(void)
2417{
2418 platform_driver_unregister(&gcc_ipq806x_driver);
2419}
2420module_exit(gcc_ipq806x_exit);
2421
2422MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2423MODULE_LICENSE("GPL v2");
2424MODULE_ALIAS("platform:gcc-ipq806x");
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index f4ffd91901f8..007534f7a2d7 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -104,6 +104,7 @@ static struct clk_regmap pll14_vote = {
104 104
105#define P_PXO 0 105#define P_PXO 0
106#define P_PLL8 1 106#define P_PLL8 1
107#define P_PLL3 2
107#define P_CXO 2 108#define P_CXO 2
108 109
109static const u8 gcc_pxo_pll8_map[] = { 110static const u8 gcc_pxo_pll8_map[] = {
@@ -128,6 +129,18 @@ static const char *gcc_pxo_pll8_cxo[] = {
128 "cxo", 129 "cxo",
129}; 130};
130 131
132static const u8 gcc_pxo_pll8_pll3_map[] = {
133 [P_PXO] = 0,
134 [P_PLL8] = 3,
135 [P_PLL3] = 6,
136};
137
138static const char *gcc_pxo_pll8_pll3[] = {
139 "pxo",
140 "pll8_vote",
141 "pll3",
142};
143
131static struct freq_tbl clk_tbl_gsbi_uart[] = { 144static struct freq_tbl clk_tbl_gsbi_uart[] = {
132 { 1843200, P_PLL8, 2, 6, 625 }, 145 { 1843200, P_PLL8, 2, 6, 625 },
133 { 3686400, P_PLL8, 2, 12, 625 }, 146 { 3686400, P_PLL8, 2, 12, 625 },
@@ -1928,6 +1941,104 @@ static struct clk_branch usb_hs1_xcvr_clk = {
1928 }, 1941 },
1929}; 1942};
1930 1943
1944static struct clk_rcg usb_hs3_xcvr_src = {
1945 .ns_reg = 0x370c,
1946 .md_reg = 0x3708,
1947 .mn = {
1948 .mnctr_en_bit = 8,
1949 .mnctr_reset_bit = 7,
1950 .mnctr_mode_shift = 5,
1951 .n_val_shift = 16,
1952 .m_val_shift = 16,
1953 .width = 8,
1954 },
1955 .p = {
1956 .pre_div_shift = 3,
1957 .pre_div_width = 2,
1958 },
1959 .s = {
1960 .src_sel_shift = 0,
1961 .parent_map = gcc_pxo_pll8_map,
1962 },
1963 .freq_tbl = clk_tbl_usb,
1964 .clkr = {
1965 .enable_reg = 0x370c,
1966 .enable_mask = BIT(11),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "usb_hs3_xcvr_src",
1969 .parent_names = gcc_pxo_pll8,
1970 .num_parents = 2,
1971 .ops = &clk_rcg_ops,
1972 .flags = CLK_SET_RATE_GATE,
1973 },
1974 }
1975};
1976
1977static struct clk_branch usb_hs3_xcvr_clk = {
1978 .halt_reg = 0x2fc8,
1979 .halt_bit = 30,
1980 .clkr = {
1981 .enable_reg = 0x370c,
1982 .enable_mask = BIT(9),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "usb_hs3_xcvr_clk",
1985 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1986 .num_parents = 1,
1987 .ops = &clk_branch_ops,
1988 .flags = CLK_SET_RATE_PARENT,
1989 },
1990 },
1991};
1992
1993static struct clk_rcg usb_hs4_xcvr_src = {
1994 .ns_reg = 0x372c,
1995 .md_reg = 0x3728,
1996 .mn = {
1997 .mnctr_en_bit = 8,
1998 .mnctr_reset_bit = 7,
1999 .mnctr_mode_shift = 5,
2000 .n_val_shift = 16,
2001 .m_val_shift = 16,
2002 .width = 8,
2003 },
2004 .p = {
2005 .pre_div_shift = 3,
2006 .pre_div_width = 2,
2007 },
2008 .s = {
2009 .src_sel_shift = 0,
2010 .parent_map = gcc_pxo_pll8_map,
2011 },
2012 .freq_tbl = clk_tbl_usb,
2013 .clkr = {
2014 .enable_reg = 0x372c,
2015 .enable_mask = BIT(11),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "usb_hs4_xcvr_src",
2018 .parent_names = gcc_pxo_pll8,
2019 .num_parents = 2,
2020 .ops = &clk_rcg_ops,
2021 .flags = CLK_SET_RATE_GATE,
2022 },
2023 }
2024};
2025
2026static struct clk_branch usb_hs4_xcvr_clk = {
2027 .halt_reg = 0x2fc8,
2028 .halt_bit = 2,
2029 .clkr = {
2030 .enable_reg = 0x372c,
2031 .enable_mask = BIT(9),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "usb_hs4_xcvr_clk",
2034 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2035 .num_parents = 1,
2036 .ops = &clk_branch_ops,
2037 .flags = CLK_SET_RATE_PARENT,
2038 },
2039 },
2040};
2041
1931static struct clk_rcg usb_hsic_xcvr_fs_src = { 2042static struct clk_rcg usb_hsic_xcvr_fs_src = {
1932 .ns_reg = 0x2928, 2043 .ns_reg = 0x2928,
1933 .md_reg = 0x2924, 2044 .md_reg = 0x2924,
@@ -2456,6 +2567,34 @@ static struct clk_branch usb_hs1_h_clk = {
2456 }, 2567 },
2457}; 2568};
2458 2569
2570static struct clk_branch usb_hs3_h_clk = {
2571 .halt_reg = 0x2fc8,
2572 .halt_bit = 31,
2573 .clkr = {
2574 .enable_reg = 0x3700,
2575 .enable_mask = BIT(4),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "usb_hs3_h_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2580 },
2581 },
2582};
2583
2584static struct clk_branch usb_hs4_h_clk = {
2585 .halt_reg = 0x2fc8,
2586 .halt_bit = 7,
2587 .clkr = {
2588 .enable_reg = 0x3720,
2589 .enable_mask = BIT(4),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "usb_hs4_h_clk",
2592 .ops = &clk_branch_ops,
2593 .flags = CLK_IS_ROOT,
2594 },
2595 },
2596};
2597
2459static struct clk_branch usb_hsic_h_clk = { 2598static struct clk_branch usb_hsic_h_clk = {
2460 .halt_reg = 0x2fcc, 2599 .halt_reg = 0x2fcc,
2461 .halt_bit = 28, 2600 .halt_bit = 28,
@@ -2582,6 +2721,244 @@ static struct clk_branch adm0_pbus_clk = {
2582 }, 2721 },
2583}; 2722};
2584 2723
2724static struct freq_tbl clk_tbl_ce3[] = {
2725 { 48000000, P_PLL8, 8 },
2726 { 100000000, P_PLL3, 12 },
2727 { 120000000, P_PLL3, 10 },
2728 { }
2729};
2730
2731static struct clk_rcg ce3_src = {
2732 .ns_reg = 0x36c0,
2733 .p = {
2734 .pre_div_shift = 3,
2735 .pre_div_width = 4,
2736 },
2737 .s = {
2738 .src_sel_shift = 0,
2739 .parent_map = gcc_pxo_pll8_pll3_map,
2740 },
2741 .freq_tbl = clk_tbl_ce3,
2742 .clkr = {
2743 .enable_reg = 0x2c08,
2744 .enable_mask = BIT(7),
2745 .hw.init = &(struct clk_init_data){
2746 .name = "ce3_src",
2747 .parent_names = gcc_pxo_pll8_pll3,
2748 .num_parents = 3,
2749 .ops = &clk_rcg_ops,
2750 .flags = CLK_SET_RATE_GATE,
2751 },
2752 },
2753};
2754
2755static struct clk_branch ce3_core_clk = {
2756 .halt_reg = 0x2fdc,
2757 .halt_bit = 5,
2758 .clkr = {
2759 .enable_reg = 0x36c4,
2760 .enable_mask = BIT(4),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "ce3_core_clk",
2763 .parent_names = (const char *[]){ "ce3_src" },
2764 .num_parents = 1,
2765 .ops = &clk_branch_ops,
2766 .flags = CLK_SET_RATE_PARENT,
2767 },
2768 },
2769};
2770
2771static struct clk_branch ce3_h_clk = {
2772 .halt_reg = 0x2fc4,
2773 .halt_bit = 16,
2774 .clkr = {
2775 .enable_reg = 0x36c4,
2776 .enable_mask = BIT(4),
2777 .hw.init = &(struct clk_init_data){
2778 .name = "ce3_h_clk",
2779 .parent_names = (const char *[]){ "ce3_src" },
2780 .num_parents = 1,
2781 .ops = &clk_branch_ops,
2782 .flags = CLK_SET_RATE_PARENT,
2783 },
2784 },
2785};
2786
2787static const struct freq_tbl clk_tbl_sata_ref[] = {
2788 { 48000000, P_PLL8, 8, 0, 0 },
2789 { 100000000, P_PLL3, 12, 0, 0 },
2790 { }
2791};
2792
2793static struct clk_rcg sata_clk_src = {
2794 .ns_reg = 0x2c08,
2795 .p = {
2796 .pre_div_shift = 3,
2797 .pre_div_width = 4,
2798 },
2799 .s = {
2800 .src_sel_shift = 0,
2801 .parent_map = gcc_pxo_pll8_pll3_map,
2802 },
2803 .freq_tbl = clk_tbl_sata_ref,
2804 .clkr = {
2805 .enable_reg = 0x2c08,
2806 .enable_mask = BIT(7),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "sata_clk_src",
2809 .parent_names = gcc_pxo_pll8_pll3,
2810 .num_parents = 3,
2811 .ops = &clk_rcg_ops,
2812 .flags = CLK_SET_RATE_GATE,
2813 },
2814 },
2815};
2816
2817static struct clk_branch sata_rxoob_clk = {
2818 .halt_reg = 0x2fdc,
2819 .halt_bit = 26,
2820 .clkr = {
2821 .enable_reg = 0x2c0c,
2822 .enable_mask = BIT(4),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "sata_rxoob_clk",
2825 .parent_names = (const char *[]){ "sata_clk_src" },
2826 .num_parents = 1,
2827 .ops = &clk_branch_ops,
2828 .flags = CLK_SET_RATE_PARENT,
2829 },
2830 },
2831};
2832
2833static struct clk_branch sata_pmalive_clk = {
2834 .halt_reg = 0x2fdc,
2835 .halt_bit = 25,
2836 .clkr = {
2837 .enable_reg = 0x2c10,
2838 .enable_mask = BIT(4),
2839 .hw.init = &(struct clk_init_data){
2840 .name = "sata_pmalive_clk",
2841 .parent_names = (const char *[]){ "sata_clk_src" },
2842 .num_parents = 1,
2843 .ops = &clk_branch_ops,
2844 .flags = CLK_SET_RATE_PARENT,
2845 },
2846 },
2847};
2848
2849static struct clk_branch sata_phy_ref_clk = {
2850 .halt_reg = 0x2fdc,
2851 .halt_bit = 24,
2852 .clkr = {
2853 .enable_reg = 0x2c14,
2854 .enable_mask = BIT(4),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "sata_phy_ref_clk",
2857 .parent_names = (const char *[]){ "pxo" },
2858 .num_parents = 1,
2859 .ops = &clk_branch_ops,
2860 },
2861 },
2862};
2863
2864static struct clk_branch sata_a_clk = {
2865 .halt_reg = 0x2fc0,
2866 .halt_bit = 12,
2867 .clkr = {
2868 .enable_reg = 0x2c20,
2869 .enable_mask = BIT(4),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "sata_a_clk",
2872 .ops = &clk_branch_ops,
2873 .flags = CLK_IS_ROOT,
2874 },
2875 },
2876};
2877
2878static struct clk_branch sata_h_clk = {
2879 .halt_reg = 0x2fdc,
2880 .halt_bit = 27,
2881 .clkr = {
2882 .enable_reg = 0x2c00,
2883 .enable_mask = BIT(4),
2884 .hw.init = &(struct clk_init_data){
2885 .name = "sata_h_clk",
2886 .ops = &clk_branch_ops,
2887 .flags = CLK_IS_ROOT,
2888 },
2889 },
2890};
2891
2892static struct clk_branch sfab_sata_s_h_clk = {
2893 .halt_reg = 0x2fc4,
2894 .halt_bit = 14,
2895 .clkr = {
2896 .enable_reg = 0x2480,
2897 .enable_mask = BIT(4),
2898 .hw.init = &(struct clk_init_data){
2899 .name = "sfab_sata_s_h_clk",
2900 .ops = &clk_branch_ops,
2901 .flags = CLK_IS_ROOT,
2902 },
2903 },
2904};
2905
2906static struct clk_branch sata_phy_cfg_clk = {
2907 .halt_reg = 0x2fcc,
2908 .halt_bit = 12,
2909 .clkr = {
2910 .enable_reg = 0x2c40,
2911 .enable_mask = BIT(4),
2912 .hw.init = &(struct clk_init_data){
2913 .name = "sata_phy_cfg_clk",
2914 .ops = &clk_branch_ops,
2915 .flags = CLK_IS_ROOT,
2916 },
2917 },
2918};
2919
2920static struct clk_branch pcie_phy_ref_clk = {
2921 .halt_reg = 0x2fdc,
2922 .halt_bit = 29,
2923 .clkr = {
2924 .enable_reg = 0x22d0,
2925 .enable_mask = BIT(4),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "pcie_phy_ref_clk",
2928 .ops = &clk_branch_ops,
2929 .flags = CLK_IS_ROOT,
2930 },
2931 },
2932};
2933
2934static struct clk_branch pcie_h_clk = {
2935 .halt_reg = 0x2fd4,
2936 .halt_bit = 8,
2937 .clkr = {
2938 .enable_reg = 0x22cc,
2939 .enable_mask = BIT(4),
2940 .hw.init = &(struct clk_init_data){
2941 .name = "pcie_h_clk",
2942 .ops = &clk_branch_ops,
2943 .flags = CLK_IS_ROOT,
2944 },
2945 },
2946};
2947
2948static struct clk_branch pcie_a_clk = {
2949 .halt_reg = 0x2fc0,
2950 .halt_bit = 13,
2951 .clkr = {
2952 .enable_reg = 0x22c0,
2953 .enable_mask = BIT(4),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "pcie_a_clk",
2956 .ops = &clk_branch_ops,
2957 .flags = CLK_IS_ROOT,
2958 },
2959 },
2960};
2961
2585static struct clk_branch pmic_arb0_h_clk = { 2962static struct clk_branch pmic_arb0_h_clk = {
2586 .halt_reg = 0x2fd8, 2963 .halt_reg = 0x2fd8,
2587 .halt_check = BRANCH_HALT_VOTED, 2964 .halt_check = BRANCH_HALT_VOTED,
@@ -2869,13 +3246,205 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
2869}; 3246};
2870 3247
2871static struct clk_regmap *gcc_apq8064_clks[] = { 3248static struct clk_regmap *gcc_apq8064_clks[] = {
3249 [PLL3] = &pll3.clkr,
2872 [PLL8] = &pll8.clkr, 3250 [PLL8] = &pll8.clkr,
2873 [PLL8_VOTE] = &pll8_vote, 3251 [PLL8_VOTE] = &pll8_vote,
3252 [PLL14] = &pll14.clkr,
3253 [PLL14_VOTE] = &pll14_vote,
3254 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3255 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3256 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3257 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3258 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3259 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3260 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3261 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3262 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3263 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3264 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3265 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2874 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 3266 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2875 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 3267 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3268 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3269 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3270 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3271 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3272 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3273 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3274 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3275 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3276 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3277 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3278 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3279 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2876 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 3280 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2877 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 3281 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3282 [GP0_SRC] = &gp0_src.clkr,
3283 [GP0_CLK] = &gp0_clk.clkr,
3284 [GP1_SRC] = &gp1_src.clkr,
3285 [GP1_CLK] = &gp1_clk.clkr,
3286 [GP2_SRC] = &gp2_src.clkr,
3287 [GP2_CLK] = &gp2_clk.clkr,
3288 [PMEM_A_CLK] = &pmem_clk.clkr,
3289 [PRNG_SRC] = &prng_src.clkr,
3290 [PRNG_CLK] = &prng_clk.clkr,
3291 [SDC1_SRC] = &sdc1_src.clkr,
3292 [SDC1_CLK] = &sdc1_clk.clkr,
3293 [SDC2_SRC] = &sdc2_src.clkr,
3294 [SDC2_CLK] = &sdc2_clk.clkr,
3295 [SDC3_SRC] = &sdc3_src.clkr,
3296 [SDC3_CLK] = &sdc3_clk.clkr,
3297 [SDC4_SRC] = &sdc4_src.clkr,
3298 [SDC4_CLK] = &sdc4_clk.clkr,
3299 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3300 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3301 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3302 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3303 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3304 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3305 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3306 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3307 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3308 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3309 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3310 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3311 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3312 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3313 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3314 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3315 [SATA_H_CLK] = &sata_h_clk.clkr,
3316 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3317 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3318 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3319 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3320 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3321 [SATA_A_CLK] = &sata_a_clk.clkr,
3322 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3323 [CE3_SRC] = &ce3_src.clkr,
3324 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3325 [CE3_H_CLK] = &ce3_h_clk.clkr,
3326 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3327 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3328 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3329 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3330 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3331 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3332 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2878 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 3333 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3334 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3335 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3336 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3337 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3338 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3339 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3340 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3341 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3342 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3343 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3344 [ADM0_CLK] = &adm0_clk.clkr,
3345 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3346 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3347 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3348 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3349 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3350 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3351 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3352 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3353};
3354
3355static const struct qcom_reset_map gcc_apq8064_resets[] = {
3356 [QDSS_STM_RESET] = { 0x2060, 6 },
3357 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3358 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3359 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3360 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3361 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3362 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3363 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3364 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3365 [ADM0_C2_RESET] = { 0x220c, 4},
3366 [ADM0_C1_RESET] = { 0x220c, 3},
3367 [ADM0_C0_RESET] = { 0x220c, 2},
3368 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3369 [ADM0_RESET] = { 0x220c },
3370 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3371 [QDSS_POR_RESET] = { 0x2260, 4 },
3372 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3373 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3374 [QDSS_AXI_RESET] = { 0x2260, 1 },
3375 [QDSS_DBG_RESET] = { 0x2260 },
3376 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3377 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3378 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3379 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3380 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3381 [PCIE_POR_RESET] = { 0x22dc, 3 },
3382 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3383 [PCIE_ACLK_RESET] = { 0x22dc },
3384 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3385 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3386 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3387 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3388 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3389 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3390 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3391 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3392 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3393 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3394 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3395 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3396 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3397 [PPSS_PROC_RESET] = { 0x2594, 1 },
3398 [PPSS_RESET] = { 0x2594},
3399 [DMA_BAM_RESET] = { 0x25c0, 7 },
3400 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3401 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3402 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3403 [TSIF_H_RESET] = { 0x2700, 7 },
3404 [CE1_H_RESET] = { 0x2720, 7 },
3405 [CE1_CORE_RESET] = { 0x2724, 7 },
3406 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3407 [CE2_H_RESET] = { 0x2740, 7 },
3408 [CE2_CORE_RESET] = { 0x2744, 7 },
3409 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3410 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3411 [RPM_PROC_RESET] = { 0x27c0, 7 },
3412 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3413 [SDC1_RESET] = { 0x2830 },
3414 [SDC2_RESET] = { 0x2850 },
3415 [SDC3_RESET] = { 0x2870 },
3416 [SDC4_RESET] = { 0x2890 },
3417 [USB_HS1_RESET] = { 0x2910 },
3418 [USB_HSIC_RESET] = { 0x2934 },
3419 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3420 [USB_FS1_RESET] = { 0x2974 },
3421 [GSBI1_RESET] = { 0x29dc },
3422 [GSBI2_RESET] = { 0x29fc },
3423 [GSBI3_RESET] = { 0x2a1c },
3424 [GSBI4_RESET] = { 0x2a3c },
3425 [GSBI5_RESET] = { 0x2a5c },
3426 [GSBI6_RESET] = { 0x2a7c },
3427 [GSBI7_RESET] = { 0x2a9c },
3428 [SPDM_RESET] = { 0x2b6c },
3429 [TLMM_H_RESET] = { 0x2ba0, 7 },
3430 [SATA_SFAB_M_RESET] = { 0x2c18 },
3431 [SATA_RESET] = { 0x2c1c },
3432 [GSS_SLP_RESET] = { 0x2c60, 7 },
3433 [GSS_RESET] = { 0x2c64 },
3434 [TSSC_RESET] = { 0x2ca0, 7 },
3435 [PDM_RESET] = { 0x2cc0, 12 },
3436 [MPM_H_RESET] = { 0x2da0, 7 },
3437 [MPM_RESET] = { 0x2da4 },
3438 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3439 [PRNG_RESET] = { 0x2e80, 12 },
3440 [RIVA_RESET] = { 0x35e0 },
3441 [CE3_H_RESET] = { 0x36c4, 7 },
3442 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3443 [SFAB_CE3_S_RESET] = { 0x36c8 },
3444 [CE3_RESET] = { 0x36cc, 7 },
3445 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3446 [USB_HS3_RESET] = { 0x3710 },
3447 [USB_HS4_RESET] = { 0x3730 },
2879}; 3448};
2880 3449
2881static const struct regmap_config gcc_msm8960_regmap_config = { 3450static const struct regmap_config gcc_msm8960_regmap_config = {
@@ -2886,6 +3455,14 @@ static const struct regmap_config gcc_msm8960_regmap_config = {
2886 .fast_io = true, 3455 .fast_io = true,
2887}; 3456};
2888 3457
3458static const struct regmap_config gcc_apq8064_regmap_config = {
3459 .reg_bits = 32,
3460 .reg_stride = 4,
3461 .val_bits = 32,
3462 .max_register = 0x3880,
3463 .fast_io = true,
3464};
3465
2889static const struct qcom_cc_desc gcc_msm8960_desc = { 3466static const struct qcom_cc_desc gcc_msm8960_desc = {
2890 .config = &gcc_msm8960_regmap_config, 3467 .config = &gcc_msm8960_regmap_config,
2891 .clks = gcc_msm8960_clks, 3468 .clks = gcc_msm8960_clks,
@@ -2895,11 +3472,11 @@ static const struct qcom_cc_desc gcc_msm8960_desc = {
2895}; 3472};
2896 3473
2897static const struct qcom_cc_desc gcc_apq8064_desc = { 3474static const struct qcom_cc_desc gcc_apq8064_desc = {
2898 .config = &gcc_msm8960_regmap_config, 3475 .config = &gcc_apq8064_regmap_config,
2899 .clks = gcc_apq8064_clks, 3476 .clks = gcc_apq8064_clks,
2900 .num_clks = ARRAY_SIZE(gcc_apq8064_clks), 3477 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
2901 .resets = gcc_msm8960_resets, 3478 .resets = gcc_apq8064_resets,
2902 .num_resets = ARRAY_SIZE(gcc_msm8960_resets), 3479 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
2903}; 3480};
2904 3481
2905static const struct of_device_id gcc_msm8960_match_table[] = { 3482static const struct of_device_id gcc_msm8960_match_table[] = {
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
new file mode 100644
index 000000000000..751eea376a2b
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -0,0 +1,3352 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/module.h>
17#include <linux/regmap.h>
18#include <linux/reset-controller.h>
19
20#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
22
23#include "common.h"
24#include "clk-regmap.h"
25#include "clk-pll.h"
26#include "clk-rcg.h"
27#include "clk-branch.h"
28#include "reset.h"
29
30#define P_XO 0
31#define P_MMPLL0 1
32#define P_EDPLINK 1
33#define P_MMPLL1 2
34#define P_HDMIPLL 2
35#define P_GPLL0 3
36#define P_EDPVCO 3
37#define P_MMPLL4 4
38#define P_DSI0PLL 4
39#define P_DSI0PLL_BYTE 4
40#define P_MMPLL2 4
41#define P_MMPLL3 4
42#define P_GPLL1 5
43#define P_DSI1PLL 5
44#define P_DSI1PLL_BYTE 5
45#define P_MMSLEEP 6
46
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
48 [P_XO] = 0,
49 [P_MMPLL0] = 1,
50 [P_MMPLL1] = 2,
51 [P_GPLL0] = 5,
52};
53
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
55 "xo",
56 "mmpll0_vote",
57 "mmpll1_vote",
58 "mmss_gpll0_vote",
59};
60
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0,
63 [P_MMPLL0] = 1,
64 [P_HDMIPLL] = 4,
65 [P_GPLL0] = 5,
66 [P_DSI0PLL] = 2,
67 [P_DSI1PLL] = 3,
68};
69
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
71 "xo",
72 "mmpll0_vote",
73 "hdmipll",
74 "mmss_gpll0_vote",
75 "dsi0pll",
76 "dsi1pll",
77};
78
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0,
81 [P_MMPLL0] = 1,
82 [P_MMPLL1] = 2,
83 [P_GPLL0] = 5,
84 [P_MMPLL2] = 3,
85};
86
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
88 "xo",
89 "mmpll0_vote",
90 "mmpll1_vote",
91 "mmss_gpll0_vote",
92 "mmpll2",
93};
94
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0,
97 [P_MMPLL0] = 1,
98 [P_MMPLL1] = 2,
99 [P_GPLL0] = 5,
100 [P_MMPLL3] = 3,
101};
102
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
104 "xo",
105 "mmpll0_vote",
106 "mmpll1_vote",
107 "mmss_gpll0_vote",
108 "mmpll3",
109};
110
111static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
112 [P_XO] = 0,
113 [P_EDPLINK] = 4,
114 [P_HDMIPLL] = 3,
115 [P_EDPVCO] = 5,
116 [P_DSI0PLL] = 1,
117 [P_DSI1PLL] = 2,
118};
119
120static const char *mmcc_xo_dsi_hdmi_edp[] = {
121 "xo",
122 "edp_link_clk",
123 "hdmipll",
124 "edp_vco_div",
125 "dsi0pll",
126 "dsi1pll",
127};
128
129static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
130 [P_XO] = 0,
131 [P_EDPLINK] = 4,
132 [P_HDMIPLL] = 3,
133 [P_GPLL0] = 5,
134 [P_DSI0PLL] = 1,
135 [P_DSI1PLL] = 2,
136};
137
138static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
139 "xo",
140 "edp_link_clk",
141 "hdmipll",
142 "gpll0_vote",
143 "dsi0pll",
144 "dsi1pll",
145};
146
147static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
148 [P_XO] = 0,
149 [P_EDPLINK] = 4,
150 [P_HDMIPLL] = 3,
151 [P_GPLL0] = 5,
152 [P_DSI0PLL_BYTE] = 1,
153 [P_DSI1PLL_BYTE] = 2,
154};
155
156static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
157 "xo",
158 "edp_link_clk",
159 "hdmipll",
160 "gpll0_vote",
161 "dsi0pllbyte",
162 "dsi1pllbyte",
163};
164
165static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
166 [P_XO] = 0,
167 [P_MMPLL0] = 1,
168 [P_MMPLL1] = 2,
169 [P_GPLL0] = 5,
170 [P_MMPLL4] = 3,
171};
172
173static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
174 "xo",
175 "mmpll0",
176 "mmpll1",
177 "mmpll4",
178 "gpll0",
179};
180
181static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
182 [P_XO] = 0,
183 [P_MMPLL0] = 1,
184 [P_MMPLL1] = 2,
185 [P_MMPLL4] = 3,
186 [P_GPLL0] = 5,
187 [P_GPLL1] = 4,
188};
189
190static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
191 "xo",
192 "mmpll0",
193 "mmpll1",
194 "mmpll4",
195 "gpll1",
196 "gpll0",
197};
198
199static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
200 [P_XO] = 0,
201 [P_MMPLL0] = 1,
202 [P_MMPLL1] = 2,
203 [P_MMPLL4] = 3,
204 [P_GPLL0] = 5,
205 [P_GPLL1] = 4,
206 [P_MMSLEEP] = 6,
207};
208
209static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
210 "xo",
211 "mmpll0",
212 "mmpll1",
213 "mmpll4",
214 "gpll1",
215 "gpll0",
216 "sleep_clk_src",
217};
218
219#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
220
221static struct clk_pll mmpll0 = {
222 .l_reg = 0x0004,
223 .m_reg = 0x0008,
224 .n_reg = 0x000c,
225 .config_reg = 0x0014,
226 .mode_reg = 0x0000,
227 .status_reg = 0x001c,
228 .status_bit = 17,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "mmpll0",
231 .parent_names = (const char *[]){ "xo" },
232 .num_parents = 1,
233 .ops = &clk_pll_ops,
234 },
235};
236
237static struct clk_regmap mmpll0_vote = {
238 .enable_reg = 0x0100,
239 .enable_mask = BIT(0),
240 .hw.init = &(struct clk_init_data){
241 .name = "mmpll0_vote",
242 .parent_names = (const char *[]){ "mmpll0" },
243 .num_parents = 1,
244 .ops = &clk_pll_vote_ops,
245 },
246};
247
248static struct clk_pll mmpll1 = {
249 .l_reg = 0x0044,
250 .m_reg = 0x0048,
251 .n_reg = 0x004c,
252 .config_reg = 0x0050,
253 .mode_reg = 0x0040,
254 .status_reg = 0x005c,
255 .status_bit = 17,
256 .clkr.hw.init = &(struct clk_init_data){
257 .name = "mmpll1",
258 .parent_names = (const char *[]){ "xo" },
259 .num_parents = 1,
260 .ops = &clk_pll_ops,
261 },
262};
263
264static struct clk_regmap mmpll1_vote = {
265 .enable_reg = 0x0100,
266 .enable_mask = BIT(1),
267 .hw.init = &(struct clk_init_data){
268 .name = "mmpll1_vote",
269 .parent_names = (const char *[]){ "mmpll1" },
270 .num_parents = 1,
271 .ops = &clk_pll_vote_ops,
272 },
273};
274
275static struct clk_pll mmpll2 = {
276 .l_reg = 0x4104,
277 .m_reg = 0x4108,
278 .n_reg = 0x410c,
279 .config_reg = 0x4110,
280 .mode_reg = 0x4100,
281 .status_reg = 0x411c,
282 .clkr.hw.init = &(struct clk_init_data){
283 .name = "mmpll2",
284 .parent_names = (const char *[]){ "xo" },
285 .num_parents = 1,
286 .ops = &clk_pll_ops,
287 },
288};
289
290static struct clk_pll mmpll3 = {
291 .l_reg = 0x0084,
292 .m_reg = 0x0088,
293 .n_reg = 0x008c,
294 .config_reg = 0x0090,
295 .mode_reg = 0x0080,
296 .status_reg = 0x009c,
297 .status_bit = 17,
298 .clkr.hw.init = &(struct clk_init_data){
299 .name = "mmpll3",
300 .parent_names = (const char *[]){ "xo" },
301 .num_parents = 1,
302 .ops = &clk_pll_ops,
303 },
304};
305
306static struct clk_pll mmpll4 = {
307 .l_reg = 0x00a4,
308 .m_reg = 0x00a8,
309 .n_reg = 0x00ac,
310 .config_reg = 0x00b0,
311 .mode_reg = 0x0080,
312 .status_reg = 0x00bc,
313 .clkr.hw.init = &(struct clk_init_data){
314 .name = "mmpll4",
315 .parent_names = (const char *[]){ "xo" },
316 .num_parents = 1,
317 .ops = &clk_pll_ops,
318 },
319};
320
321static struct clk_rcg2 mmss_ahb_clk_src = {
322 .cmd_rcgr = 0x5000,
323 .hid_width = 5,
324 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
325 .clkr.hw.init = &(struct clk_init_data){
326 .name = "mmss_ahb_clk_src",
327 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
328 .num_parents = 4,
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct freq_tbl ftbl_mmss_axi_clk[] = {
334 F(19200000, P_XO, 1, 0, 0),
335 F(37500000, P_GPLL0, 16, 0, 0),
336 F(50000000, P_GPLL0, 12, 0, 0),
337 F(75000000, P_GPLL0, 8, 0, 0),
338 F(100000000, P_GPLL0, 6, 0, 0),
339 F(150000000, P_GPLL0, 4, 0, 0),
340 F(333430000, P_MMPLL1, 3.5, 0, 0),
341 F(400000000, P_MMPLL0, 2, 0, 0),
342 F(466800000, P_MMPLL1, 2.5, 0, 0),
343};
344
345static struct clk_rcg2 mmss_axi_clk_src = {
346 .cmd_rcgr = 0x5040,
347 .hid_width = 5,
348 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
349 .freq_tbl = ftbl_mmss_axi_clk,
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "mmss_axi_clk_src",
352 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
353 .num_parents = 4,
354 .ops = &clk_rcg2_ops,
355 },
356};
357
358static struct freq_tbl ftbl_ocmemnoc_clk[] = {
359 F(19200000, P_XO, 1, 0, 0),
360 F(37500000, P_GPLL0, 16, 0, 0),
361 F(50000000, P_GPLL0, 12, 0, 0),
362 F(75000000, P_GPLL0, 8, 0, 0),
363 F(109090000, P_GPLL0, 5.5, 0, 0),
364 F(150000000, P_GPLL0, 4, 0, 0),
365 F(228570000, P_MMPLL0, 3.5, 0, 0),
366 F(320000000, P_MMPLL0, 2.5, 0, 0),
367};
368
369static struct clk_rcg2 ocmemnoc_clk_src = {
370 .cmd_rcgr = 0x5090,
371 .hid_width = 5,
372 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
373 .freq_tbl = ftbl_ocmemnoc_clk,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "ocmemnoc_clk_src",
376 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
377 .num_parents = 4,
378 .ops = &clk_rcg2_ops,
379 },
380};
381
382static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
383 F(100000000, P_GPLL0, 6, 0, 0),
384 F(200000000, P_MMPLL0, 4, 0, 0),
385 { }
386};
387
388static struct clk_rcg2 csi0_clk_src = {
389 .cmd_rcgr = 0x3090,
390 .hid_width = 5,
391 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
392 .freq_tbl = ftbl_camss_csi0_3_clk,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "csi0_clk_src",
395 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
396 .num_parents = 5,
397 .ops = &clk_rcg2_ops,
398 },
399};
400
401static struct clk_rcg2 csi1_clk_src = {
402 .cmd_rcgr = 0x3100,
403 .hid_width = 5,
404 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
405 .freq_tbl = ftbl_camss_csi0_3_clk,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "csi1_clk_src",
408 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
409 .num_parents = 5,
410 .ops = &clk_rcg2_ops,
411 },
412};
413
414static struct clk_rcg2 csi2_clk_src = {
415 .cmd_rcgr = 0x3160,
416 .hid_width = 5,
417 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
418 .freq_tbl = ftbl_camss_csi0_3_clk,
419 .clkr.hw.init = &(struct clk_init_data){
420 .name = "csi2_clk_src",
421 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
422 .num_parents = 5,
423 .ops = &clk_rcg2_ops,
424 },
425};
426
427static struct clk_rcg2 csi3_clk_src = {
428 .cmd_rcgr = 0x31c0,
429 .hid_width = 5,
430 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
431 .freq_tbl = ftbl_camss_csi0_3_clk,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "csi3_clk_src",
434 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
435 .num_parents = 5,
436 .ops = &clk_rcg2_ops,
437 },
438};
439
440static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
441 F(37500000, P_GPLL0, 16, 0, 0),
442 F(50000000, P_GPLL0, 12, 0, 0),
443 F(60000000, P_GPLL0, 10, 0, 0),
444 F(80000000, P_GPLL0, 7.5, 0, 0),
445 F(100000000, P_GPLL0, 6, 0, 0),
446 F(109090000, P_GPLL0, 5.5, 0, 0),
447 F(133330000, P_GPLL0, 4.5, 0, 0),
448 F(200000000, P_GPLL0, 3, 0, 0),
449 F(228570000, P_MMPLL0, 3.5, 0, 0),
450 F(266670000, P_MMPLL0, 3, 0, 0),
451 F(320000000, P_MMPLL0, 2.5, 0, 0),
452 F(465000000, P_MMPLL4, 2, 0, 0),
453 F(600000000, P_GPLL0, 1, 0, 0),
454 { }
455};
456
457static struct clk_rcg2 vfe0_clk_src = {
458 .cmd_rcgr = 0x3600,
459 .hid_width = 5,
460 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
461 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
462 .clkr.hw.init = &(struct clk_init_data){
463 .name = "vfe0_clk_src",
464 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
465 .num_parents = 5,
466 .ops = &clk_rcg2_ops,
467 },
468};
469
470static struct clk_rcg2 vfe1_clk_src = {
471 .cmd_rcgr = 0x3620,
472 .hid_width = 5,
473 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
474 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "vfe1_clk_src",
477 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
478 .num_parents = 5,
479 .ops = &clk_rcg2_ops,
480 },
481};
482
483static struct freq_tbl ftbl_mdss_mdp_clk[] = {
484 F(37500000, P_GPLL0, 16, 0, 0),
485 F(60000000, P_GPLL0, 10, 0, 0),
486 F(75000000, P_GPLL0, 8, 0, 0),
487 F(85710000, P_GPLL0, 7, 0, 0),
488 F(100000000, P_GPLL0, 6, 0, 0),
489 F(150000000, P_GPLL0, 4, 0, 0),
490 F(160000000, P_MMPLL0, 5, 0, 0),
491 F(200000000, P_MMPLL0, 4, 0, 0),
492 F(228570000, P_MMPLL0, 3.5, 0, 0),
493 F(300000000, P_GPLL0, 2, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
495 { }
496};
497
498static struct clk_rcg2 mdp_clk_src = {
499 .cmd_rcgr = 0x2040,
500 .hid_width = 5,
501 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
502 .freq_tbl = ftbl_mdss_mdp_clk,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "mdp_clk_src",
505 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
506 .num_parents = 6,
507 .ops = &clk_rcg2_ops,
508 },
509};
510
511static struct clk_rcg2 gfx3d_clk_src = {
512 .cmd_rcgr = 0x4000,
513 .hid_width = 5,
514 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "gfx3d_clk_src",
517 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
518 .num_parents = 5,
519 .ops = &clk_rcg2_ops,
520 },
521};
522
523static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
524 F(75000000, P_GPLL0, 8, 0, 0),
525 F(133330000, P_GPLL0, 4.5, 0, 0),
526 F(200000000, P_GPLL0, 3, 0, 0),
527 F(228570000, P_MMPLL0, 3.5, 0, 0),
528 F(266670000, P_MMPLL0, 3, 0, 0),
529 F(320000000, P_MMPLL0, 2.5, 0, 0),
530 { }
531};
532
533static struct clk_rcg2 jpeg0_clk_src = {
534 .cmd_rcgr = 0x3500,
535 .hid_width = 5,
536 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
537 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "jpeg0_clk_src",
540 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
541 .num_parents = 5,
542 .ops = &clk_rcg2_ops,
543 },
544};
545
546static struct clk_rcg2 jpeg1_clk_src = {
547 .cmd_rcgr = 0x3520,
548 .hid_width = 5,
549 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
550 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "jpeg1_clk_src",
553 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
554 .num_parents = 5,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 jpeg2_clk_src = {
560 .cmd_rcgr = 0x3540,
561 .hid_width = 5,
562 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
563 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "jpeg2_clk_src",
566 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
567 .num_parents = 5,
568 .ops = &clk_rcg2_ops,
569 },
570};
571
572static struct freq_tbl pixel_freq_tbl[] = {
573 { .src = P_DSI0PLL },
574 { }
575};
576
577static struct clk_rcg2 pclk0_clk_src = {
578 .cmd_rcgr = 0x2000,
579 .mnd_width = 8,
580 .hid_width = 5,
581 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
582 .freq_tbl = pixel_freq_tbl,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "pclk0_clk_src",
585 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
586 .num_parents = 6,
587 .ops = &clk_pixel_ops,
588 .flags = CLK_SET_RATE_PARENT,
589 },
590};
591
592static struct clk_rcg2 pclk1_clk_src = {
593 .cmd_rcgr = 0x2020,
594 .mnd_width = 8,
595 .hid_width = 5,
596 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
597 .freq_tbl = pixel_freq_tbl,
598 .clkr.hw.init = &(struct clk_init_data){
599 .name = "pclk1_clk_src",
600 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
601 .num_parents = 6,
602 .ops = &clk_pixel_ops,
603 .flags = CLK_SET_RATE_PARENT,
604 },
605};
606
607static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
608 F(50000000, P_GPLL0, 12, 0, 0),
609 F(100000000, P_GPLL0, 6, 0, 0),
610 F(133330000, P_GPLL0, 4.5, 0, 0),
611 F(200000000, P_MMPLL0, 4, 0, 0),
612 F(266670000, P_MMPLL0, 3, 0, 0),
613 F(465000000, P_MMPLL3, 2, 0, 0),
614 { }
615};
616
617static struct clk_rcg2 vcodec0_clk_src = {
618 .cmd_rcgr = 0x1000,
619 .mnd_width = 8,
620 .hid_width = 5,
621 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
622 .freq_tbl = ftbl_venus0_vcodec0_clk,
623 .clkr.hw.init = &(struct clk_init_data){
624 .name = "vcodec0_clk_src",
625 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
626 .num_parents = 5,
627 .ops = &clk_rcg2_ops,
628 },
629};
630
631static struct freq_tbl ftbl_avsync_vp_clk[] = {
632 F(150000000, P_GPLL0, 4, 0, 0),
633 F(320000000, P_MMPLL0, 2.5, 0, 0),
634 { }
635};
636
637static struct clk_rcg2 vp_clk_src = {
638 .cmd_rcgr = 0x2430,
639 .hid_width = 5,
640 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
641 .freq_tbl = ftbl_avsync_vp_clk,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "vp_clk_src",
644 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
645 .num_parents = 4,
646 .ops = &clk_rcg2_ops,
647 },
648};
649
650static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
651 F(19200000, P_XO, 1, 0, 0),
652 { }
653};
654
655static struct clk_rcg2 cci_clk_src = {
656 .cmd_rcgr = 0x3300,
657 .mnd_width = 8,
658 .hid_width = 5,
659 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
660 .freq_tbl = ftbl_camss_cci_cci_clk,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "cci_clk_src",
663 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
664 .num_parents = 6,
665 .ops = &clk_rcg2_ops,
666 },
667};
668
669static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
670 F(10000, P_XO, 16, 1, 120),
671 F(24000, P_XO, 16, 1, 50),
672 F(6000000, P_GPLL0, 10, 1, 10),
673 F(12000000, P_GPLL0, 10, 1, 5),
674 F(13000000, P_GPLL0, 4, 13, 150),
675 F(24000000, P_GPLL0, 5, 1, 5),
676 { }
677};
678
679static struct clk_rcg2 camss_gp0_clk_src = {
680 .cmd_rcgr = 0x3420,
681 .mnd_width = 8,
682 .hid_width = 5,
683 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
684 .freq_tbl = ftbl_camss_gp0_1_clk,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "camss_gp0_clk_src",
687 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
688 .num_parents = 7,
689 .ops = &clk_rcg2_ops,
690 },
691};
692
693static struct clk_rcg2 camss_gp1_clk_src = {
694 .cmd_rcgr = 0x3450,
695 .mnd_width = 8,
696 .hid_width = 5,
697 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
698 .freq_tbl = ftbl_camss_gp0_1_clk,
699 .clkr.hw.init = &(struct clk_init_data){
700 .name = "camss_gp1_clk_src",
701 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
702 .num_parents = 7,
703 .ops = &clk_rcg2_ops,
704 },
705};
706
707static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
708 F(4800000, P_XO, 4, 0, 0),
709 F(6000000, P_GPLL0, 10, 1, 10),
710 F(8000000, P_GPLL0, 15, 1, 5),
711 F(9600000, P_XO, 2, 0, 0),
712 F(16000000, P_MMPLL0, 10, 1, 5),
713 F(19200000, P_XO, 1, 0, 0),
714 F(24000000, P_GPLL0, 5, 1, 5),
715 F(32000000, P_MMPLL0, 5, 1, 5),
716 F(48000000, P_GPLL0, 12.5, 0, 0),
717 F(64000000, P_MMPLL0, 12.5, 0, 0),
718 { }
719};
720
721static struct clk_rcg2 mclk0_clk_src = {
722 .cmd_rcgr = 0x3360,
723 .mnd_width = 8,
724 .hid_width = 5,
725 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
726 .freq_tbl = ftbl_camss_mclk0_3_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "mclk0_clk_src",
729 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
730 .num_parents = 6,
731 .ops = &clk_rcg2_ops,
732 },
733};
734
735static struct clk_rcg2 mclk1_clk_src = {
736 .cmd_rcgr = 0x3390,
737 .mnd_width = 8,
738 .hid_width = 5,
739 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
740 .freq_tbl = ftbl_camss_mclk0_3_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "mclk1_clk_src",
743 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
744 .num_parents = 6,
745 .ops = &clk_rcg2_ops,
746 },
747};
748
749static struct clk_rcg2 mclk2_clk_src = {
750 .cmd_rcgr = 0x33c0,
751 .mnd_width = 8,
752 .hid_width = 5,
753 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
754 .freq_tbl = ftbl_camss_mclk0_3_clk,
755 .clkr.hw.init = &(struct clk_init_data){
756 .name = "mclk2_clk_src",
757 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
758 .num_parents = 6,
759 .ops = &clk_rcg2_ops,
760 },
761};
762
763static struct clk_rcg2 mclk3_clk_src = {
764 .cmd_rcgr = 0x33f0,
765 .mnd_width = 8,
766 .hid_width = 5,
767 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
768 .freq_tbl = ftbl_camss_mclk0_3_clk,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "mclk3_clk_src",
771 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
772 .num_parents = 6,
773 .ops = &clk_rcg2_ops,
774 },
775};
776
777static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
778 F(100000000, P_GPLL0, 6, 0, 0),
779 F(200000000, P_MMPLL0, 4, 0, 0),
780 { }
781};
782
783static struct clk_rcg2 csi0phytimer_clk_src = {
784 .cmd_rcgr = 0x3000,
785 .hid_width = 5,
786 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
787 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "csi0phytimer_clk_src",
790 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
791 .num_parents = 5,
792 .ops = &clk_rcg2_ops,
793 },
794};
795
796static struct clk_rcg2 csi1phytimer_clk_src = {
797 .cmd_rcgr = 0x3030,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
800 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "csi1phytimer_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 5,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct clk_rcg2 csi2phytimer_clk_src = {
810 .cmd_rcgr = 0x3060,
811 .hid_width = 5,
812 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
813 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "csi2phytimer_clk_src",
816 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
817 .num_parents = 5,
818 .ops = &clk_rcg2_ops,
819 },
820};
821
822static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
823 F(133330000, P_GPLL0, 4.5, 0, 0),
824 F(266670000, P_MMPLL0, 3, 0, 0),
825 F(320000000, P_MMPLL0, 2.5, 0, 0),
826 F(372000000, P_MMPLL4, 2.5, 0, 0),
827 F(465000000, P_MMPLL4, 2, 0, 0),
828 F(600000000, P_GPLL0, 1, 0, 0),
829 { }
830};
831
832static struct clk_rcg2 cpp_clk_src = {
833 .cmd_rcgr = 0x3640,
834 .hid_width = 5,
835 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
836 .freq_tbl = ftbl_camss_vfe_cpp_clk,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "cpp_clk_src",
839 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
840 .num_parents = 5,
841 .ops = &clk_rcg2_ops,
842 },
843};
844
845static struct freq_tbl byte_freq_tbl[] = {
846 { .src = P_DSI0PLL_BYTE },
847 { }
848};
849
850static struct clk_rcg2 byte0_clk_src = {
851 .cmd_rcgr = 0x2120,
852 .hid_width = 5,
853 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
854 .freq_tbl = byte_freq_tbl,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "byte0_clk_src",
857 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
858 .num_parents = 6,
859 .ops = &clk_byte_ops,
860 .flags = CLK_SET_RATE_PARENT,
861 },
862};
863
864static struct clk_rcg2 byte1_clk_src = {
865 .cmd_rcgr = 0x2140,
866 .hid_width = 5,
867 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
868 .freq_tbl = byte_freq_tbl,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "byte1_clk_src",
871 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
872 .num_parents = 6,
873 .ops = &clk_byte_ops,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876};
877
878static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
879 F(19200000, P_XO, 1, 0, 0),
880 { }
881};
882
883static struct clk_rcg2 edpaux_clk_src = {
884 .cmd_rcgr = 0x20e0,
885 .hid_width = 5,
886 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
887 .freq_tbl = ftbl_mdss_edpaux_clk,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "edpaux_clk_src",
890 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
891 .num_parents = 4,
892 .ops = &clk_rcg2_ops,
893 },
894};
895
896static struct freq_tbl ftbl_mdss_edplink_clk[] = {
897 F(135000000, P_EDPLINK, 2, 0, 0),
898 F(270000000, P_EDPLINK, 11, 0, 0),
899 { }
900};
901
902static struct clk_rcg2 edplink_clk_src = {
903 .cmd_rcgr = 0x20c0,
904 .hid_width = 5,
905 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
906 .freq_tbl = ftbl_mdss_edplink_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "edplink_clk_src",
909 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
910 .num_parents = 6,
911 .ops = &clk_rcg2_ops,
912 .flags = CLK_SET_RATE_PARENT,
913 },
914};
915
916static struct freq_tbl edp_pixel_freq_tbl[] = {
917 { .src = P_EDPVCO },
918 { }
919};
920
921static struct clk_rcg2 edppixel_clk_src = {
922 .cmd_rcgr = 0x20a0,
923 .mnd_width = 8,
924 .hid_width = 5,
925 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
926 .freq_tbl = edp_pixel_freq_tbl,
927 .clkr.hw.init = &(struct clk_init_data){
928 .name = "edppixel_clk_src",
929 .parent_names = mmcc_xo_dsi_hdmi_edp,
930 .num_parents = 6,
931 .ops = &clk_edp_pixel_ops,
932 },
933};
934
935static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
936 F(19200000, P_XO, 1, 0, 0),
937 { }
938};
939
940static struct clk_rcg2 esc0_clk_src = {
941 .cmd_rcgr = 0x2160,
942 .hid_width = 5,
943 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
944 .freq_tbl = ftbl_mdss_esc0_1_clk,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "esc0_clk_src",
947 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
948 .num_parents = 6,
949 .ops = &clk_rcg2_ops,
950 },
951};
952
953static struct clk_rcg2 esc1_clk_src = {
954 .cmd_rcgr = 0x2180,
955 .hid_width = 5,
956 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
957 .freq_tbl = ftbl_mdss_esc0_1_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "esc1_clk_src",
960 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
961 .num_parents = 6,
962 .ops = &clk_rcg2_ops,
963 },
964};
965
966static struct freq_tbl extpclk_freq_tbl[] = {
967 { .src = P_HDMIPLL },
968 { }
969};
970
971static struct clk_rcg2 extpclk_clk_src = {
972 .cmd_rcgr = 0x2060,
973 .hid_width = 5,
974 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
975 .freq_tbl = extpclk_freq_tbl,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "extpclk_clk_src",
978 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
979 .num_parents = 6,
980 .ops = &clk_byte_ops,
981 .flags = CLK_SET_RATE_PARENT,
982 },
983};
984
985static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
986 F(19200000, P_XO, 1, 0, 0),
987 { }
988};
989
990static struct clk_rcg2 hdmi_clk_src = {
991 .cmd_rcgr = 0x2100,
992 .hid_width = 5,
993 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
994 .freq_tbl = ftbl_mdss_hdmi_clk,
995 .clkr.hw.init = &(struct clk_init_data){
996 .name = "hdmi_clk_src",
997 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
998 .num_parents = 4,
999 .ops = &clk_rcg2_ops,
1000 },
1001};
1002
1003static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1004 F(19200000, P_XO, 1, 0, 0),
1005 { }
1006};
1007
1008static struct clk_rcg2 vsync_clk_src = {
1009 .cmd_rcgr = 0x2080,
1010 .hid_width = 5,
1011 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1012 .freq_tbl = ftbl_mdss_vsync_clk,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "vsync_clk_src",
1015 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1016 .num_parents = 4,
1017 .ops = &clk_rcg2_ops,
1018 },
1019};
1020
1021static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1022 F(50000000, P_GPLL0, 12, 0, 0),
1023 { }
1024};
1025
1026static struct clk_rcg2 rbcpr_clk_src = {
1027 .cmd_rcgr = 0x4060,
1028 .hid_width = 5,
1029 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1030 .freq_tbl = ftbl_mmss_rbcpr_clk,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "rbcpr_clk_src",
1033 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1034 .num_parents = 4,
1035 .ops = &clk_rcg2_ops,
1036 },
1037};
1038
1039static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1040 F(19200000, P_XO, 1, 0, 0),
1041 { }
1042};
1043
1044static struct clk_rcg2 rbbmtimer_clk_src = {
1045 .cmd_rcgr = 0x4090,
1046 .hid_width = 5,
1047 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1048 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1049 .clkr.hw.init = &(struct clk_init_data){
1050 .name = "rbbmtimer_clk_src",
1051 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1052 .num_parents = 4,
1053 .ops = &clk_rcg2_ops,
1054 },
1055};
1056
1057static struct freq_tbl ftbl_vpu_maple_clk[] = {
1058 F(50000000, P_GPLL0, 12, 0, 0),
1059 F(100000000, P_GPLL0, 6, 0, 0),
1060 F(133330000, P_GPLL0, 4.5, 0, 0),
1061 F(200000000, P_MMPLL0, 4, 0, 0),
1062 F(266670000, P_MMPLL0, 3, 0, 0),
1063 F(465000000, P_MMPLL3, 2, 0, 0),
1064 { }
1065};
1066
1067static struct clk_rcg2 maple_clk_src = {
1068 .cmd_rcgr = 0x1320,
1069 .hid_width = 5,
1070 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1071 .freq_tbl = ftbl_vpu_maple_clk,
1072 .clkr.hw.init = &(struct clk_init_data){
1073 .name = "maple_clk_src",
1074 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1075 .num_parents = 4,
1076 .ops = &clk_rcg2_ops,
1077 },
1078};
1079
1080static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1081 F(50000000, P_GPLL0, 12, 0, 0),
1082 F(100000000, P_GPLL0, 6, 0, 0),
1083 F(200000000, P_MMPLL0, 4, 0, 0),
1084 F(320000000, P_MMPLL0, 2.5, 0, 0),
1085 F(400000000, P_MMPLL0, 2, 0, 0),
1086 { }
1087};
1088
1089static struct clk_rcg2 vdp_clk_src = {
1090 .cmd_rcgr = 0x1300,
1091 .hid_width = 5,
1092 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1093 .freq_tbl = ftbl_vpu_vdp_clk,
1094 .clkr.hw.init = &(struct clk_init_data){
1095 .name = "vdp_clk_src",
1096 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1097 .num_parents = 4,
1098 .ops = &clk_rcg2_ops,
1099 },
1100};
1101
1102static struct freq_tbl ftbl_vpu_bus_clk[] = {
1103 F(40000000, P_GPLL0, 15, 0, 0),
1104 F(80000000, P_MMPLL0, 10, 0, 0),
1105 { }
1106};
1107
1108static struct clk_rcg2 vpu_bus_clk_src = {
1109 .cmd_rcgr = 0x1340,
1110 .hid_width = 5,
1111 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1112 .freq_tbl = ftbl_vpu_bus_clk,
1113 .clkr.hw.init = &(struct clk_init_data){
1114 .name = "vpu_bus_clk_src",
1115 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1116 .num_parents = 4,
1117 .ops = &clk_rcg2_ops,
1118 },
1119};
1120
1121static struct clk_branch mmss_cxo_clk = {
1122 .halt_reg = 0x5104,
1123 .clkr = {
1124 .enable_reg = 0x5104,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "mmss_cxo_clk",
1128 .parent_names = (const char *[]){ "xo" },
1129 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_ops,
1132 },
1133 },
1134};
1135
1136static struct clk_branch mmss_sleepclk_clk = {
1137 .halt_reg = 0x5100,
1138 .clkr = {
1139 .enable_reg = 0x5100,
1140 .enable_mask = BIT(0),
1141 .hw.init = &(struct clk_init_data){
1142 .name = "mmss_sleepclk_clk",
1143 .parent_names = (const char *[]){
1144 "sleep_clk_src",
1145 },
1146 .num_parents = 1,
1147 .flags = CLK_SET_RATE_PARENT,
1148 .ops = &clk_branch2_ops,
1149 },
1150 },
1151};
1152
1153static struct clk_branch avsync_ahb_clk = {
1154 .halt_reg = 0x2414,
1155 .clkr = {
1156 .enable_reg = 0x2414,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "avsync_ahb_clk",
1160 .parent_names = (const char *[]){
1161 "mmss_ahb_clk_src",
1162 },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch avsync_edppixel_clk = {
1171 .halt_reg = 0x2418,
1172 .clkr = {
1173 .enable_reg = 0x2418,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "avsync_edppixel_clk",
1177 .parent_names = (const char *[]){
1178 "edppixel_clk_src",
1179 },
1180 .num_parents = 1,
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1183 },
1184 },
1185};
1186
1187static struct clk_branch avsync_extpclk_clk = {
1188 .halt_reg = 0x2410,
1189 .clkr = {
1190 .enable_reg = 0x2410,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "avsync_extpclk_clk",
1194 .parent_names = (const char *[]){
1195 "extpclk_clk_src",
1196 },
1197 .num_parents = 1,
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1200 },
1201 },
1202};
1203
1204static struct clk_branch avsync_pclk0_clk = {
1205 .halt_reg = 0x241c,
1206 .clkr = {
1207 .enable_reg = 0x241c,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "avsync_pclk0_clk",
1211 .parent_names = (const char *[]){
1212 "pclk0_clk_src",
1213 },
1214 .num_parents = 1,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219};
1220
1221static struct clk_branch avsync_pclk1_clk = {
1222 .halt_reg = 0x2420,
1223 .clkr = {
1224 .enable_reg = 0x2420,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "avsync_pclk1_clk",
1228 .parent_names = (const char *[]){
1229 "pclk1_clk_src",
1230 },
1231 .num_parents = 1,
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1234 },
1235 },
1236};
1237
1238static struct clk_branch avsync_vp_clk = {
1239 .halt_reg = 0x2404,
1240 .clkr = {
1241 .enable_reg = 0x2404,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "avsync_vp_clk",
1245 .parent_names = (const char *[]){
1246 "vp_clk_src",
1247 },
1248 .num_parents = 1,
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1251 },
1252 },
1253};
1254
1255static struct clk_branch camss_ahb_clk = {
1256 .halt_reg = 0x348c,
1257 .clkr = {
1258 .enable_reg = 0x348c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "camss_ahb_clk",
1262 .parent_names = (const char *[]){
1263 "mmss_ahb_clk_src",
1264 },
1265 .num_parents = 1,
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1268 },
1269 },
1270};
1271
1272static struct clk_branch camss_cci_cci_ahb_clk = {
1273 .halt_reg = 0x3348,
1274 .clkr = {
1275 .enable_reg = 0x3348,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "camss_cci_cci_ahb_clk",
1279 .parent_names = (const char *[]){
1280 "mmss_ahb_clk_src",
1281 },
1282 .num_parents = 1,
1283 .ops = &clk_branch2_ops,
1284 },
1285 },
1286};
1287
1288static struct clk_branch camss_cci_cci_clk = {
1289 .halt_reg = 0x3344,
1290 .clkr = {
1291 .enable_reg = 0x3344,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "camss_cci_cci_clk",
1295 .parent_names = (const char *[]){
1296 "cci_clk_src",
1297 },
1298 .num_parents = 1,
1299 .flags = CLK_SET_RATE_PARENT,
1300 .ops = &clk_branch2_ops,
1301 },
1302 },
1303};
1304
1305static struct clk_branch camss_csi0_ahb_clk = {
1306 .halt_reg = 0x30bc,
1307 .clkr = {
1308 .enable_reg = 0x30bc,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "camss_csi0_ahb_clk",
1312 .parent_names = (const char *[]){
1313 "mmss_ahb_clk_src",
1314 },
1315 .num_parents = 1,
1316 .ops = &clk_branch2_ops,
1317 },
1318 },
1319};
1320
1321static struct clk_branch camss_csi0_clk = {
1322 .halt_reg = 0x30b4,
1323 .clkr = {
1324 .enable_reg = 0x30b4,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "camss_csi0_clk",
1328 .parent_names = (const char *[]){
1329 "csi0_clk_src",
1330 },
1331 .num_parents = 1,
1332 .flags = CLK_SET_RATE_PARENT,
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336};
1337
1338static struct clk_branch camss_csi0phy_clk = {
1339 .halt_reg = 0x30c4,
1340 .clkr = {
1341 .enable_reg = 0x30c4,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "camss_csi0phy_clk",
1345 .parent_names = (const char *[]){
1346 "csi0_clk_src",
1347 },
1348 .num_parents = 1,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1351 },
1352 },
1353};
1354
1355static struct clk_branch camss_csi0pix_clk = {
1356 .halt_reg = 0x30e4,
1357 .clkr = {
1358 .enable_reg = 0x30e4,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "camss_csi0pix_clk",
1362 .parent_names = (const char *[]){
1363 "csi0_clk_src",
1364 },
1365 .num_parents = 1,
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1368 },
1369 },
1370};
1371
1372static struct clk_branch camss_csi0rdi_clk = {
1373 .halt_reg = 0x30d4,
1374 .clkr = {
1375 .enable_reg = 0x30d4,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "camss_csi0rdi_clk",
1379 .parent_names = (const char *[]){
1380 "csi0_clk_src",
1381 },
1382 .num_parents = 1,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch camss_csi1_ahb_clk = {
1390 .halt_reg = 0x3128,
1391 .clkr = {
1392 .enable_reg = 0x3128,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "camss_csi1_ahb_clk",
1396 .parent_names = (const char *[]){
1397 "mmss_ahb_clk_src",
1398 },
1399 .num_parents = 1,
1400 .flags = CLK_SET_RATE_PARENT,
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404};
1405
1406static struct clk_branch camss_csi1_clk = {
1407 .halt_reg = 0x3124,
1408 .clkr = {
1409 .enable_reg = 0x3124,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "camss_csi1_clk",
1413 .parent_names = (const char *[]){
1414 "csi1_clk_src",
1415 },
1416 .num_parents = 1,
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1419 },
1420 },
1421};
1422
1423static struct clk_branch camss_csi1phy_clk = {
1424 .halt_reg = 0x3134,
1425 .clkr = {
1426 .enable_reg = 0x3134,
1427 .enable_mask = BIT(0),
1428 .hw.init = &(struct clk_init_data){
1429 .name = "camss_csi1phy_clk",
1430 .parent_names = (const char *[]){
1431 "csi1_clk_src",
1432 },
1433 .num_parents = 1,
1434 .flags = CLK_SET_RATE_PARENT,
1435 .ops = &clk_branch2_ops,
1436 },
1437 },
1438};
1439
1440static struct clk_branch camss_csi1pix_clk = {
1441 .halt_reg = 0x3154,
1442 .clkr = {
1443 .enable_reg = 0x3154,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "camss_csi1pix_clk",
1447 .parent_names = (const char *[]){
1448 "csi1_clk_src",
1449 },
1450 .num_parents = 1,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455};
1456
1457static struct clk_branch camss_csi1rdi_clk = {
1458 .halt_reg = 0x3144,
1459 .clkr = {
1460 .enable_reg = 0x3144,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "camss_csi1rdi_clk",
1464 .parent_names = (const char *[]){
1465 "csi1_clk_src",
1466 },
1467 .num_parents = 1,
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474static struct clk_branch camss_csi2_ahb_clk = {
1475 .halt_reg = 0x3188,
1476 .clkr = {
1477 .enable_reg = 0x3188,
1478 .enable_mask = BIT(0),
1479 .hw.init = &(struct clk_init_data){
1480 .name = "camss_csi2_ahb_clk",
1481 .parent_names = (const char *[]){
1482 "mmss_ahb_clk_src",
1483 },
1484 .num_parents = 1,
1485 .ops = &clk_branch2_ops,
1486 },
1487 },
1488};
1489
1490static struct clk_branch camss_csi2_clk = {
1491 .halt_reg = 0x3184,
1492 .clkr = {
1493 .enable_reg = 0x3184,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "camss_csi2_clk",
1497 .parent_names = (const char *[]){
1498 "csi2_clk_src",
1499 },
1500 .num_parents = 1,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch camss_csi2phy_clk = {
1508 .halt_reg = 0x3194,
1509 .clkr = {
1510 .enable_reg = 0x3194,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "camss_csi2phy_clk",
1514 .parent_names = (const char *[]){
1515 "csi2_clk_src",
1516 },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522};
1523
1524static struct clk_branch camss_csi2pix_clk = {
1525 .halt_reg = 0x31b4,
1526 .clkr = {
1527 .enable_reg = 0x31b4,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "camss_csi2pix_clk",
1531 .parent_names = (const char *[]){
1532 "csi2_clk_src",
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539};
1540
1541static struct clk_branch camss_csi2rdi_clk = {
1542 .halt_reg = 0x31a4,
1543 .clkr = {
1544 .enable_reg = 0x31a4,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "camss_csi2rdi_clk",
1548 .parent_names = (const char *[]){
1549 "csi2_clk_src",
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556};
1557
1558static struct clk_branch camss_csi3_ahb_clk = {
1559 .halt_reg = 0x31e8,
1560 .clkr = {
1561 .enable_reg = 0x31e8,
1562 .enable_mask = BIT(0),
1563 .hw.init = &(struct clk_init_data){
1564 .name = "camss_csi3_ahb_clk",
1565 .parent_names = (const char *[]){
1566 "mmss_ahb_clk_src",
1567 },
1568 .num_parents = 1,
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572};
1573
1574static struct clk_branch camss_csi3_clk = {
1575 .halt_reg = 0x31e4,
1576 .clkr = {
1577 .enable_reg = 0x31e4,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "camss_csi3_clk",
1581 .parent_names = (const char *[]){
1582 "csi3_clk_src",
1583 },
1584 .num_parents = 1,
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1587 },
1588 },
1589};
1590
1591static struct clk_branch camss_csi3phy_clk = {
1592 .halt_reg = 0x31f4,
1593 .clkr = {
1594 .enable_reg = 0x31f4,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "camss_csi3phy_clk",
1598 .parent_names = (const char *[]){
1599 "csi3_clk_src",
1600 },
1601 .num_parents = 1,
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1604 },
1605 },
1606};
1607
1608static struct clk_branch camss_csi3pix_clk = {
1609 .halt_reg = 0x3214,
1610 .clkr = {
1611 .enable_reg = 0x3214,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "camss_csi3pix_clk",
1615 .parent_names = (const char *[]){
1616 "csi3_clk_src",
1617 },
1618 .num_parents = 1,
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1621 },
1622 },
1623};
1624
1625static struct clk_branch camss_csi3rdi_clk = {
1626 .halt_reg = 0x3204,
1627 .clkr = {
1628 .enable_reg = 0x3204,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "camss_csi3rdi_clk",
1632 .parent_names = (const char *[]){
1633 "csi3_clk_src",
1634 },
1635 .num_parents = 1,
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1638 },
1639 },
1640};
1641
1642static struct clk_branch camss_csi_vfe0_clk = {
1643 .halt_reg = 0x3704,
1644 .clkr = {
1645 .enable_reg = 0x3704,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "camss_csi_vfe0_clk",
1649 .parent_names = (const char *[]){
1650 "vfe0_clk_src",
1651 },
1652 .num_parents = 1,
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1655 },
1656 },
1657};
1658
1659static struct clk_branch camss_csi_vfe1_clk = {
1660 .halt_reg = 0x3714,
1661 .clkr = {
1662 .enable_reg = 0x3714,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "camss_csi_vfe1_clk",
1666 .parent_names = (const char *[]){
1667 "vfe1_clk_src",
1668 },
1669 .num_parents = 1,
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1672 },
1673 },
1674};
1675
1676static struct clk_branch camss_gp0_clk = {
1677 .halt_reg = 0x3444,
1678 .clkr = {
1679 .enable_reg = 0x3444,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "camss_gp0_clk",
1683 .parent_names = (const char *[]){
1684 "camss_gp0_clk_src",
1685 },
1686 .num_parents = 1,
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691};
1692
1693static struct clk_branch camss_gp1_clk = {
1694 .halt_reg = 0x3474,
1695 .clkr = {
1696 .enable_reg = 0x3474,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "camss_gp1_clk",
1700 .parent_names = (const char *[]){
1701 "camss_gp1_clk_src",
1702 },
1703 .num_parents = 1,
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1706 },
1707 },
1708};
1709
1710static struct clk_branch camss_ispif_ahb_clk = {
1711 .halt_reg = 0x3224,
1712 .clkr = {
1713 .enable_reg = 0x3224,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "camss_ispif_ahb_clk",
1717 .parent_names = (const char *[]){
1718 "mmss_ahb_clk_src",
1719 },
1720 .num_parents = 1,
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1723 },
1724 },
1725};
1726
1727static struct clk_branch camss_jpeg_jpeg0_clk = {
1728 .halt_reg = 0x35a8,
1729 .clkr = {
1730 .enable_reg = 0x35a8,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "camss_jpeg_jpeg0_clk",
1734 .parent_names = (const char *[]){
1735 "jpeg0_clk_src",
1736 },
1737 .num_parents = 1,
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1740 },
1741 },
1742};
1743
1744static struct clk_branch camss_jpeg_jpeg1_clk = {
1745 .halt_reg = 0x35ac,
1746 .clkr = {
1747 .enable_reg = 0x35ac,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_jpeg_jpeg1_clk",
1751 .parent_names = (const char *[]){
1752 "jpeg1_clk_src",
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch camss_jpeg_jpeg2_clk = {
1762 .halt_reg = 0x35b0,
1763 .clkr = {
1764 .enable_reg = 0x35b0,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "camss_jpeg_jpeg2_clk",
1768 .parent_names = (const char *[]){
1769 "jpeg2_clk_src",
1770 },
1771 .num_parents = 1,
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776};
1777
1778static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1779 .halt_reg = 0x35b4,
1780 .clkr = {
1781 .enable_reg = 0x35b4,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "camss_jpeg_jpeg_ahb_clk",
1785 .parent_names = (const char *[]){
1786 "mmss_ahb_clk_src",
1787 },
1788 .num_parents = 1,
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1795 .halt_reg = 0x35b8,
1796 .clkr = {
1797 .enable_reg = 0x35b8,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "camss_jpeg_jpeg_axi_clk",
1801 .parent_names = (const char *[]){
1802 "mmss_axi_clk_src",
1803 },
1804 .num_parents = 1,
1805 .ops = &clk_branch2_ops,
1806 },
1807 },
1808};
1809
1810static struct clk_branch camss_mclk0_clk = {
1811 .halt_reg = 0x3384,
1812 .clkr = {
1813 .enable_reg = 0x3384,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "camss_mclk0_clk",
1817 .parent_names = (const char *[]){
1818 "mclk0_clk_src",
1819 },
1820 .num_parents = 1,
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1823 },
1824 },
1825};
1826
1827static struct clk_branch camss_mclk1_clk = {
1828 .halt_reg = 0x33b4,
1829 .clkr = {
1830 .enable_reg = 0x33b4,
1831 .enable_mask = BIT(0),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "camss_mclk1_clk",
1834 .parent_names = (const char *[]){
1835 "mclk1_clk_src",
1836 },
1837 .num_parents = 1,
1838 .flags = CLK_SET_RATE_PARENT,
1839 .ops = &clk_branch2_ops,
1840 },
1841 },
1842};
1843
1844static struct clk_branch camss_mclk2_clk = {
1845 .halt_reg = 0x33e4,
1846 .clkr = {
1847 .enable_reg = 0x33e4,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "camss_mclk2_clk",
1851 .parent_names = (const char *[]){
1852 "mclk2_clk_src",
1853 },
1854 .num_parents = 1,
1855 .flags = CLK_SET_RATE_PARENT,
1856 .ops = &clk_branch2_ops,
1857 },
1858 },
1859};
1860
1861static struct clk_branch camss_mclk3_clk = {
1862 .halt_reg = 0x3414,
1863 .clkr = {
1864 .enable_reg = 0x3414,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "camss_mclk3_clk",
1868 .parent_names = (const char *[]){
1869 "mclk3_clk_src",
1870 },
1871 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT,
1873 .ops = &clk_branch2_ops,
1874 },
1875 },
1876};
1877
1878static struct clk_branch camss_micro_ahb_clk = {
1879 .halt_reg = 0x3494,
1880 .clkr = {
1881 .enable_reg = 0x3494,
1882 .enable_mask = BIT(0),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "camss_micro_ahb_clk",
1885 .parent_names = (const char *[]){
1886 "mmss_ahb_clk_src",
1887 },
1888 .num_parents = 1,
1889 .ops = &clk_branch2_ops,
1890 },
1891 },
1892};
1893
1894static struct clk_branch camss_phy0_csi0phytimer_clk = {
1895 .halt_reg = 0x3024,
1896 .clkr = {
1897 .enable_reg = 0x3024,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "camss_phy0_csi0phytimer_clk",
1901 .parent_names = (const char *[]){
1902 "csi0phytimer_clk_src",
1903 },
1904 .num_parents = 1,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909};
1910
1911static struct clk_branch camss_phy1_csi1phytimer_clk = {
1912 .halt_reg = 0x3054,
1913 .clkr = {
1914 .enable_reg = 0x3054,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "camss_phy1_csi1phytimer_clk",
1918 .parent_names = (const char *[]){
1919 "csi1phytimer_clk_src",
1920 },
1921 .num_parents = 1,
1922 .flags = CLK_SET_RATE_PARENT,
1923 .ops = &clk_branch2_ops,
1924 },
1925 },
1926};
1927
1928static struct clk_branch camss_phy2_csi2phytimer_clk = {
1929 .halt_reg = 0x3084,
1930 .clkr = {
1931 .enable_reg = 0x3084,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "camss_phy2_csi2phytimer_clk",
1935 .parent_names = (const char *[]){
1936 "csi2phytimer_clk_src",
1937 },
1938 .num_parents = 1,
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1941 },
1942 },
1943};
1944
1945static struct clk_branch camss_top_ahb_clk = {
1946 .halt_reg = 0x3484,
1947 .clkr = {
1948 .enable_reg = 0x3484,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "camss_top_ahb_clk",
1952 .parent_names = (const char *[]){
1953 "mmss_ahb_clk_src",
1954 },
1955 .num_parents = 1,
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1958 },
1959 },
1960};
1961
1962static struct clk_branch camss_vfe_cpp_ahb_clk = {
1963 .halt_reg = 0x36b4,
1964 .clkr = {
1965 .enable_reg = 0x36b4,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "camss_vfe_cpp_ahb_clk",
1969 .parent_names = (const char *[]){
1970 "mmss_ahb_clk_src",
1971 },
1972 .num_parents = 1,
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_branch2_ops,
1975 },
1976 },
1977};
1978
1979static struct clk_branch camss_vfe_cpp_clk = {
1980 .halt_reg = 0x36b0,
1981 .clkr = {
1982 .enable_reg = 0x36b0,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "camss_vfe_cpp_clk",
1986 .parent_names = (const char *[]){
1987 "cpp_clk_src",
1988 },
1989 .num_parents = 1,
1990 .flags = CLK_SET_RATE_PARENT,
1991 .ops = &clk_branch2_ops,
1992 },
1993 },
1994};
1995
1996static struct clk_branch camss_vfe_vfe0_clk = {
1997 .halt_reg = 0x36a8,
1998 .clkr = {
1999 .enable_reg = 0x36a8,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "camss_vfe_vfe0_clk",
2003 .parent_names = (const char *[]){
2004 "vfe0_clk_src",
2005 },
2006 .num_parents = 1,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011};
2012
2013static struct clk_branch camss_vfe_vfe1_clk = {
2014 .halt_reg = 0x36ac,
2015 .clkr = {
2016 .enable_reg = 0x36ac,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "camss_vfe_vfe1_clk",
2020 .parent_names = (const char *[]){
2021 "vfe1_clk_src",
2022 },
2023 .num_parents = 1,
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2026 },
2027 },
2028};
2029
2030static struct clk_branch camss_vfe_vfe_ahb_clk = {
2031 .halt_reg = 0x36b8,
2032 .clkr = {
2033 .enable_reg = 0x36b8,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "camss_vfe_vfe_ahb_clk",
2037 .parent_names = (const char *[]){
2038 "mmss_ahb_clk_src",
2039 },
2040 .num_parents = 1,
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2043 },
2044 },
2045};
2046
2047static struct clk_branch camss_vfe_vfe_axi_clk = {
2048 .halt_reg = 0x36bc,
2049 .clkr = {
2050 .enable_reg = 0x36bc,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "camss_vfe_vfe_axi_clk",
2054 .parent_names = (const char *[]){
2055 "mmss_axi_clk_src",
2056 },
2057 .num_parents = 1,
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch mdss_ahb_clk = {
2065 .halt_reg = 0x2308,
2066 .clkr = {
2067 .enable_reg = 0x2308,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mdss_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "mmss_ahb_clk_src",
2073 },
2074 .num_parents = 1,
2075 .flags = CLK_SET_RATE_PARENT,
2076 .ops = &clk_branch2_ops,
2077 },
2078 },
2079};
2080
2081static struct clk_branch mdss_axi_clk = {
2082 .halt_reg = 0x2310,
2083 .clkr = {
2084 .enable_reg = 0x2310,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mdss_axi_clk",
2088 .parent_names = (const char *[]){
2089 "mmss_axi_clk_src",
2090 },
2091 .num_parents = 1,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch mdss_byte0_clk = {
2099 .halt_reg = 0x233c,
2100 .clkr = {
2101 .enable_reg = 0x233c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mdss_byte0_clk",
2105 .parent_names = (const char *[]){
2106 "byte0_clk_src",
2107 },
2108 .num_parents = 1,
2109 .flags = CLK_SET_RATE_PARENT,
2110 .ops = &clk_branch2_ops,
2111 },
2112 },
2113};
2114
2115static struct clk_branch mdss_byte1_clk = {
2116 .halt_reg = 0x2340,
2117 .clkr = {
2118 .enable_reg = 0x2340,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mdss_byte1_clk",
2122 .parent_names = (const char *[]){
2123 "byte1_clk_src",
2124 },
2125 .num_parents = 1,
2126 .flags = CLK_SET_RATE_PARENT,
2127 .ops = &clk_branch2_ops,
2128 },
2129 },
2130};
2131
2132static struct clk_branch mdss_edpaux_clk = {
2133 .halt_reg = 0x2334,
2134 .clkr = {
2135 .enable_reg = 0x2334,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "mdss_edpaux_clk",
2139 .parent_names = (const char *[]){
2140 "edpaux_clk_src",
2141 },
2142 .num_parents = 1,
2143 .flags = CLK_SET_RATE_PARENT,
2144 .ops = &clk_branch2_ops,
2145 },
2146 },
2147};
2148
2149static struct clk_branch mdss_edplink_clk = {
2150 .halt_reg = 0x2330,
2151 .clkr = {
2152 .enable_reg = 0x2330,
2153 .enable_mask = BIT(0),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "mdss_edplink_clk",
2156 .parent_names = (const char *[]){
2157 "edplink_clk_src",
2158 },
2159 .num_parents = 1,
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2162 },
2163 },
2164};
2165
2166static struct clk_branch mdss_edppixel_clk = {
2167 .halt_reg = 0x232c,
2168 .clkr = {
2169 .enable_reg = 0x232c,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "mdss_edppixel_clk",
2173 .parent_names = (const char *[]){
2174 "edppixel_clk_src",
2175 },
2176 .num_parents = 1,
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2179 },
2180 },
2181};
2182
2183static struct clk_branch mdss_esc0_clk = {
2184 .halt_reg = 0x2344,
2185 .clkr = {
2186 .enable_reg = 0x2344,
2187 .enable_mask = BIT(0),
2188 .hw.init = &(struct clk_init_data){
2189 .name = "mdss_esc0_clk",
2190 .parent_names = (const char *[]){
2191 "esc0_clk_src",
2192 },
2193 .num_parents = 1,
2194 .flags = CLK_SET_RATE_PARENT,
2195 .ops = &clk_branch2_ops,
2196 },
2197 },
2198};
2199
2200static struct clk_branch mdss_esc1_clk = {
2201 .halt_reg = 0x2348,
2202 .clkr = {
2203 .enable_reg = 0x2348,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(struct clk_init_data){
2206 .name = "mdss_esc1_clk",
2207 .parent_names = (const char *[]){
2208 "esc1_clk_src",
2209 },
2210 .num_parents = 1,
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2213 },
2214 },
2215};
2216
2217static struct clk_branch mdss_extpclk_clk = {
2218 .halt_reg = 0x2324,
2219 .clkr = {
2220 .enable_reg = 0x2324,
2221 .enable_mask = BIT(0),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "mdss_extpclk_clk",
2224 .parent_names = (const char *[]){
2225 "extpclk_clk_src",
2226 },
2227 .num_parents = 1,
2228 .flags = CLK_SET_RATE_PARENT,
2229 .ops = &clk_branch2_ops,
2230 },
2231 },
2232};
2233
2234static struct clk_branch mdss_hdmi_ahb_clk = {
2235 .halt_reg = 0x230c,
2236 .clkr = {
2237 .enable_reg = 0x230c,
2238 .enable_mask = BIT(0),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "mdss_hdmi_ahb_clk",
2241 .parent_names = (const char *[]){
2242 "mmss_ahb_clk_src",
2243 },
2244 .num_parents = 1,
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2247 },
2248 },
2249};
2250
2251static struct clk_branch mdss_hdmi_clk = {
2252 .halt_reg = 0x2338,
2253 .clkr = {
2254 .enable_reg = 0x2338,
2255 .enable_mask = BIT(0),
2256 .hw.init = &(struct clk_init_data){
2257 .name = "mdss_hdmi_clk",
2258 .parent_names = (const char *[]){
2259 "hdmi_clk_src",
2260 },
2261 .num_parents = 1,
2262 .flags = CLK_SET_RATE_PARENT,
2263 .ops = &clk_branch2_ops,
2264 },
2265 },
2266};
2267
2268static struct clk_branch mdss_mdp_clk = {
2269 .halt_reg = 0x231c,
2270 .clkr = {
2271 .enable_reg = 0x231c,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "mdss_mdp_clk",
2275 .parent_names = (const char *[]){
2276 "mdp_clk_src",
2277 },
2278 .num_parents = 1,
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2281 },
2282 },
2283};
2284
2285static struct clk_branch mdss_mdp_lut_clk = {
2286 .halt_reg = 0x2320,
2287 .clkr = {
2288 .enable_reg = 0x2320,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "mdss_mdp_lut_clk",
2292 .parent_names = (const char *[]){
2293 "mdp_clk_src",
2294 },
2295 .num_parents = 1,
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2298 },
2299 },
2300};
2301
2302static struct clk_branch mdss_pclk0_clk = {
2303 .halt_reg = 0x2314,
2304 .clkr = {
2305 .enable_reg = 0x2314,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "mdss_pclk0_clk",
2309 .parent_names = (const char *[]){
2310 "pclk0_clk_src",
2311 },
2312 .num_parents = 1,
2313 .flags = CLK_SET_RATE_PARENT,
2314 .ops = &clk_branch2_ops,
2315 },
2316 },
2317};
2318
2319static struct clk_branch mdss_pclk1_clk = {
2320 .halt_reg = 0x2318,
2321 .clkr = {
2322 .enable_reg = 0x2318,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "mdss_pclk1_clk",
2326 .parent_names = (const char *[]){
2327 "pclk1_clk_src",
2328 },
2329 .num_parents = 1,
2330 .flags = CLK_SET_RATE_PARENT,
2331 .ops = &clk_branch2_ops,
2332 },
2333 },
2334};
2335
2336static struct clk_branch mdss_vsync_clk = {
2337 .halt_reg = 0x2328,
2338 .clkr = {
2339 .enable_reg = 0x2328,
2340 .enable_mask = BIT(0),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "mdss_vsync_clk",
2343 .parent_names = (const char *[]){
2344 "vsync_clk_src",
2345 },
2346 .num_parents = 1,
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2349 },
2350 },
2351};
2352
2353static struct clk_branch mmss_rbcpr_ahb_clk = {
2354 .halt_reg = 0x4088,
2355 .clkr = {
2356 .enable_reg = 0x4088,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "mmss_rbcpr_ahb_clk",
2360 .parent_names = (const char *[]){
2361 "mmss_ahb_clk_src",
2362 },
2363 .num_parents = 1,
2364 .flags = CLK_SET_RATE_PARENT,
2365 .ops = &clk_branch2_ops,
2366 },
2367 },
2368};
2369
2370static struct clk_branch mmss_rbcpr_clk = {
2371 .halt_reg = 0x4084,
2372 .clkr = {
2373 .enable_reg = 0x4084,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "mmss_rbcpr_clk",
2377 .parent_names = (const char *[]){
2378 "rbcpr_clk_src",
2379 },
2380 .num_parents = 1,
2381 .flags = CLK_SET_RATE_PARENT,
2382 .ops = &clk_branch2_ops,
2383 },
2384 },
2385};
2386
2387static struct clk_branch mmss_spdm_ahb_clk = {
2388 .halt_reg = 0x0230,
2389 .clkr = {
2390 .enable_reg = 0x0230,
2391 .enable_mask = BIT(0),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "mmss_spdm_ahb_clk",
2394 .parent_names = (const char *[]){
2395 "mmss_spdm_ahb_div_clk",
2396 },
2397 .num_parents = 1,
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_branch2_ops,
2400 },
2401 },
2402};
2403
2404static struct clk_branch mmss_spdm_axi_clk = {
2405 .halt_reg = 0x0210,
2406 .clkr = {
2407 .enable_reg = 0x0210,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "mmss_spdm_axi_clk",
2411 .parent_names = (const char *[]){
2412 "mmss_spdm_axi_div_clk",
2413 },
2414 .num_parents = 1,
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2417 },
2418 },
2419};
2420
2421static struct clk_branch mmss_spdm_csi0_clk = {
2422 .halt_reg = 0x023c,
2423 .clkr = {
2424 .enable_reg = 0x023c,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "mmss_spdm_csi0_clk",
2428 .parent_names = (const char *[]){
2429 "mmss_spdm_csi0_div_clk",
2430 },
2431 .num_parents = 1,
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2434 },
2435 },
2436};
2437
2438static struct clk_branch mmss_spdm_gfx3d_clk = {
2439 .halt_reg = 0x022c,
2440 .clkr = {
2441 .enable_reg = 0x022c,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "mmss_spdm_gfx3d_clk",
2445 .parent_names = (const char *[]){
2446 "mmss_spdm_gfx3d_div_clk",
2447 },
2448 .num_parents = 1,
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2451 },
2452 },
2453};
2454
2455static struct clk_branch mmss_spdm_jpeg0_clk = {
2456 .halt_reg = 0x0204,
2457 .clkr = {
2458 .enable_reg = 0x0204,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "mmss_spdm_jpeg0_clk",
2462 .parent_names = (const char *[]){
2463 "mmss_spdm_jpeg0_div_clk",
2464 },
2465 .num_parents = 1,
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2468 },
2469 },
2470};
2471
2472static struct clk_branch mmss_spdm_jpeg1_clk = {
2473 .halt_reg = 0x0208,
2474 .clkr = {
2475 .enable_reg = 0x0208,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "mmss_spdm_jpeg1_clk",
2479 .parent_names = (const char *[]){
2480 "mmss_spdm_jpeg1_div_clk",
2481 },
2482 .num_parents = 1,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2485 },
2486 },
2487};
2488
2489static struct clk_branch mmss_spdm_jpeg2_clk = {
2490 .halt_reg = 0x0224,
2491 .clkr = {
2492 .enable_reg = 0x0224,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mmss_spdm_jpeg2_clk",
2496 .parent_names = (const char *[]){
2497 "mmss_spdm_jpeg2_div_clk",
2498 },
2499 .num_parents = 1,
2500 .flags = CLK_SET_RATE_PARENT,
2501 .ops = &clk_branch2_ops,
2502 },
2503 },
2504};
2505
2506static struct clk_branch mmss_spdm_mdp_clk = {
2507 .halt_reg = 0x020c,
2508 .clkr = {
2509 .enable_reg = 0x020c,
2510 .enable_mask = BIT(0),
2511 .hw.init = &(struct clk_init_data){
2512 .name = "mmss_spdm_mdp_clk",
2513 .parent_names = (const char *[]){
2514 "mmss_spdm_mdp_div_clk",
2515 },
2516 .num_parents = 1,
2517 .flags = CLK_SET_RATE_PARENT,
2518 .ops = &clk_branch2_ops,
2519 },
2520 },
2521};
2522
2523static struct clk_branch mmss_spdm_pclk0_clk = {
2524 .halt_reg = 0x0234,
2525 .clkr = {
2526 .enable_reg = 0x0234,
2527 .enable_mask = BIT(0),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "mmss_spdm_pclk0_clk",
2530 .parent_names = (const char *[]){
2531 "mmss_spdm_pclk0_div_clk",
2532 },
2533 .num_parents = 1,
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2536 },
2537 },
2538};
2539
2540static struct clk_branch mmss_spdm_pclk1_clk = {
2541 .halt_reg = 0x0228,
2542 .clkr = {
2543 .enable_reg = 0x0228,
2544 .enable_mask = BIT(0),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "mmss_spdm_pclk1_clk",
2547 .parent_names = (const char *[]){
2548 "mmss_spdm_pclk1_div_clk",
2549 },
2550 .num_parents = 1,
2551 .flags = CLK_SET_RATE_PARENT,
2552 .ops = &clk_branch2_ops,
2553 },
2554 },
2555};
2556
2557static struct clk_branch mmss_spdm_vcodec0_clk = {
2558 .halt_reg = 0x0214,
2559 .clkr = {
2560 .enable_reg = 0x0214,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "mmss_spdm_vcodec0_clk",
2564 .parent_names = (const char *[]){
2565 "mmss_spdm_vcodec0_div_clk",
2566 },
2567 .num_parents = 1,
2568 .flags = CLK_SET_RATE_PARENT,
2569 .ops = &clk_branch2_ops,
2570 },
2571 },
2572};
2573
2574static struct clk_branch mmss_spdm_vfe0_clk = {
2575 .halt_reg = 0x0218,
2576 .clkr = {
2577 .enable_reg = 0x0218,
2578 .enable_mask = BIT(0),
2579 .hw.init = &(struct clk_init_data){
2580 .name = "mmss_spdm_vfe0_clk",
2581 .parent_names = (const char *[]){
2582 "mmss_spdm_vfe0_div_clk",
2583 },
2584 .num_parents = 1,
2585 .flags = CLK_SET_RATE_PARENT,
2586 .ops = &clk_branch2_ops,
2587 },
2588 },
2589};
2590
2591static struct clk_branch mmss_spdm_vfe1_clk = {
2592 .halt_reg = 0x021c,
2593 .clkr = {
2594 .enable_reg = 0x021c,
2595 .enable_mask = BIT(0),
2596 .hw.init = &(struct clk_init_data){
2597 .name = "mmss_spdm_vfe1_clk",
2598 .parent_names = (const char *[]){
2599 "mmss_spdm_vfe1_div_clk",
2600 },
2601 .num_parents = 1,
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2604 },
2605 },
2606};
2607
2608static struct clk_branch mmss_spdm_rm_axi_clk = {
2609 .halt_reg = 0x0304,
2610 .clkr = {
2611 .enable_reg = 0x0304,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "mmss_spdm_rm_axi_clk",
2615 .parent_names = (const char *[]){
2616 "mmss_axi_clk_src",
2617 },
2618 .num_parents = 1,
2619 .flags = CLK_SET_RATE_PARENT,
2620 .ops = &clk_branch2_ops,
2621 },
2622 },
2623};
2624
2625static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2626 .halt_reg = 0x0308,
2627 .clkr = {
2628 .enable_reg = 0x0308,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "mmss_spdm_rm_ocmemnoc_clk",
2632 .parent_names = (const char *[]){
2633 "ocmemnoc_clk_src",
2634 },
2635 .num_parents = 1,
2636 .flags = CLK_SET_RATE_PARENT,
2637 .ops = &clk_branch2_ops,
2638 },
2639 },
2640};
2641
2642
2643static struct clk_branch mmss_misc_ahb_clk = {
2644 .halt_reg = 0x502c,
2645 .clkr = {
2646 .enable_reg = 0x502c,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "mmss_misc_ahb_clk",
2650 .parent_names = (const char *[]){
2651 "mmss_ahb_clk_src",
2652 },
2653 .num_parents = 1,
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2656 },
2657 },
2658};
2659
2660static struct clk_branch mmss_mmssnoc_ahb_clk = {
2661 .halt_reg = 0x5024,
2662 .clkr = {
2663 .enable_reg = 0x5024,
2664 .enable_mask = BIT(0),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "mmss_mmssnoc_ahb_clk",
2667 .parent_names = (const char *[]){
2668 "mmss_ahb_clk_src",
2669 },
2670 .num_parents = 1,
2671 .ops = &clk_branch2_ops,
2672 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2673 },
2674 },
2675};
2676
2677static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2678 .halt_reg = 0x5028,
2679 .clkr = {
2680 .enable_reg = 0x5028,
2681 .enable_mask = BIT(0),
2682 .hw.init = &(struct clk_init_data){
2683 .name = "mmss_mmssnoc_bto_ahb_clk",
2684 .parent_names = (const char *[]){
2685 "mmss_ahb_clk_src",
2686 },
2687 .num_parents = 1,
2688 .ops = &clk_branch2_ops,
2689 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2690 },
2691 },
2692};
2693
2694static struct clk_branch mmss_mmssnoc_axi_clk = {
2695 .halt_reg = 0x506c,
2696 .clkr = {
2697 .enable_reg = 0x506c,
2698 .enable_mask = BIT(0),
2699 .hw.init = &(struct clk_init_data){
2700 .name = "mmss_mmssnoc_axi_clk",
2701 .parent_names = (const char *[]){
2702 "mmss_axi_clk_src",
2703 },
2704 .num_parents = 1,
2705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2706 .ops = &clk_branch2_ops,
2707 },
2708 },
2709};
2710
2711static struct clk_branch mmss_s0_axi_clk = {
2712 .halt_reg = 0x5064,
2713 .clkr = {
2714 .enable_reg = 0x5064,
2715 .enable_mask = BIT(0),
2716 .hw.init = &(struct clk_init_data){
2717 .name = "mmss_s0_axi_clk",
2718 .parent_names = (const char *[]){
2719 "mmss_axi_clk_src",
2720 },
2721 .num_parents = 1,
2722 .ops = &clk_branch2_ops,
2723 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2724 },
2725 },
2726};
2727
2728static struct clk_branch ocmemcx_ahb_clk = {
2729 .halt_reg = 0x405c,
2730 .clkr = {
2731 .enable_reg = 0x405c,
2732 .enable_mask = BIT(0),
2733 .hw.init = &(struct clk_init_data){
2734 .name = "ocmemcx_ahb_clk",
2735 .parent_names = (const char *[]){
2736 "mmss_ahb_clk_src",
2737 },
2738 .num_parents = 1,
2739 .flags = CLK_SET_RATE_PARENT,
2740 .ops = &clk_branch2_ops,
2741 },
2742 },
2743};
2744
2745static struct clk_branch ocmemcx_ocmemnoc_clk = {
2746 .halt_reg = 0x4058,
2747 .clkr = {
2748 .enable_reg = 0x4058,
2749 .enable_mask = BIT(0),
2750 .hw.init = &(struct clk_init_data){
2751 .name = "ocmemcx_ocmemnoc_clk",
2752 .parent_names = (const char *[]){
2753 "ocmemnoc_clk_src",
2754 },
2755 .num_parents = 1,
2756 .flags = CLK_SET_RATE_PARENT,
2757 .ops = &clk_branch2_ops,
2758 },
2759 },
2760};
2761
2762static struct clk_branch oxili_ocmemgx_clk = {
2763 .halt_reg = 0x402c,
2764 .clkr = {
2765 .enable_reg = 0x402c,
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data){
2768 .name = "oxili_ocmemgx_clk",
2769 .parent_names = (const char *[]){
2770 "gfx3d_clk_src",
2771 },
2772 .num_parents = 1,
2773 .flags = CLK_SET_RATE_PARENT,
2774 .ops = &clk_branch2_ops,
2775 },
2776 },
2777};
2778
2779static struct clk_branch oxili_gfx3d_clk = {
2780 .halt_reg = 0x4028,
2781 .clkr = {
2782 .enable_reg = 0x4028,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "oxili_gfx3d_clk",
2786 .parent_names = (const char *[]){
2787 "gfx3d_clk_src",
2788 },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch oxili_rbbmtimer_clk = {
2797 .halt_reg = 0x40b0,
2798 .clkr = {
2799 .enable_reg = 0x40b0,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "oxili_rbbmtimer_clk",
2803 .parent_names = (const char *[]){
2804 "rbbmtimer_clk_src",
2805 },
2806 .num_parents = 1,
2807 .flags = CLK_SET_RATE_PARENT,
2808 .ops = &clk_branch2_ops,
2809 },
2810 },
2811};
2812
2813static struct clk_branch oxilicx_ahb_clk = {
2814 .halt_reg = 0x403c,
2815 .clkr = {
2816 .enable_reg = 0x403c,
2817 .enable_mask = BIT(0),
2818 .hw.init = &(struct clk_init_data){
2819 .name = "oxilicx_ahb_clk",
2820 .parent_names = (const char *[]){
2821 "mmss_ahb_clk_src",
2822 },
2823 .num_parents = 1,
2824 .flags = CLK_SET_RATE_PARENT,
2825 .ops = &clk_branch2_ops,
2826 },
2827 },
2828};
2829
2830static struct clk_branch venus0_ahb_clk = {
2831 .halt_reg = 0x1030,
2832 .clkr = {
2833 .enable_reg = 0x1030,
2834 .enable_mask = BIT(0),
2835 .hw.init = &(struct clk_init_data){
2836 .name = "venus0_ahb_clk",
2837 .parent_names = (const char *[]){
2838 "mmss_ahb_clk_src",
2839 },
2840 .num_parents = 1,
2841 .flags = CLK_SET_RATE_PARENT,
2842 .ops = &clk_branch2_ops,
2843 },
2844 },
2845};
2846
2847static struct clk_branch venus0_axi_clk = {
2848 .halt_reg = 0x1034,
2849 .clkr = {
2850 .enable_reg = 0x1034,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "venus0_axi_clk",
2854 .parent_names = (const char *[]){
2855 "mmss_axi_clk_src",
2856 },
2857 .num_parents = 1,
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2860 },
2861 },
2862};
2863
2864static struct clk_branch venus0_core0_vcodec_clk = {
2865 .halt_reg = 0x1048,
2866 .clkr = {
2867 .enable_reg = 0x1048,
2868 .enable_mask = BIT(0),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "venus0_core0_vcodec_clk",
2871 .parent_names = (const char *[]){
2872 "vcodec0_clk_src",
2873 },
2874 .num_parents = 1,
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2877 },
2878 },
2879};
2880
2881static struct clk_branch venus0_core1_vcodec_clk = {
2882 .halt_reg = 0x104c,
2883 .clkr = {
2884 .enable_reg = 0x104c,
2885 .enable_mask = BIT(0),
2886 .hw.init = &(struct clk_init_data){
2887 .name = "venus0_core1_vcodec_clk",
2888 .parent_names = (const char *[]){
2889 "vcodec0_clk_src",
2890 },
2891 .num_parents = 1,
2892 .flags = CLK_SET_RATE_PARENT,
2893 .ops = &clk_branch2_ops,
2894 },
2895 },
2896};
2897
2898static struct clk_branch venus0_ocmemnoc_clk = {
2899 .halt_reg = 0x1038,
2900 .clkr = {
2901 .enable_reg = 0x1038,
2902 .enable_mask = BIT(0),
2903 .hw.init = &(struct clk_init_data){
2904 .name = "venus0_ocmemnoc_clk",
2905 .parent_names = (const char *[]){
2906 "ocmemnoc_clk_src",
2907 },
2908 .num_parents = 1,
2909 .flags = CLK_SET_RATE_PARENT,
2910 .ops = &clk_branch2_ops,
2911 },
2912 },
2913};
2914
2915static struct clk_branch venus0_vcodec0_clk = {
2916 .halt_reg = 0x1028,
2917 .clkr = {
2918 .enable_reg = 0x1028,
2919 .enable_mask = BIT(0),
2920 .hw.init = &(struct clk_init_data){
2921 .name = "venus0_vcodec0_clk",
2922 .parent_names = (const char *[]){
2923 "vcodec0_clk_src",
2924 },
2925 .num_parents = 1,
2926 .flags = CLK_SET_RATE_PARENT,
2927 .ops = &clk_branch2_ops,
2928 },
2929 },
2930};
2931
2932static struct clk_branch vpu_ahb_clk = {
2933 .halt_reg = 0x1430,
2934 .clkr = {
2935 .enable_reg = 0x1430,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "vpu_ahb_clk",
2939 .parent_names = (const char *[]){
2940 "mmss_ahb_clk_src",
2941 },
2942 .num_parents = 1,
2943 .flags = CLK_SET_RATE_PARENT,
2944 .ops = &clk_branch2_ops,
2945 },
2946 },
2947};
2948
2949static struct clk_branch vpu_axi_clk = {
2950 .halt_reg = 0x143c,
2951 .clkr = {
2952 .enable_reg = 0x143c,
2953 .enable_mask = BIT(0),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "vpu_axi_clk",
2956 .parent_names = (const char *[]){
2957 "mmss_axi_clk_src",
2958 },
2959 .num_parents = 1,
2960 .flags = CLK_SET_RATE_PARENT,
2961 .ops = &clk_branch2_ops,
2962 },
2963 },
2964};
2965
2966static struct clk_branch vpu_bus_clk = {
2967 .halt_reg = 0x1440,
2968 .clkr = {
2969 .enable_reg = 0x1440,
2970 .enable_mask = BIT(0),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "vpu_bus_clk",
2973 .parent_names = (const char *[]){
2974 "vpu_bus_clk_src",
2975 },
2976 .num_parents = 1,
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2979 },
2980 },
2981};
2982
2983static struct clk_branch vpu_cxo_clk = {
2984 .halt_reg = 0x1434,
2985 .clkr = {
2986 .enable_reg = 0x1434,
2987 .enable_mask = BIT(0),
2988 .hw.init = &(struct clk_init_data){
2989 .name = "vpu_cxo_clk",
2990 .parent_names = (const char *[]){ "xo" },
2991 .num_parents = 1,
2992 .flags = CLK_SET_RATE_PARENT,
2993 .ops = &clk_branch2_ops,
2994 },
2995 },
2996};
2997
2998static struct clk_branch vpu_maple_clk = {
2999 .halt_reg = 0x142c,
3000 .clkr = {
3001 .enable_reg = 0x142c,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "vpu_maple_clk",
3005 .parent_names = (const char *[]){
3006 "maple_clk_src",
3007 },
3008 .num_parents = 1,
3009 .flags = CLK_SET_RATE_PARENT,
3010 .ops = &clk_branch2_ops,
3011 },
3012 },
3013};
3014
3015static struct clk_branch vpu_sleep_clk = {
3016 .halt_reg = 0x1438,
3017 .clkr = {
3018 .enable_reg = 0x1438,
3019 .enable_mask = BIT(0),
3020 .hw.init = &(struct clk_init_data){
3021 .name = "vpu_sleep_clk",
3022 .parent_names = (const char *[]){
3023 "sleep_clk_src",
3024 },
3025 .num_parents = 1,
3026 .flags = CLK_SET_RATE_PARENT,
3027 .ops = &clk_branch2_ops,
3028 },
3029 },
3030};
3031
3032static struct clk_branch vpu_vdp_clk = {
3033 .halt_reg = 0x1428,
3034 .clkr = {
3035 .enable_reg = 0x1428,
3036 .enable_mask = BIT(0),
3037 .hw.init = &(struct clk_init_data){
3038 .name = "vpu_vdp_clk",
3039 .parent_names = (const char *[]){
3040 "vdp_clk_src",
3041 },
3042 .num_parents = 1,
3043 .flags = CLK_SET_RATE_PARENT,
3044 .ops = &clk_branch2_ops,
3045 },
3046 },
3047};
3048
3049static const struct pll_config mmpll1_config = {
3050 .l = 60,
3051 .m = 25,
3052 .n = 32,
3053 .vco_val = 0x0,
3054 .vco_mask = 0x3 << 20,
3055 .pre_div_val = 0x0,
3056 .pre_div_mask = 0x7 << 12,
3057 .post_div_val = 0x0,
3058 .post_div_mask = 0x3 << 8,
3059 .mn_ena_mask = BIT(24),
3060 .main_output_mask = BIT(0),
3061};
3062
3063static const struct pll_config mmpll3_config = {
3064 .l = 48,
3065 .m = 7,
3066 .n = 16,
3067 .vco_val = 0x0,
3068 .vco_mask = 0x3 << 20,
3069 .pre_div_val = 0x0,
3070 .pre_div_mask = 0x7 << 12,
3071 .post_div_val = 0x0,
3072 .post_div_mask = 0x3 << 8,
3073 .mn_ena_mask = BIT(24),
3074 .main_output_mask = BIT(0),
3075 .aux_output_mask = BIT(1),
3076};
3077
3078static struct clk_regmap *mmcc_apq8084_clocks[] = {
3079 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3080 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3081 [MMPLL0] = &mmpll0.clkr,
3082 [MMPLL0_VOTE] = &mmpll0_vote,
3083 [MMPLL1] = &mmpll1.clkr,
3084 [MMPLL1_VOTE] = &mmpll1_vote,
3085 [MMPLL2] = &mmpll2.clkr,
3086 [MMPLL3] = &mmpll3.clkr,
3087 [MMPLL4] = &mmpll4.clkr,
3088 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3089 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3090 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3091 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3092 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3093 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3094 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3095 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3096 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3097 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3098 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3099 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3100 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3101 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3102 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3103 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3104 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3105 [VP_CLK_SRC] = &vp_clk_src.clkr,
3106 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3107 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3108 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3109 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3110 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3111 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3112 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3113 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3114 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3115 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3116 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3117 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3118 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3119 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3120 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3121 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3122 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3123 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3124 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3125 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3126 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3127 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3128 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3129 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3130 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3131 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3132 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3133 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3134 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3135 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3136 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3137 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3138 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3139 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3140 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3141 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3142 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3143 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3144 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3145 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3146 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3147 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3148 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3149 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3150 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3151 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3152 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3153 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3154 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3155 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3156 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3157 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3158 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3159 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3160 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3161 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3162 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3163 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3164 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3165 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3166 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3167 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3168 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3169 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3170 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3171 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3172 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3173 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3174 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3175 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3176 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3177 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3178 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3179 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3180 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3181 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3182 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3183 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3184 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3185 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3186 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3187 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3188 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3189 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3190 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3191 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3192 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3193 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3194 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3195 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3196 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3197 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3198 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3199 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3200 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3201 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3202 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3203 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3204 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3205 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3206 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3207 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3208 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3209 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3210 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3211 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3212 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3213 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3214 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3215 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3216 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3217 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3218 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3219 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3220 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3221 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3222 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3223 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3224 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3225 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3226 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3227 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3228 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3229 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3230 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3231 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3232 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3233 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3234 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3235 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3236 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3237 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3238 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3239 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3240 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3241 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3242 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3243 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3244};
3245
3246static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3247 [MMSS_SPDM_RESET] = { 0x0200 },
3248 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3249 [VENUS0_RESET] = { 0x1020 },
3250 [VPU_RESET] = { 0x1400 },
3251 [MDSS_RESET] = { 0x2300 },
3252 [AVSYNC_RESET] = { 0x2400 },
3253 [CAMSS_PHY0_RESET] = { 0x3020 },
3254 [CAMSS_PHY1_RESET] = { 0x3050 },
3255 [CAMSS_PHY2_RESET] = { 0x3080 },
3256 [CAMSS_CSI0_RESET] = { 0x30b0 },
3257 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3258 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3259 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3260 [CAMSS_CSI1_RESET] = { 0x3120 },
3261 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3262 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3263 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3264 [CAMSS_CSI2_RESET] = { 0x3180 },
3265 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3266 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3267 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3268 [CAMSS_CSI3_RESET] = { 0x31e0 },
3269 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3270 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3271 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3272 [CAMSS_ISPIF_RESET] = { 0x3220 },
3273 [CAMSS_CCI_RESET] = { 0x3340 },
3274 [CAMSS_MCLK0_RESET] = { 0x3380 },
3275 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3276 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3277 [CAMSS_MCLK3_RESET] = { 0x3410 },
3278 [CAMSS_GP0_RESET] = { 0x3440 },
3279 [CAMSS_GP1_RESET] = { 0x3470 },
3280 [CAMSS_TOP_RESET] = { 0x3480 },
3281 [CAMSS_AHB_RESET] = { 0x3488 },
3282 [CAMSS_MICRO_RESET] = { 0x3490 },
3283 [CAMSS_JPEG_RESET] = { 0x35a0 },
3284 [CAMSS_VFE_RESET] = { 0x36a0 },
3285 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3286 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3287 [OXILI_RESET] = { 0x4020 },
3288 [OXILICX_RESET] = { 0x4030 },
3289 [OCMEMCX_RESET] = { 0x4050 },
3290 [MMSS_RBCRP_RESET] = { 0x4080 },
3291 [MMSSNOCAHB_RESET] = { 0x5020 },
3292 [MMSSNOCAXI_RESET] = { 0x5060 },
3293};
3294
3295static const struct regmap_config mmcc_apq8084_regmap_config = {
3296 .reg_bits = 32,
3297 .reg_stride = 4,
3298 .val_bits = 32,
3299 .max_register = 0x5104,
3300 .fast_io = true,
3301};
3302
3303static const struct qcom_cc_desc mmcc_apq8084_desc = {
3304 .config = &mmcc_apq8084_regmap_config,
3305 .clks = mmcc_apq8084_clocks,
3306 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3307 .resets = mmcc_apq8084_resets,
3308 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3309};
3310
3311static const struct of_device_id mmcc_apq8084_match_table[] = {
3312 { .compatible = "qcom,mmcc-apq8084" },
3313 { }
3314};
3315MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3316
3317static int mmcc_apq8084_probe(struct platform_device *pdev)
3318{
3319 int ret;
3320 struct regmap *regmap;
3321
3322 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3323 if (ret)
3324 return ret;
3325
3326 regmap = dev_get_regmap(&pdev->dev, NULL);
3327 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3328 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3329
3330 return 0;
3331}
3332
3333static int mmcc_apq8084_remove(struct platform_device *pdev)
3334{
3335 qcom_cc_remove(pdev);
3336 return 0;
3337}
3338
3339static struct platform_driver mmcc_apq8084_driver = {
3340 .probe = mmcc_apq8084_probe,
3341 .remove = mmcc_apq8084_remove,
3342 .driver = {
3343 .name = "mmcc-apq8084",
3344 .owner = THIS_MODULE,
3345 .of_match_table = mmcc_apq8084_match_table,
3346 },
3347};
3348module_platform_driver(mmcc_apq8084_driver);
3349
3350MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3351MODULE_LICENSE("GPL v2");
3352MODULE_ALIAS("platform:mmcc-apq8084");
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 4c449b3170f6..2e80a219b8ea 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -37,6 +37,9 @@
37#define P_PLL8 1 37#define P_PLL8 1
38#define P_PLL2 2 38#define P_PLL2 2
39#define P_PLL3 3 39#define P_PLL3 3
40#define P_PLL15 3
41
42#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
40 43
41static u8 mmcc_pxo_pll8_pll2_map[] = { 44static u8 mmcc_pxo_pll8_pll2_map[] = {
42 [P_PXO] = 0, 45 [P_PXO] = 0,
@@ -57,10 +60,24 @@ static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
57 [P_PLL3] = 3, 60 [P_PLL3] = 3,
58}; 61};
59 62
60static const char *mmcc_pxo_pll8_pll2_pll3[] = { 63static const char *mmcc_pxo_pll8_pll2_pll15[] = {
61 "pxo", 64 "pxo",
65 "pll8_vote",
62 "pll2", 66 "pll2",
67 "pll15",
68};
69
70static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
71 [P_PXO] = 0,
72 [P_PLL8] = 2,
73 [P_PLL2] = 1,
74 [P_PLL15] = 3,
75};
76
77static const char *mmcc_pxo_pll8_pll2_pll3[] = {
78 "pxo",
63 "pll8_vote", 79 "pll8_vote",
80 "pll2",
64 "pll3", 81 "pll3",
65}; 82};
66 83
@@ -80,6 +97,36 @@ static struct clk_pll pll2 = {
80 }, 97 },
81}; 98};
82 99
100static struct clk_pll pll15 = {
101 .l_reg = 0x33c,
102 .m_reg = 0x340,
103 .n_reg = 0x344,
104 .config_reg = 0x348,
105 .mode_reg = 0x338,
106 .status_reg = 0x350,
107 .status_bit = 16,
108 .clkr.hw.init = &(struct clk_init_data){
109 .name = "pll15",
110 .parent_names = (const char *[]){ "pxo" },
111 .num_parents = 1,
112 .ops = &clk_pll_ops,
113 },
114};
115
116static const struct pll_config pll15_config = {
117 .l = 33,
118 .m = 1,
119 .n = 3,
120 .vco_val = 0x2 << 16,
121 .vco_mask = 0x3 << 16,
122 .pre_div_val = 0x0,
123 .pre_div_mask = BIT(19),
124 .post_div_val = 0x0,
125 .post_div_mask = 0x3 << 20,
126 .mn_ena_mask = BIT(22),
127 .main_output_mask = BIT(23),
128};
129
83static struct freq_tbl clk_tbl_cam[] = { 130static struct freq_tbl clk_tbl_cam[] = {
84 { 6000000, P_PLL8, 4, 1, 16 }, 131 { 6000000, P_PLL8, 4, 1, 16 },
85 { 8000000, P_PLL8, 4, 1, 12 }, 132 { 8000000, P_PLL8, 4, 1, 12 },
@@ -710,18 +757,18 @@ static struct clk_branch csiphy2_timer_clk = {
710}; 757};
711 758
712static struct freq_tbl clk_tbl_gfx2d[] = { 759static struct freq_tbl clk_tbl_gfx2d[] = {
713 { 27000000, P_PXO, 1, 0 }, 760 F_MN( 27000000, P_PXO, 1, 0),
714 { 48000000, P_PLL8, 1, 8 }, 761 F_MN( 48000000, P_PLL8, 1, 8),
715 { 54857000, P_PLL8, 1, 7 }, 762 F_MN( 54857000, P_PLL8, 1, 7),
716 { 64000000, P_PLL8, 1, 6 }, 763 F_MN( 64000000, P_PLL8, 1, 6),
717 { 76800000, P_PLL8, 1, 5 }, 764 F_MN( 76800000, P_PLL8, 1, 5),
718 { 96000000, P_PLL8, 1, 4 }, 765 F_MN( 96000000, P_PLL8, 1, 4),
719 { 128000000, P_PLL8, 1, 3 }, 766 F_MN(128000000, P_PLL8, 1, 3),
720 { 145455000, P_PLL2, 2, 11 }, 767 F_MN(145455000, P_PLL2, 2, 11),
721 { 160000000, P_PLL2, 1, 5 }, 768 F_MN(160000000, P_PLL2, 1, 5),
722 { 177778000, P_PLL2, 2, 9 }, 769 F_MN(177778000, P_PLL2, 2, 9),
723 { 200000000, P_PLL2, 1, 4 }, 770 F_MN(200000000, P_PLL2, 1, 4),
724 { 228571000, P_PLL2, 2, 7 }, 771 F_MN(228571000, P_PLL2, 2, 7),
725 { } 772 { }
726}; 773};
727 774
@@ -842,22 +889,43 @@ static struct clk_branch gfx2d1_clk = {
842}; 889};
843 890
844static struct freq_tbl clk_tbl_gfx3d[] = { 891static struct freq_tbl clk_tbl_gfx3d[] = {
845 { 27000000, P_PXO, 1, 0 }, 892 F_MN( 27000000, P_PXO, 1, 0),
846 { 48000000, P_PLL8, 1, 8 }, 893 F_MN( 48000000, P_PLL8, 1, 8),
847 { 54857000, P_PLL8, 1, 7 }, 894 F_MN( 54857000, P_PLL8, 1, 7),
848 { 64000000, P_PLL8, 1, 6 }, 895 F_MN( 64000000, P_PLL8, 1, 6),
849 { 76800000, P_PLL8, 1, 5 }, 896 F_MN( 76800000, P_PLL8, 1, 5),
850 { 96000000, P_PLL8, 1, 4 }, 897 F_MN( 96000000, P_PLL8, 1, 4),
851 { 128000000, P_PLL8, 1, 3 }, 898 F_MN(128000000, P_PLL8, 1, 3),
852 { 145455000, P_PLL2, 2, 11 }, 899 F_MN(145455000, P_PLL2, 2, 11),
853 { 160000000, P_PLL2, 1, 5 }, 900 F_MN(160000000, P_PLL2, 1, 5),
854 { 177778000, P_PLL2, 2, 9 }, 901 F_MN(177778000, P_PLL2, 2, 9),
855 { 200000000, P_PLL2, 1, 4 }, 902 F_MN(200000000, P_PLL2, 1, 4),
856 { 228571000, P_PLL2, 2, 7 }, 903 F_MN(228571000, P_PLL2, 2, 7),
857 { 266667000, P_PLL2, 1, 3 }, 904 F_MN(266667000, P_PLL2, 1, 3),
858 { 300000000, P_PLL3, 1, 4 }, 905 F_MN(300000000, P_PLL3, 1, 4),
859 { 320000000, P_PLL2, 2, 5 }, 906 F_MN(320000000, P_PLL2, 2, 5),
860 { 400000000, P_PLL2, 1, 2 }, 907 F_MN(400000000, P_PLL2, 1, 2),
908 { }
909};
910
911static struct freq_tbl clk_tbl_gfx3d_8064[] = {
912 F_MN( 27000000, P_PXO, 0, 0),
913 F_MN( 48000000, P_PLL8, 1, 8),
914 F_MN( 54857000, P_PLL8, 1, 7),
915 F_MN( 64000000, P_PLL8, 1, 6),
916 F_MN( 76800000, P_PLL8, 1, 5),
917 F_MN( 96000000, P_PLL8, 1, 4),
918 F_MN(128000000, P_PLL8, 1, 3),
919 F_MN(145455000, P_PLL2, 2, 11),
920 F_MN(160000000, P_PLL2, 1, 5),
921 F_MN(177778000, P_PLL2, 2, 9),
922 F_MN(192000000, P_PLL8, 1, 2),
923 F_MN(200000000, P_PLL2, 1, 4),
924 F_MN(228571000, P_PLL2, 2, 7),
925 F_MN(266667000, P_PLL2, 1, 3),
926 F_MN(320000000, P_PLL2, 2, 5),
927 F_MN(400000000, P_PLL2, 1, 2),
928 F_MN(450000000, P_PLL15, 1, 2),
861 { } 929 { }
862}; 930};
863 931
@@ -897,12 +965,19 @@ static struct clk_dyn_rcg gfx3d_src = {
897 .hw.init = &(struct clk_init_data){ 965 .hw.init = &(struct clk_init_data){
898 .name = "gfx3d_src", 966 .name = "gfx3d_src",
899 .parent_names = mmcc_pxo_pll8_pll2_pll3, 967 .parent_names = mmcc_pxo_pll8_pll2_pll3,
900 .num_parents = 3, 968 .num_parents = 4,
901 .ops = &clk_dyn_rcg_ops, 969 .ops = &clk_dyn_rcg_ops,
902 }, 970 },
903 }, 971 },
904}; 972};
905 973
974static const struct clk_init_data gfx3d_8064_init = {
975 .name = "gfx3d_src",
976 .parent_names = mmcc_pxo_pll8_pll2_pll15,
977 .num_parents = 4,
978 .ops = &clk_dyn_rcg_ops,
979};
980
906static struct clk_branch gfx3d_clk = { 981static struct clk_branch gfx3d_clk = {
907 .halt_reg = 0x01c8, 982 .halt_reg = 0x01c8,
908 .halt_bit = 4, 983 .halt_bit = 4,
@@ -919,6 +994,91 @@ static struct clk_branch gfx3d_clk = {
919 }, 994 },
920}; 995};
921 996
997static struct freq_tbl clk_tbl_vcap[] = {
998 F_MN( 27000000, P_PXO, 0, 0),
999 F_MN( 54860000, P_PLL8, 1, 7),
1000 F_MN( 64000000, P_PLL8, 1, 6),
1001 F_MN( 76800000, P_PLL8, 1, 5),
1002 F_MN(128000000, P_PLL8, 1, 3),
1003 F_MN(160000000, P_PLL2, 1, 5),
1004 F_MN(200000000, P_PLL2, 1, 4),
1005 { }
1006};
1007
1008static struct clk_dyn_rcg vcap_src = {
1009 .ns_reg = 0x021c,
1010 .md_reg[0] = 0x01ec,
1011 .md_reg[1] = 0x0218,
1012 .mn[0] = {
1013 .mnctr_en_bit = 8,
1014 .mnctr_reset_bit = 23,
1015 .mnctr_mode_shift = 9,
1016 .n_val_shift = 18,
1017 .m_val_shift = 4,
1018 .width = 4,
1019 },
1020 .mn[1] = {
1021 .mnctr_en_bit = 5,
1022 .mnctr_reset_bit = 22,
1023 .mnctr_mode_shift = 6,
1024 .n_val_shift = 14,
1025 .m_val_shift = 4,
1026 .width = 4,
1027 },
1028 .s[0] = {
1029 .src_sel_shift = 3,
1030 .parent_map = mmcc_pxo_pll8_pll2_map,
1031 },
1032 .s[1] = {
1033 .src_sel_shift = 0,
1034 .parent_map = mmcc_pxo_pll8_pll2_map,
1035 },
1036 .mux_sel_bit = 11,
1037 .freq_tbl = clk_tbl_vcap,
1038 .clkr = {
1039 .enable_reg = 0x0178,
1040 .enable_mask = BIT(2),
1041 .hw.init = &(struct clk_init_data){
1042 .name = "vcap_src",
1043 .parent_names = mmcc_pxo_pll8_pll2,
1044 .num_parents = 3,
1045 .ops = &clk_dyn_rcg_ops,
1046 },
1047 },
1048};
1049
1050static struct clk_branch vcap_clk = {
1051 .halt_reg = 0x0240,
1052 .halt_bit = 15,
1053 .clkr = {
1054 .enable_reg = 0x0178,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(struct clk_init_data){
1057 .name = "vcap_clk",
1058 .parent_names = (const char *[]){ "vcap_src" },
1059 .num_parents = 1,
1060 .ops = &clk_branch_ops,
1061 .flags = CLK_SET_RATE_PARENT,
1062 },
1063 },
1064};
1065
1066static struct clk_branch vcap_npl_clk = {
1067 .halt_reg = 0x0240,
1068 .halt_bit = 25,
1069 .clkr = {
1070 .enable_reg = 0x0178,
1071 .enable_mask = BIT(13),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "vcap_npl_clk",
1074 .parent_names = (const char *[]){ "vcap_src" },
1075 .num_parents = 1,
1076 .ops = &clk_branch_ops,
1077 .flags = CLK_SET_RATE_PARENT,
1078 },
1079 },
1080};
1081
922static struct freq_tbl clk_tbl_ijpeg[] = { 1082static struct freq_tbl clk_tbl_ijpeg[] = {
923 { 27000000, P_PXO, 1, 0, 0 }, 1083 { 27000000, P_PXO, 1, 0, 0 },
924 { 36570000, P_PLL8, 1, 2, 21 }, 1084 { 36570000, P_PLL8, 1, 2, 21 },
@@ -995,7 +1155,7 @@ static struct clk_rcg jpegd_src = {
995 .ns_reg = 0x00ac, 1155 .ns_reg = 0x00ac,
996 .p = { 1156 .p = {
997 .pre_div_shift = 12, 1157 .pre_div_shift = 12,
998 .pre_div_width = 2, 1158 .pre_div_width = 4,
999 }, 1159 },
1000 .s = { 1160 .s = {
1001 .src_sel_shift = 0, 1161 .src_sel_shift = 0,
@@ -1115,7 +1275,7 @@ static struct clk_branch mdp_lut_clk = {
1115 .enable_reg = 0x016c, 1275 .enable_reg = 0x016c,
1116 .enable_mask = BIT(0), 1276 .enable_mask = BIT(0),
1117 .hw.init = &(struct clk_init_data){ 1277 .hw.init = &(struct clk_init_data){
1118 .parent_names = (const char *[]){ "mdp_clk" }, 1278 .parent_names = (const char *[]){ "mdp_src" },
1119 .num_parents = 1, 1279 .num_parents = 1,
1120 .name = "mdp_lut_clk", 1280 .name = "mdp_lut_clk",
1121 .ops = &clk_branch_ops, 1281 .ops = &clk_branch_ops,
@@ -1218,12 +1378,7 @@ static const char *mmcc_pxo_hdmi[] = {
1218}; 1378};
1219 1379
1220static struct freq_tbl clk_tbl_tv[] = { 1380static struct freq_tbl clk_tbl_tv[] = {
1221 { 25200000, P_HDMI_PLL, 1, 0, 0 }, 1381 { .src = P_HDMI_PLL, .pre_div = 1 },
1222 { 27000000, P_HDMI_PLL, 1, 0, 0 },
1223 { 27030000, P_HDMI_PLL, 1, 0, 0 },
1224 { 74250000, P_HDMI_PLL, 1, 0, 0 },
1225 { 108000000, P_HDMI_PLL, 1, 0, 0 },
1226 { 148500000, P_HDMI_PLL, 1, 0, 0 },
1227 { } 1382 { }
1228}; 1383};
1229 1384
@@ -1254,7 +1409,7 @@ static struct clk_rcg tv_src = {
1254 .name = "tv_src", 1409 .name = "tv_src",
1255 .parent_names = mmcc_pxo_hdmi, 1410 .parent_names = mmcc_pxo_hdmi,
1256 .num_parents = 2, 1411 .num_parents = 2,
1257 .ops = &clk_rcg_ops, 1412 .ops = &clk_rcg_bypass_ops,
1258 .flags = CLK_SET_RATE_PARENT, 1413 .flags = CLK_SET_RATE_PARENT,
1259 }, 1414 },
1260 }, 1415 },
@@ -1326,6 +1481,38 @@ static struct clk_branch hdmi_tv_clk = {
1326 }, 1481 },
1327}; 1482};
1328 1483
1484static struct clk_branch rgb_tv_clk = {
1485 .halt_reg = 0x0240,
1486 .halt_bit = 27,
1487 .clkr = {
1488 .enable_reg = 0x0124,
1489 .enable_mask = BIT(14),
1490 .hw.init = &(struct clk_init_data){
1491 .parent_names = tv_src_name,
1492 .num_parents = 1,
1493 .name = "rgb_tv_clk",
1494 .ops = &clk_branch_ops,
1495 .flags = CLK_SET_RATE_PARENT,
1496 },
1497 },
1498};
1499
1500static struct clk_branch npl_tv_clk = {
1501 .halt_reg = 0x0240,
1502 .halt_bit = 26,
1503 .clkr = {
1504 .enable_reg = 0x0124,
1505 .enable_mask = BIT(16),
1506 .hw.init = &(struct clk_init_data){
1507 .parent_names = tv_src_name,
1508 .num_parents = 1,
1509 .name = "npl_tv_clk",
1510 .ops = &clk_branch_ops,
1511 .flags = CLK_SET_RATE_PARENT,
1512 },
1513 },
1514};
1515
1329static struct clk_branch hdmi_app_clk = { 1516static struct clk_branch hdmi_app_clk = {
1330 .halt_reg = 0x01cc, 1517 .halt_reg = 0x01cc,
1331 .halt_bit = 25, 1518 .halt_bit = 25,
@@ -1342,15 +1529,15 @@ static struct clk_branch hdmi_app_clk = {
1342}; 1529};
1343 1530
1344static struct freq_tbl clk_tbl_vcodec[] = { 1531static struct freq_tbl clk_tbl_vcodec[] = {
1345 { 27000000, P_PXO, 1, 0 }, 1532 F_MN( 27000000, P_PXO, 1, 0),
1346 { 32000000, P_PLL8, 1, 12 }, 1533 F_MN( 32000000, P_PLL8, 1, 12),
1347 { 48000000, P_PLL8, 1, 8 }, 1534 F_MN( 48000000, P_PLL8, 1, 8),
1348 { 54860000, P_PLL8, 1, 7 }, 1535 F_MN( 54860000, P_PLL8, 1, 7),
1349 { 96000000, P_PLL8, 1, 4 }, 1536 F_MN( 96000000, P_PLL8, 1, 4),
1350 { 133330000, P_PLL2, 1, 6 }, 1537 F_MN(133330000, P_PLL2, 1, 6),
1351 { 200000000, P_PLL2, 1, 4 }, 1538 F_MN(200000000, P_PLL2, 1, 4),
1352 { 228570000, P_PLL2, 2, 7 }, 1539 F_MN(228570000, P_PLL2, 2, 7),
1353 { 266670000, P_PLL2, 1, 3 }, 1540 F_MN(266670000, P_PLL2, 1, 3),
1354 { } 1541 { }
1355}; 1542};
1356 1543
@@ -1701,6 +1888,22 @@ static struct clk_branch rot_axi_clk = {
1701 }, 1888 },
1702}; 1889};
1703 1890
1891static struct clk_branch vcap_axi_clk = {
1892 .halt_reg = 0x0240,
1893 .halt_bit = 20,
1894 .hwcg_reg = 0x0244,
1895 .hwcg_bit = 11,
1896 .clkr = {
1897 .enable_reg = 0x0244,
1898 .enable_mask = BIT(12),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "vcap_axi_clk",
1901 .ops = &clk_branch_ops,
1902 .flags = CLK_IS_ROOT,
1903 },
1904 },
1905};
1906
1704static struct clk_branch vpe_axi_clk = { 1907static struct clk_branch vpe_axi_clk = {
1705 .hwcg_reg = 0x0020, 1908 .hwcg_reg = 0x0020,
1706 .hwcg_bit = 27, 1909 .hwcg_bit = 27,
@@ -2003,6 +2206,20 @@ static struct clk_branch tv_enc_ahb_clk = {
2003 }, 2206 },
2004}; 2207};
2005 2208
2209static struct clk_branch vcap_ahb_clk = {
2210 .halt_reg = 0x0240,
2211 .halt_bit = 23,
2212 .clkr = {
2213 .enable_reg = 0x0248,
2214 .enable_mask = BIT(1),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "vcap_ahb_clk",
2217 .ops = &clk_branch_ops,
2218 .flags = CLK_IS_ROOT,
2219 },
2220 },
2221};
2222
2006static struct clk_branch vcodec_ahb_clk = { 2223static struct clk_branch vcodec_ahb_clk = {
2007 .hwcg_reg = 0x0038, 2224 .hwcg_reg = 0x0038,
2008 .hwcg_bit = 26, 2225 .hwcg_bit = 26,
@@ -2215,6 +2432,175 @@ static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2215 [CSI_RDI2_RESET] = { 0x0214 }, 2432 [CSI_RDI2_RESET] = { 0x0214 },
2216}; 2433};
2217 2434
2435static struct clk_regmap *mmcc_apq8064_clks[] = {
2436 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2437 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2438 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2439 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2440 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2441 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2442 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2443 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2444 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2445 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2446 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2447 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2448 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2449 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2450 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2451 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2452 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2453 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2454 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2455 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2456 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2457 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2458 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2459 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2460 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2461 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2462 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2463 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2464 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2465 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2466 [CSI0_SRC] = &csi0_src.clkr,
2467 [CSI0_CLK] = &csi0_clk.clkr,
2468 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2469 [CSI1_SRC] = &csi1_src.clkr,
2470 [CSI1_CLK] = &csi1_clk.clkr,
2471 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2472 [CSI2_SRC] = &csi2_src.clkr,
2473 [CSI2_CLK] = &csi2_clk.clkr,
2474 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2475 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2476 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2477 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2478 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2479 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2480 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2481 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2482 [GFX3D_SRC] = &gfx3d_src.clkr,
2483 [GFX3D_CLK] = &gfx3d_clk.clkr,
2484 [IJPEG_SRC] = &ijpeg_src.clkr,
2485 [IJPEG_CLK] = &ijpeg_clk.clkr,
2486 [JPEGD_SRC] = &jpegd_src.clkr,
2487 [JPEGD_CLK] = &jpegd_clk.clkr,
2488 [MDP_SRC] = &mdp_src.clkr,
2489 [MDP_CLK] = &mdp_clk.clkr,
2490 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2491 [ROT_SRC] = &rot_src.clkr,
2492 [ROT_CLK] = &rot_clk.clkr,
2493 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2494 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2495 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2496 [TV_SRC] = &tv_src.clkr,
2497 [VCODEC_SRC] = &vcodec_src.clkr,
2498 [VCODEC_CLK] = &vcodec_clk.clkr,
2499 [VFE_SRC] = &vfe_src.clkr,
2500 [VFE_CLK] = &vfe_clk.clkr,
2501 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2502 [VPE_SRC] = &vpe_src.clkr,
2503 [VPE_CLK] = &vpe_clk.clkr,
2504 [CAMCLK0_SRC] = &camclk0_src.clkr,
2505 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2506 [CAMCLK1_SRC] = &camclk1_src.clkr,
2507 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2508 [CAMCLK2_SRC] = &camclk2_src.clkr,
2509 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2510 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2511 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2512 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2513 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2514 [PLL2] = &pll2.clkr,
2515 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2516 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2517 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2518 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2519 [VCAP_SRC] = &vcap_src.clkr,
2520 [VCAP_CLK] = &vcap_clk.clkr,
2521 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2522 [PLL15] = &pll15.clkr,
2523};
2524
2525static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2526 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2527 [VCAP_AXI_RESET] = { 0x0208, 16 },
2528 [VPE_AXI_RESET] = { 0x0208, 15 },
2529 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2530 [MPD_AXI_RESET] = { 0x0208, 13 },
2531 [VFE_AXI_RESET] = { 0x0208, 9 },
2532 [SP_AXI_RESET] = { 0x0208, 8 },
2533 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2534 [ROT_AXI_RESET] = { 0x0208, 6 },
2535 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2536 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2537 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2538 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2539 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2540 [FAB_S0_AXI_RESET] = { 0x0208 },
2541 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2542 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2543 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2544 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2545 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2546 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2547 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2548 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2549 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2550 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2551 [APU_AHB_RESET] = { 0x020c, 18 },
2552 [CSI_AHB_RESET] = { 0x020c, 17 },
2553 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2554 [VPE_AHB_RESET] = { 0x020c, 14 },
2555 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2556 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2557 [HDMI_AHB_RESET] = { 0x020c, 9 },
2558 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2559 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2560 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2561 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2562 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2563 [MDP_AHB_RESET] = { 0x020c, 3 },
2564 [ROT_AHB_RESET] = { 0x020c, 2 },
2565 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2566 [VFE_AHB_RESET] = { 0x020c, 0 },
2567 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2568 [VCAP_AHB_RESET] = { 0x0200, 2 },
2569 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2570 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2571 [CSIPHY2_RESET] = { 0x0210, 31 },
2572 [CSI_PIX1_RESET] = { 0x0210, 30 },
2573 [CSIPHY0_RESET] = { 0x0210, 29 },
2574 [CSIPHY1_RESET] = { 0x0210, 28 },
2575 [CSI_RDI_RESET] = { 0x0210, 27 },
2576 [CSI_PIX_RESET] = { 0x0210, 26 },
2577 [DSI2_RESET] = { 0x0210, 25 },
2578 [VFE_CSI_RESET] = { 0x0210, 24 },
2579 [MDP_RESET] = { 0x0210, 21 },
2580 [AMP_RESET] = { 0x0210, 20 },
2581 [JPEGD_RESET] = { 0x0210, 19 },
2582 [CSI1_RESET] = { 0x0210, 18 },
2583 [VPE_RESET] = { 0x0210, 17 },
2584 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2585 [VFE_RESET] = { 0x0210, 15 },
2586 [GFX3D_RESET] = { 0x0210, 12 },
2587 [HDMI_RESET] = { 0x0210, 11 },
2588 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2589 [IJPEG_RESET] = { 0x0210, 9 },
2590 [CSI0_RESET] = { 0x0210, 8 },
2591 [DSI_RESET] = { 0x0210, 7 },
2592 [VCODEC_RESET] = { 0x0210, 6 },
2593 [MDP_TV_RESET] = { 0x0210, 4 },
2594 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2595 [ROT_RESET] = { 0x0210, 2 },
2596 [TV_HDMI_RESET] = { 0x0210, 1 },
2597 [VCAP_NPL_RESET] = { 0x0214, 4 },
2598 [VCAP_RESET] = { 0x0214, 3 },
2599 [CSI2_RESET] = { 0x0214, 2 },
2600 [CSI_RDI1_RESET] = { 0x0214, 1 },
2601 [CSI_RDI2_RESET] = { 0x0214 },
2602};
2603
2218static const struct regmap_config mmcc_msm8960_regmap_config = { 2604static const struct regmap_config mmcc_msm8960_regmap_config = {
2219 .reg_bits = 32, 2605 .reg_bits = 32,
2220 .reg_stride = 4, 2606 .reg_stride = 4,
@@ -2223,6 +2609,14 @@ static const struct regmap_config mmcc_msm8960_regmap_config = {
2223 .fast_io = true, 2609 .fast_io = true,
2224}; 2610};
2225 2611
2612static const struct regmap_config mmcc_apq8064_regmap_config = {
2613 .reg_bits = 32,
2614 .reg_stride = 4,
2615 .val_bits = 32,
2616 .max_register = 0x350,
2617 .fast_io = true,
2618};
2619
2226static const struct qcom_cc_desc mmcc_msm8960_desc = { 2620static const struct qcom_cc_desc mmcc_msm8960_desc = {
2227 .config = &mmcc_msm8960_regmap_config, 2621 .config = &mmcc_msm8960_regmap_config,
2228 .clks = mmcc_msm8960_clks, 2622 .clks = mmcc_msm8960_clks,
@@ -2231,15 +2625,47 @@ static const struct qcom_cc_desc mmcc_msm8960_desc = {
2231 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), 2625 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2232}; 2626};
2233 2627
2628static const struct qcom_cc_desc mmcc_apq8064_desc = {
2629 .config = &mmcc_apq8064_regmap_config,
2630 .clks = mmcc_apq8064_clks,
2631 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2632 .resets = mmcc_apq8064_resets,
2633 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2634};
2635
2234static const struct of_device_id mmcc_msm8960_match_table[] = { 2636static const struct of_device_id mmcc_msm8960_match_table[] = {
2235 { .compatible = "qcom,mmcc-msm8960" }, 2637 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2638 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
2236 { } 2639 { }
2237}; 2640};
2238MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); 2641MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2239 2642
2240static int mmcc_msm8960_probe(struct platform_device *pdev) 2643static int mmcc_msm8960_probe(struct platform_device *pdev)
2241{ 2644{
2242 return qcom_cc_probe(pdev, &mmcc_msm8960_desc); 2645 const struct of_device_id *match;
2646 struct regmap *regmap;
2647 bool is_8064;
2648 struct device *dev = &pdev->dev;
2649
2650 match = of_match_device(mmcc_msm8960_match_table, dev);
2651 if (!match)
2652 return -EINVAL;
2653
2654 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2655 if (is_8064) {
2656 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2657 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2658 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2659 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2660 }
2661
2662 regmap = qcom_cc_map(pdev, match->data);
2663 if (IS_ERR(regmap))
2664 return PTR_ERR(regmap);
2665
2666 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2667
2668 return qcom_cc_really_probe(pdev, match->data, regmap);
2243} 2669}
2244 2670
2245static int mmcc_msm8960_remove(struct platform_device *pdev) 2671static int mmcc_msm8960_remove(struct platform_device *pdev)
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index c65b90515872..bc8f519c47aa 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2547,18 +2547,16 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2547 2547
2548static int mmcc_msm8974_probe(struct platform_device *pdev) 2548static int mmcc_msm8974_probe(struct platform_device *pdev)
2549{ 2549{
2550 int ret;
2551 struct regmap *regmap; 2550 struct regmap *regmap;
2552 2551
2553 ret = qcom_cc_probe(pdev, &mmcc_msm8974_desc); 2552 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2554 if (ret) 2553 if (IS_ERR(regmap))
2555 return ret; 2554 return PTR_ERR(regmap);
2556 2555
2557 regmap = dev_get_regmap(&pdev->dev, NULL);
2558 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 2556 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2559 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 2557 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2560 2558
2561 return 0; 2559 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2562} 2560}
2563 2561
2564static int mmcc_msm8974_remove(struct platform_device *pdev) 2562static int mmcc_msm8974_remove(struct platform_device *pdev)
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 09:48:48 -0400