diff options
author | Georgi Djakov <georgi.djakov@linaro.org> | 2015-03-20 12:30:24 -0400 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-03-23 18:50:53 -0400 |
commit | 7f218978f10693f65e35b0bbcdcd539fbe78221a (patch) | |
tree | 7f83ff1dfa6340053dc005784ff9930d4e101807 /drivers/clk/qcom | |
parent | 0b21503dbbfa669dbd847b33578d4041513cddb2 (diff) |
clk: qcom: Fix clk_get_parent function return value
According to the common clock framework API, the clk_get_parent() function
should return u8. Currently we are returning negative values on error. Fix
this and use the default parent in case of an error.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r-- | drivers/clk/qcom/clk-rcg.c | 26 | ||||
-rw-r--r-- | drivers/clk/qcom/clk-rcg2.c | 7 |
2 files changed, 24 insertions, 9 deletions
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index 466f30ca65c2..59a093e56366 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c | |||
@@ -47,15 +47,20 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw) | |||
47 | struct clk_rcg *rcg = to_clk_rcg(hw); | 47 | struct clk_rcg *rcg = to_clk_rcg(hw); |
48 | int num_parents = __clk_get_num_parents(hw->clk); | 48 | int num_parents = __clk_get_num_parents(hw->clk); |
49 | u32 ns; | 49 | u32 ns; |
50 | int i; | 50 | int i, ret; |
51 | 51 | ||
52 | regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); | 52 | ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); |
53 | if (ret) | ||
54 | goto err; | ||
53 | ns = ns_to_src(&rcg->s, ns); | 55 | ns = ns_to_src(&rcg->s, ns); |
54 | for (i = 0; i < num_parents; i++) | 56 | for (i = 0; i < num_parents; i++) |
55 | if (ns == rcg->s.parent_map[i]) | 57 | if (ns == rcg->s.parent_map[i]) |
56 | return i; | 58 | return i; |
57 | 59 | ||
58 | return -EINVAL; | 60 | err: |
61 | pr_debug("%s: Clock %s has invalid parent, using default.\n", | ||
62 | __func__, __clk_get_name(hw->clk)); | ||
63 | return 0; | ||
59 | } | 64 | } |
60 | 65 | ||
61 | static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) | 66 | static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) |
@@ -70,21 +75,28 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) | |||
70 | int num_parents = __clk_get_num_parents(hw->clk); | 75 | int num_parents = __clk_get_num_parents(hw->clk); |
71 | u32 ns, reg; | 76 | u32 ns, reg; |
72 | int bank; | 77 | int bank; |
73 | int i; | 78 | int i, ret; |
74 | struct src_sel *s; | 79 | struct src_sel *s; |
75 | 80 | ||
76 | regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); | 81 | ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); |
82 | if (ret) | ||
83 | goto err; | ||
77 | bank = reg_to_bank(rcg, reg); | 84 | bank = reg_to_bank(rcg, reg); |
78 | s = &rcg->s[bank]; | 85 | s = &rcg->s[bank]; |
79 | 86 | ||
80 | regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); | 87 | ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); |
88 | if (ret) | ||
89 | goto err; | ||
81 | ns = ns_to_src(s, ns); | 90 | ns = ns_to_src(s, ns); |
82 | 91 | ||
83 | for (i = 0; i < num_parents; i++) | 92 | for (i = 0; i < num_parents; i++) |
84 | if (ns == s->parent_map[i]) | 93 | if (ns == s->parent_map[i]) |
85 | return i; | 94 | return i; |
86 | 95 | ||
87 | return -EINVAL; | 96 | err: |
97 | pr_debug("%s: Clock %s has invalid parent, using default.\n", | ||
98 | __func__, __clk_get_name(hw->clk)); | ||
99 | return 0; | ||
88 | } | 100 | } |
89 | 101 | ||
90 | static int clk_rcg_set_parent(struct clk_hw *hw, u8 index) | 102 | static int clk_rcg_set_parent(struct clk_hw *hw, u8 index) |
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 381f27469a9c..10c2e45832b8 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c | |||
@@ -69,7 +69,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) | |||
69 | 69 | ||
70 | ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); | 70 | ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); |
71 | if (ret) | 71 | if (ret) |
72 | return ret; | 72 | goto err; |
73 | 73 | ||
74 | cfg &= CFG_SRC_SEL_MASK; | 74 | cfg &= CFG_SRC_SEL_MASK; |
75 | cfg >>= CFG_SRC_SEL_SHIFT; | 75 | cfg >>= CFG_SRC_SEL_SHIFT; |
@@ -78,7 +78,10 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) | |||
78 | if (cfg == rcg->parent_map[i]) | 78 | if (cfg == rcg->parent_map[i]) |
79 | return i; | 79 | return i; |
80 | 80 | ||
81 | return -EINVAL; | 81 | err: |
82 | pr_debug("%s: Clock %s has invalid parent, using default.\n", | ||
83 | __func__, __clk_get_name(hw->clk)); | ||
84 | return 0; | ||
82 | } | 85 | } |
83 | 86 | ||
84 | static int update_config(struct clk_rcg2 *rcg) | 87 | static int update_config(struct clk_rcg2 *rcg) |