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authorGeorgi Djakov <gdjakov@mm-sol.com>2014-06-03 10:24:09 -0400
committerStephen Boyd <sboyd@codeaurora.org>2014-07-11 16:22:00 -0400
commit02824653200b31bd411f0def8006dc3d1c3ac4f4 (patch)
tree9a8582dd5d79cc41d201f5fce1adef81735c479f /drivers/clk/qcom
parent56097d8df0aefb507a4522728c922e9f568ccbaf (diff)
clk: qcom: Add APQ8084 Global Clock Controller support
This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r--drivers/clk/qcom/Kconfig8
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c2944
3 files changed, 2953 insertions, 0 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7f696b7d4422..e7516c2a2502 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -4,6 +4,14 @@ config COMMON_CLK_QCOM
4 select REGMAP_MMIO 4 select REGMAP_MMIO
5 select RESET_CONTROLLER 5 select RESET_CONTROLLER
6 6
7config APQ_GCC_8084
8 tristate "APQ8084 Global Clock Controller"
9 depends on COMMON_CLK_QCOM
10 help
11 Support for the global clock controller on apq8084 devices.
12 Say Y if you want to use peripheral devices such as UART, SPI,
13 i2c, USB, SD/eMMC, SATA, PCIe, etc.
14
7config MSM_GCC_8660 15config MSM_GCC_8660
8 tristate "MSM8660 Global Clock Controller" 16 tristate "MSM8660 Global Clock Controller"
9 depends on COMMON_CLK_QCOM 17 depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 689e05bf4f95..196a5df9125a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
8clk-qcom-y += clk-branch.o 8clk-qcom-y += clk-branch.o
9clk-qcom-y += reset.o 9clk-qcom-y += reset.o
10 10
11obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
11obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 12obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
12obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 13obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
13obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 14obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
new file mode 100644
index 000000000000..b9e6140674cc
--- /dev/null
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -0,0 +1,2944 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-apq8084.h>
26#include <dt-bindings/reset/qcom,gcc-apq8084.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35#define P_XO 0
36#define P_GPLL0 1
37#define P_GPLL1 1
38#define P_GPLL4 2
39
40static const u8 gcc_xo_gpll0_map[] = {
41 [P_XO] = 0,
42 [P_GPLL0] = 1,
43};
44
45static const char *gcc_xo_gpll0[] = {
46 "xo",
47 "gpll0_vote",
48};
49
50static const u8 gcc_xo_gpll0_gpll4_map[] = {
51 [P_XO] = 0,
52 [P_GPLL0] = 1,
53 [P_GPLL4] = 5,
54};
55
56static const char *gcc_xo_gpll0_gpll4[] = {
57 "xo",
58 "gpll0_vote",
59 "gpll4_vote",
60};
61
62#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
63
64static struct clk_pll gpll0 = {
65 .l_reg = 0x0004,
66 .m_reg = 0x0008,
67 .n_reg = 0x000c,
68 .config_reg = 0x0014,
69 .mode_reg = 0x0000,
70 .status_reg = 0x001c,
71 .status_bit = 17,
72 .clkr.hw.init = &(struct clk_init_data){
73 .name = "gpll0",
74 .parent_names = (const char *[]){ "xo" },
75 .num_parents = 1,
76 .ops = &clk_pll_ops,
77 },
78};
79
80static struct clk_regmap gpll0_vote = {
81 .enable_reg = 0x1480,
82 .enable_mask = BIT(0),
83 .hw.init = &(struct clk_init_data){
84 .name = "gpll0_vote",
85 .parent_names = (const char *[]){ "gpll0" },
86 .num_parents = 1,
87 .ops = &clk_pll_vote_ops,
88 },
89};
90
91static struct clk_rcg2 config_noc_clk_src = {
92 .cmd_rcgr = 0x0150,
93 .hid_width = 5,
94 .parent_map = gcc_xo_gpll0_map,
95 .clkr.hw.init = &(struct clk_init_data){
96 .name = "config_noc_clk_src",
97 .parent_names = gcc_xo_gpll0,
98 .num_parents = 2,
99 .ops = &clk_rcg2_ops,
100 },
101};
102
103static struct clk_rcg2 periph_noc_clk_src = {
104 .cmd_rcgr = 0x0190,
105 .hid_width = 5,
106 .parent_map = gcc_xo_gpll0_map,
107 .clkr.hw.init = &(struct clk_init_data){
108 .name = "periph_noc_clk_src",
109 .parent_names = gcc_xo_gpll0,
110 .num_parents = 2,
111 .ops = &clk_rcg2_ops,
112 },
113};
114
115static struct clk_rcg2 system_noc_clk_src = {
116 .cmd_rcgr = 0x0120,
117 .hid_width = 5,
118 .parent_map = gcc_xo_gpll0_map,
119 .clkr.hw.init = &(struct clk_init_data){
120 .name = "system_noc_clk_src",
121 .parent_names = gcc_xo_gpll0,
122 .num_parents = 2,
123 .ops = &clk_rcg2_ops,
124 },
125};
126
127static struct clk_pll gpll1 = {
128 .l_reg = 0x0044,
129 .m_reg = 0x0048,
130 .n_reg = 0x004c,
131 .config_reg = 0x0054,
132 .mode_reg = 0x0040,
133 .status_reg = 0x005c,
134 .status_bit = 17,
135 .clkr.hw.init = &(struct clk_init_data){
136 .name = "gpll1",
137 .parent_names = (const char *[]){ "xo" },
138 .num_parents = 1,
139 .ops = &clk_pll_ops,
140 },
141};
142
143static struct clk_regmap gpll1_vote = {
144 .enable_reg = 0x1480,
145 .enable_mask = BIT(1),
146 .hw.init = &(struct clk_init_data){
147 .name = "gpll1_vote",
148 .parent_names = (const char *[]){ "gpll1" },
149 .num_parents = 1,
150 .ops = &clk_pll_vote_ops,
151 },
152};
153
154static struct clk_pll gpll4 = {
155 .l_reg = 0x1dc4,
156 .m_reg = 0x1dc8,
157 .n_reg = 0x1dcc,
158 .config_reg = 0x1dd4,
159 .mode_reg = 0x1dc0,
160 .status_reg = 0x1ddc,
161 .status_bit = 17,
162 .clkr.hw.init = &(struct clk_init_data){
163 .name = "gpll4",
164 .parent_names = (const char *[]){ "xo" },
165 .num_parents = 1,
166 .ops = &clk_pll_ops,
167 },
168};
169
170static struct clk_regmap gpll4_vote = {
171 .enable_reg = 0x1480,
172 .enable_mask = BIT(4),
173 .hw.init = &(struct clk_init_data){
174 .name = "gpll4_vote",
175 .parent_names = (const char *[]){ "gpll4" },
176 .num_parents = 1,
177 .ops = &clk_pll_vote_ops,
178 },
179};
180
181static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
182 F(125000000, P_GPLL0, 1, 5, 24),
183 { }
184};
185
186static struct clk_rcg2 usb30_master_clk_src = {
187 .cmd_rcgr = 0x03d4,
188 .mnd_width = 8,
189 .hid_width = 5,
190 .parent_map = gcc_xo_gpll0_map,
191 .freq_tbl = ftbl_gcc_usb30_master_clk,
192 .clkr.hw.init = &(struct clk_init_data){
193 .name = "usb30_master_clk_src",
194 .parent_names = gcc_xo_gpll0,
195 .num_parents = 2,
196 .ops = &clk_rcg2_ops,
197 },
198};
199
200static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
201 F(125000000, P_GPLL0, 1, 5, 24),
202 { }
203};
204
205static struct clk_rcg2 usb30_sec_master_clk_src = {
206 .cmd_rcgr = 0x1bd4,
207 .mnd_width = 8,
208 .hid_width = 5,
209 .parent_map = gcc_xo_gpll0_map,
210 .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
211 .clkr.hw.init = &(struct clk_init_data){
212 .name = "usb30_sec_master_clk_src",
213 .parent_names = gcc_xo_gpll0,
214 .num_parents = 2,
215 .ops = &clk_rcg2_ops,
216 },
217};
218
219static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
220 .halt_reg = 0x1bd0,
221 .clkr = {
222 .enable_reg = 0x1bd0,
223 .enable_mask = BIT(0),
224 .hw.init = &(struct clk_init_data){
225 .name = "gcc_usb30_sec_mock_utmi_clk",
226 .parent_names = (const char *[]){
227 "usb30_sec_mock_utmi_clk_src",
228 },
229 .num_parents = 1,
230 .flags = CLK_SET_RATE_PARENT,
231 .ops = &clk_branch2_ops,
232 },
233 },
234};
235
236static struct clk_branch gcc_usb30_sec_sleep_clk = {
237 .halt_reg = 0x1bcc,
238 .clkr = {
239 .enable_reg = 0x1bcc,
240 .enable_mask = BIT(0),
241 .hw.init = &(struct clk_init_data){
242 .name = "gcc_usb30_sec_sleep_clk",
243 .parent_names = (const char *[]){
244 "sleep_clk_src",
245 },
246 .num_parents = 1,
247 .flags = CLK_SET_RATE_PARENT,
248 .ops = &clk_branch2_ops,
249 },
250 },
251};
252
253static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
254 F(19200000, P_XO, 1, 0, 0),
255 F(50000000, P_GPLL0, 12, 0, 0),
256 { }
257};
258
259static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
260 .cmd_rcgr = 0x0660,
261 .hid_width = 5,
262 .parent_map = gcc_xo_gpll0_map,
263 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
264 .clkr.hw.init = &(struct clk_init_data){
265 .name = "blsp1_qup1_i2c_apps_clk_src",
266 .parent_names = gcc_xo_gpll0,
267 .num_parents = 2,
268 .ops = &clk_rcg2_ops,
269 },
270};
271
272static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
273 F(960000, P_XO, 10, 1, 2),
274 F(4800000, P_XO, 4, 0, 0),
275 F(9600000, P_XO, 2, 0, 0),
276 F(15000000, P_GPLL0, 10, 1, 4),
277 F(19200000, P_XO, 1, 0, 0),
278 F(25000000, P_GPLL0, 12, 1, 2),
279 F(50000000, P_GPLL0, 12, 0, 0),
280 { }
281};
282
283static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
284 .cmd_rcgr = 0x064c,
285 .mnd_width = 8,
286 .hid_width = 5,
287 .parent_map = gcc_xo_gpll0_map,
288 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "blsp1_qup1_spi_apps_clk_src",
291 .parent_names = gcc_xo_gpll0,
292 .num_parents = 2,
293 .ops = &clk_rcg2_ops,
294 },
295};
296
297static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
298 .cmd_rcgr = 0x06e0,
299 .hid_width = 5,
300 .parent_map = gcc_xo_gpll0_map,
301 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
302 .clkr.hw.init = &(struct clk_init_data){
303 .name = "blsp1_qup2_i2c_apps_clk_src",
304 .parent_names = gcc_xo_gpll0,
305 .num_parents = 2,
306 .ops = &clk_rcg2_ops,
307 },
308};
309
310static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
311 .cmd_rcgr = 0x06cc,
312 .mnd_width = 8,
313 .hid_width = 5,
314 .parent_map = gcc_xo_gpll0_map,
315 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "blsp1_qup2_spi_apps_clk_src",
318 .parent_names = gcc_xo_gpll0,
319 .num_parents = 2,
320 .ops = &clk_rcg2_ops,
321 },
322};
323
324static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
325 .cmd_rcgr = 0x0760,
326 .hid_width = 5,
327 .parent_map = gcc_xo_gpll0_map,
328 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "blsp1_qup3_i2c_apps_clk_src",
331 .parent_names = gcc_xo_gpll0,
332 .num_parents = 2,
333 .ops = &clk_rcg2_ops,
334 },
335};
336
337static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
338 .cmd_rcgr = 0x074c,
339 .mnd_width = 8,
340 .hid_width = 5,
341 .parent_map = gcc_xo_gpll0_map,
342 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "blsp1_qup3_spi_apps_clk_src",
345 .parent_names = gcc_xo_gpll0,
346 .num_parents = 2,
347 .ops = &clk_rcg2_ops,
348 },
349};
350
351static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
352 .cmd_rcgr = 0x07e0,
353 .hid_width = 5,
354 .parent_map = gcc_xo_gpll0_map,
355 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "blsp1_qup4_i2c_apps_clk_src",
358 .parent_names = gcc_xo_gpll0,
359 .num_parents = 2,
360 .ops = &clk_rcg2_ops,
361 },
362};
363
364static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
365 .cmd_rcgr = 0x07cc,
366 .mnd_width = 8,
367 .hid_width = 5,
368 .parent_map = gcc_xo_gpll0_map,
369 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "blsp1_qup4_spi_apps_clk_src",
372 .parent_names = gcc_xo_gpll0,
373 .num_parents = 2,
374 .ops = &clk_rcg2_ops,
375 },
376};
377
378static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
379 .cmd_rcgr = 0x0860,
380 .hid_width = 5,
381 .parent_map = gcc_xo_gpll0_map,
382 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
383 .clkr.hw.init = &(struct clk_init_data){
384 .name = "blsp1_qup5_i2c_apps_clk_src",
385 .parent_names = gcc_xo_gpll0,
386 .num_parents = 2,
387 .ops = &clk_rcg2_ops,
388 },
389};
390
391static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
392 .cmd_rcgr = 0x084c,
393 .mnd_width = 8,
394 .hid_width = 5,
395 .parent_map = gcc_xo_gpll0_map,
396 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
397 .clkr.hw.init = &(struct clk_init_data){
398 .name = "blsp1_qup5_spi_apps_clk_src",
399 .parent_names = gcc_xo_gpll0,
400 .num_parents = 2,
401 .ops = &clk_rcg2_ops,
402 },
403};
404
405static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
406 .cmd_rcgr = 0x08e0,
407 .hid_width = 5,
408 .parent_map = gcc_xo_gpll0_map,
409 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
410 .clkr.hw.init = &(struct clk_init_data){
411 .name = "blsp1_qup6_i2c_apps_clk_src",
412 .parent_names = gcc_xo_gpll0,
413 .num_parents = 2,
414 .ops = &clk_rcg2_ops,
415 },
416};
417
418static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
419 .cmd_rcgr = 0x08cc,
420 .mnd_width = 8,
421 .hid_width = 5,
422 .parent_map = gcc_xo_gpll0_map,
423 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "blsp1_qup6_spi_apps_clk_src",
426 .parent_names = gcc_xo_gpll0,
427 .num_parents = 2,
428 .ops = &clk_rcg2_ops,
429 },
430};
431
432static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
433 F(3686400, P_GPLL0, 1, 96, 15625),
434 F(7372800, P_GPLL0, 1, 192, 15625),
435 F(14745600, P_GPLL0, 1, 384, 15625),
436 F(16000000, P_GPLL0, 5, 2, 15),
437 F(19200000, P_XO, 1, 0, 0),
438 F(24000000, P_GPLL0, 5, 1, 5),
439 F(32000000, P_GPLL0, 1, 4, 75),
440 F(40000000, P_GPLL0, 15, 0, 0),
441 F(46400000, P_GPLL0, 1, 29, 375),
442 F(48000000, P_GPLL0, 12.5, 0, 0),
443 F(51200000, P_GPLL0, 1, 32, 375),
444 F(56000000, P_GPLL0, 1, 7, 75),
445 F(58982400, P_GPLL0, 1, 1536, 15625),
446 F(60000000, P_GPLL0, 10, 0, 0),
447 F(63160000, P_GPLL0, 9.5, 0, 0),
448 { }
449};
450
451static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
452 .cmd_rcgr = 0x068c,
453 .mnd_width = 16,
454 .hid_width = 5,
455 .parent_map = gcc_xo_gpll0_map,
456 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
457 .clkr.hw.init = &(struct clk_init_data){
458 .name = "blsp1_uart1_apps_clk_src",
459 .parent_names = gcc_xo_gpll0,
460 .num_parents = 2,
461 .ops = &clk_rcg2_ops,
462 },
463};
464
465static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
466 .cmd_rcgr = 0x070c,
467 .mnd_width = 16,
468 .hid_width = 5,
469 .parent_map = gcc_xo_gpll0_map,
470 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
471 .clkr.hw.init = &(struct clk_init_data){
472 .name = "blsp1_uart2_apps_clk_src",
473 .parent_names = gcc_xo_gpll0,
474 .num_parents = 2,
475 .ops = &clk_rcg2_ops,
476 },
477};
478
479static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
480 .cmd_rcgr = 0x078c,
481 .mnd_width = 16,
482 .hid_width = 5,
483 .parent_map = gcc_xo_gpll0_map,
484 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
485 .clkr.hw.init = &(struct clk_init_data){
486 .name = "blsp1_uart3_apps_clk_src",
487 .parent_names = gcc_xo_gpll0,
488 .num_parents = 2,
489 .ops = &clk_rcg2_ops,
490 },
491};
492
493static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
494 .cmd_rcgr = 0x080c,
495 .mnd_width = 16,
496 .hid_width = 5,
497 .parent_map = gcc_xo_gpll0_map,
498 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
499 .clkr.hw.init = &(struct clk_init_data){
500 .name = "blsp1_uart4_apps_clk_src",
501 .parent_names = gcc_xo_gpll0,
502 .num_parents = 2,
503 .ops = &clk_rcg2_ops,
504 },
505};
506
507static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
508 .cmd_rcgr = 0x088c,
509 .mnd_width = 16,
510 .hid_width = 5,
511 .parent_map = gcc_xo_gpll0_map,
512 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
513 .clkr.hw.init = &(struct clk_init_data){
514 .name = "blsp1_uart5_apps_clk_src",
515 .parent_names = gcc_xo_gpll0,
516 .num_parents = 2,
517 .ops = &clk_rcg2_ops,
518 },
519};
520
521static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
522 .cmd_rcgr = 0x090c,
523 .mnd_width = 16,
524 .hid_width = 5,
525 .parent_map = gcc_xo_gpll0_map,
526 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
527 .clkr.hw.init = &(struct clk_init_data){
528 .name = "blsp1_uart6_apps_clk_src",
529 .parent_names = gcc_xo_gpll0,
530 .num_parents = 2,
531 .ops = &clk_rcg2_ops,
532 },
533};
534
535static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
536 .cmd_rcgr = 0x09a0,
537 .hid_width = 5,
538 .parent_map = gcc_xo_gpll0_map,
539 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
540 .clkr.hw.init = &(struct clk_init_data){
541 .name = "blsp2_qup1_i2c_apps_clk_src",
542 .parent_names = gcc_xo_gpll0,
543 .num_parents = 2,
544 .ops = &clk_rcg2_ops,
545 },
546};
547
548static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
549 .cmd_rcgr = 0x098c,
550 .mnd_width = 8,
551 .hid_width = 5,
552 .parent_map = gcc_xo_gpll0_map,
553 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
554 .clkr.hw.init = &(struct clk_init_data){
555 .name = "blsp2_qup1_spi_apps_clk_src",
556 .parent_names = gcc_xo_gpll0,
557 .num_parents = 2,
558 .ops = &clk_rcg2_ops,
559 },
560};
561
562static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
563 .cmd_rcgr = 0x0a20,
564 .hid_width = 5,
565 .parent_map = gcc_xo_gpll0_map,
566 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "blsp2_qup2_i2c_apps_clk_src",
569 .parent_names = gcc_xo_gpll0,
570 .num_parents = 2,
571 .ops = &clk_rcg2_ops,
572 },
573};
574
575static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
576 .cmd_rcgr = 0x0a0c,
577 .mnd_width = 8,
578 .hid_width = 5,
579 .parent_map = gcc_xo_gpll0_map,
580 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
581 .clkr.hw.init = &(struct clk_init_data){
582 .name = "blsp2_qup2_spi_apps_clk_src",
583 .parent_names = gcc_xo_gpll0,
584 .num_parents = 2,
585 .ops = &clk_rcg2_ops,
586 },
587};
588
589static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
590 .cmd_rcgr = 0x0aa0,
591 .hid_width = 5,
592 .parent_map = gcc_xo_gpll0_map,
593 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "blsp2_qup3_i2c_apps_clk_src",
596 .parent_names = gcc_xo_gpll0,
597 .num_parents = 2,
598 .ops = &clk_rcg2_ops,
599 },
600};
601
602static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
603 .cmd_rcgr = 0x0a8c,
604 .mnd_width = 8,
605 .hid_width = 5,
606 .parent_map = gcc_xo_gpll0_map,
607 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
608 .clkr.hw.init = &(struct clk_init_data){
609 .name = "blsp2_qup3_spi_apps_clk_src",
610 .parent_names = gcc_xo_gpll0,
611 .num_parents = 2,
612 .ops = &clk_rcg2_ops,
613 },
614};
615
616static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
617 .cmd_rcgr = 0x0b20,
618 .hid_width = 5,
619 .parent_map = gcc_xo_gpll0_map,
620 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "blsp2_qup4_i2c_apps_clk_src",
623 .parent_names = gcc_xo_gpll0,
624 .num_parents = 2,
625 .ops = &clk_rcg2_ops,
626 },
627};
628
629static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
630 .cmd_rcgr = 0x0b0c,
631 .mnd_width = 8,
632 .hid_width = 5,
633 .parent_map = gcc_xo_gpll0_map,
634 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
635 .clkr.hw.init = &(struct clk_init_data){
636 .name = "blsp2_qup4_spi_apps_clk_src",
637 .parent_names = gcc_xo_gpll0,
638 .num_parents = 2,
639 .ops = &clk_rcg2_ops,
640 },
641};
642
643static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
644 .cmd_rcgr = 0x0ba0,
645 .hid_width = 5,
646 .parent_map = gcc_xo_gpll0_map,
647 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "blsp2_qup5_i2c_apps_clk_src",
650 .parent_names = gcc_xo_gpll0,
651 .num_parents = 2,
652 .ops = &clk_rcg2_ops,
653 },
654};
655
656static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
657 .cmd_rcgr = 0x0b8c,
658 .mnd_width = 8,
659 .hid_width = 5,
660 .parent_map = gcc_xo_gpll0_map,
661 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
662 .clkr.hw.init = &(struct clk_init_data){
663 .name = "blsp2_qup5_spi_apps_clk_src",
664 .parent_names = gcc_xo_gpll0,
665 .num_parents = 2,
666 .ops = &clk_rcg2_ops,
667 },
668};
669
670static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
671 .cmd_rcgr = 0x0c20,
672 .hid_width = 5,
673 .parent_map = gcc_xo_gpll0_map,
674 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
675 .clkr.hw.init = &(struct clk_init_data){
676 .name = "blsp2_qup6_i2c_apps_clk_src",
677 .parent_names = gcc_xo_gpll0,
678 .num_parents = 2,
679 .ops = &clk_rcg2_ops,
680 },
681};
682
683static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
684 .cmd_rcgr = 0x0c0c,
685 .mnd_width = 8,
686 .hid_width = 5,
687 .parent_map = gcc_xo_gpll0_map,
688 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "blsp2_qup6_spi_apps_clk_src",
691 .parent_names = gcc_xo_gpll0,
692 .num_parents = 2,
693 .ops = &clk_rcg2_ops,
694 },
695};
696
697static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
698 .cmd_rcgr = 0x09cc,
699 .mnd_width = 16,
700 .hid_width = 5,
701 .parent_map = gcc_xo_gpll0_map,
702 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
703 .clkr.hw.init = &(struct clk_init_data){
704 .name = "blsp2_uart1_apps_clk_src",
705 .parent_names = gcc_xo_gpll0,
706 .num_parents = 2,
707 .ops = &clk_rcg2_ops,
708 },
709};
710
711static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
712 .cmd_rcgr = 0x0a4c,
713 .mnd_width = 16,
714 .hid_width = 5,
715 .parent_map = gcc_xo_gpll0_map,
716 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
717 .clkr.hw.init = &(struct clk_init_data){
718 .name = "blsp2_uart2_apps_clk_src",
719 .parent_names = gcc_xo_gpll0,
720 .num_parents = 2,
721 .ops = &clk_rcg2_ops,
722 },
723};
724
725static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
726 .cmd_rcgr = 0x0acc,
727 .mnd_width = 16,
728 .hid_width = 5,
729 .parent_map = gcc_xo_gpll0_map,
730 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
731 .clkr.hw.init = &(struct clk_init_data){
732 .name = "blsp2_uart3_apps_clk_src",
733 .parent_names = gcc_xo_gpll0,
734 .num_parents = 2,
735 .ops = &clk_rcg2_ops,
736 },
737};
738
739static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
740 .cmd_rcgr = 0x0b4c,
741 .mnd_width = 16,
742 .hid_width = 5,
743 .parent_map = gcc_xo_gpll0_map,
744 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "blsp2_uart4_apps_clk_src",
747 .parent_names = gcc_xo_gpll0,
748 .num_parents = 2,
749 .ops = &clk_rcg2_ops,
750 },
751};
752
753static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
754 .cmd_rcgr = 0x0bcc,
755 .mnd_width = 16,
756 .hid_width = 5,
757 .parent_map = gcc_xo_gpll0_map,
758 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
759 .clkr.hw.init = &(struct clk_init_data){
760 .name = "blsp2_uart5_apps_clk_src",
761 .parent_names = gcc_xo_gpll0,
762 .num_parents = 2,
763 .ops = &clk_rcg2_ops,
764 },
765};
766
767static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
768 .cmd_rcgr = 0x0c4c,
769 .mnd_width = 16,
770 .hid_width = 5,
771 .parent_map = gcc_xo_gpll0_map,
772 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
773 .clkr.hw.init = &(struct clk_init_data){
774 .name = "blsp2_uart6_apps_clk_src",
775 .parent_names = gcc_xo_gpll0,
776 .num_parents = 2,
777 .ops = &clk_rcg2_ops,
778 },
779};
780
781static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
782 F(50000000, P_GPLL0, 12, 0, 0),
783 F(85710000, P_GPLL0, 7, 0, 0),
784 F(100000000, P_GPLL0, 6, 0, 0),
785 F(171430000, P_GPLL0, 3.5, 0, 0),
786 { }
787};
788
789static struct clk_rcg2 ce1_clk_src = {
790 .cmd_rcgr = 0x1050,
791 .hid_width = 5,
792 .parent_map = gcc_xo_gpll0_map,
793 .freq_tbl = ftbl_gcc_ce1_clk,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "ce1_clk_src",
796 .parent_names = gcc_xo_gpll0,
797 .num_parents = 2,
798 .ops = &clk_rcg2_ops,
799 },
800};
801
802static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
803 F(50000000, P_GPLL0, 12, 0, 0),
804 F(85710000, P_GPLL0, 7, 0, 0),
805 F(100000000, P_GPLL0, 6, 0, 0),
806 F(171430000, P_GPLL0, 3.5, 0, 0),
807 { }
808};
809
810static struct clk_rcg2 ce2_clk_src = {
811 .cmd_rcgr = 0x1090,
812 .hid_width = 5,
813 .parent_map = gcc_xo_gpll0_map,
814 .freq_tbl = ftbl_gcc_ce2_clk,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "ce2_clk_src",
817 .parent_names = gcc_xo_gpll0,
818 .num_parents = 2,
819 .ops = &clk_rcg2_ops,
820 },
821};
822
823static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
824 F(50000000, P_GPLL0, 12, 0, 0),
825 F(85710000, P_GPLL0, 7, 0, 0),
826 F(100000000, P_GPLL0, 6, 0, 0),
827 F(171430000, P_GPLL0, 3.5, 0, 0),
828 { }
829};
830
831static struct clk_rcg2 ce3_clk_src = {
832 .cmd_rcgr = 0x1d10,
833 .hid_width = 5,
834 .parent_map = gcc_xo_gpll0_map,
835 .freq_tbl = ftbl_gcc_ce3_clk,
836 .clkr.hw.init = &(struct clk_init_data){
837 .name = "ce3_clk_src",
838 .parent_names = gcc_xo_gpll0,
839 .num_parents = 2,
840 .ops = &clk_rcg2_ops,
841 },
842};
843
844static const struct freq_tbl ftbl_gcc_gp_clk[] = {
845 F(19200000, P_XO, 1, 0, 0),
846 F(100000000, P_GPLL0, 6, 0, 0),
847 F(200000000, P_GPLL0, 3, 0, 0),
848 { }
849};
850
851static struct clk_rcg2 gp1_clk_src = {
852 .cmd_rcgr = 0x1904,
853 .mnd_width = 8,
854 .hid_width = 5,
855 .parent_map = gcc_xo_gpll0_map,
856 .freq_tbl = ftbl_gcc_gp_clk,
857 .clkr.hw.init = &(struct clk_init_data){
858 .name = "gp1_clk_src",
859 .parent_names = gcc_xo_gpll0,
860 .num_parents = 2,
861 .ops = &clk_rcg2_ops,
862 },
863};
864
865static struct clk_rcg2 gp2_clk_src = {
866 .cmd_rcgr = 0x1944,
867 .mnd_width = 8,
868 .hid_width = 5,
869 .parent_map = gcc_xo_gpll0_map,
870 .freq_tbl = ftbl_gcc_gp_clk,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "gp2_clk_src",
873 .parent_names = gcc_xo_gpll0,
874 .num_parents = 2,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static struct clk_rcg2 gp3_clk_src = {
880 .cmd_rcgr = 0x1984,
881 .mnd_width = 8,
882 .hid_width = 5,
883 .parent_map = gcc_xo_gpll0_map,
884 .freq_tbl = ftbl_gcc_gp_clk,
885 .clkr.hw.init = &(struct clk_init_data){
886 .name = "gp3_clk_src",
887 .parent_names = gcc_xo_gpll0,
888 .num_parents = 2,
889 .ops = &clk_rcg2_ops,
890 },
891};
892
893static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
894 F(60000000, P_GPLL0, 10, 0, 0),
895 { }
896};
897
898static struct clk_rcg2 pdm2_clk_src = {
899 .cmd_rcgr = 0x0cd0,
900 .hid_width = 5,
901 .parent_map = gcc_xo_gpll0_map,
902 .freq_tbl = ftbl_gcc_pdm2_clk,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "pdm2_clk_src",
905 .parent_names = gcc_xo_gpll0,
906 .num_parents = 2,
907 .ops = &clk_rcg2_ops,
908 },
909};
910
911static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
912 F(144000, P_XO, 16, 3, 25),
913 F(400000, P_XO, 12, 1, 4),
914 F(20000000, P_GPLL0, 15, 1, 2),
915 F(25000000, P_GPLL0, 12, 1, 2),
916 F(50000000, P_GPLL0, 12, 0, 0),
917 F(100000000, P_GPLL0, 6, 0, 0),
918 F(192000000, P_GPLL4, 4, 0, 0),
919 F(200000000, P_GPLL0, 3, 0, 0),
920 F(384000000, P_GPLL4, 2, 0, 0),
921 { }
922};
923
924static struct clk_rcg2 sdcc1_apps_clk_src = {
925 .cmd_rcgr = 0x04d0,
926 .mnd_width = 8,
927 .hid_width = 5,
928 .parent_map = gcc_xo_gpll0_gpll4_map,
929 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
930 .clkr.hw.init = &(struct clk_init_data){
931 .name = "sdcc1_apps_clk_src",
932 .parent_names = gcc_xo_gpll0_gpll4,
933 .num_parents = 3,
934 .ops = &clk_rcg2_ops,
935 },
936};
937
938static struct clk_rcg2 sdcc2_apps_clk_src = {
939 .cmd_rcgr = 0x0510,
940 .mnd_width = 8,
941 .hid_width = 5,
942 .parent_map = gcc_xo_gpll0_map,
943 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
944 .clkr.hw.init = &(struct clk_init_data){
945 .name = "sdcc2_apps_clk_src",
946 .parent_names = gcc_xo_gpll0,
947 .num_parents = 2,
948 .ops = &clk_rcg2_ops,
949 },
950};
951
952static struct clk_rcg2 sdcc3_apps_clk_src = {
953 .cmd_rcgr = 0x0550,
954 .mnd_width = 8,
955 .hid_width = 5,
956 .parent_map = gcc_xo_gpll0_map,
957 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "sdcc3_apps_clk_src",
960 .parent_names = gcc_xo_gpll0,
961 .num_parents = 2,
962 .ops = &clk_rcg2_ops,
963 },
964};
965
966static struct clk_rcg2 sdcc4_apps_clk_src = {
967 .cmd_rcgr = 0x0590,
968 .mnd_width = 8,
969 .hid_width = 5,
970 .parent_map = gcc_xo_gpll0_map,
971 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
972 .clkr.hw.init = &(struct clk_init_data){
973 .name = "sdcc4_apps_clk_src",
974 .parent_names = gcc_xo_gpll0,
975 .num_parents = 2,
976 .ops = &clk_rcg2_ops,
977 },
978};
979
980static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
981 F(105000, P_XO, 2, 1, 91),
982 { }
983};
984
985static struct clk_rcg2 tsif_ref_clk_src = {
986 .cmd_rcgr = 0x0d90,
987 .mnd_width = 8,
988 .hid_width = 5,
989 .parent_map = gcc_xo_gpll0_map,
990 .freq_tbl = ftbl_gcc_tsif_ref_clk,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "tsif_ref_clk_src",
993 .parent_names = gcc_xo_gpll0,
994 .num_parents = 2,
995 .ops = &clk_rcg2_ops,
996 },
997};
998
999static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1000 F(60000000, P_GPLL0, 10, 0, 0),
1001 { }
1002};
1003
1004static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1005 .cmd_rcgr = 0x03e8,
1006 .hid_width = 5,
1007 .parent_map = gcc_xo_gpll0_map,
1008 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1009 .clkr.hw.init = &(struct clk_init_data){
1010 .name = "usb30_mock_utmi_clk_src",
1011 .parent_names = gcc_xo_gpll0,
1012 .num_parents = 2,
1013 .ops = &clk_rcg2_ops,
1014 },
1015};
1016
1017static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1018 F(125000000, P_GPLL0, 1, 5, 24),
1019 { }
1020};
1021
1022static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1023 .cmd_rcgr = 0x1be8,
1024 .hid_width = 5,
1025 .parent_map = gcc_xo_gpll0_map,
1026 .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1027 .clkr.hw.init = &(struct clk_init_data){
1028 .name = "usb30_sec_mock_utmi_clk_src",
1029 .parent_names = gcc_xo_gpll0,
1030 .num_parents = 2,
1031 .ops = &clk_rcg2_ops,
1032 },
1033};
1034
1035static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1036 F(75000000, P_GPLL0, 8, 0, 0),
1037 { }
1038};
1039
1040static struct clk_rcg2 usb_hs_system_clk_src = {
1041 .cmd_rcgr = 0x0490,
1042 .hid_width = 5,
1043 .parent_map = gcc_xo_gpll0_map,
1044 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1045 .clkr.hw.init = &(struct clk_init_data){
1046 .name = "usb_hs_system_clk_src",
1047 .parent_names = gcc_xo_gpll0,
1048 .num_parents = 2,
1049 .ops = &clk_rcg2_ops,
1050 },
1051};
1052
1053static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1054 F(480000000, P_GPLL1, 1, 0, 0),
1055 { }
1056};
1057
1058static u8 usb_hsic_clk_src_map[] = {
1059 [P_XO] = 0,
1060 [P_GPLL1] = 4,
1061};
1062
1063static struct clk_rcg2 usb_hsic_clk_src = {
1064 .cmd_rcgr = 0x0440,
1065 .hid_width = 5,
1066 .parent_map = usb_hsic_clk_src_map,
1067 .freq_tbl = ftbl_gcc_usb_hsic_clk,
1068 .clkr.hw.init = &(struct clk_init_data){
1069 .name = "usb_hsic_clk_src",
1070 .parent_names = (const char *[]){
1071 "xo",
1072 "gpll1_vote",
1073 },
1074 .num_parents = 2,
1075 .ops = &clk_rcg2_ops,
1076 },
1077};
1078
1079static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1080 F(60000000, P_GPLL1, 8, 0, 0),
1081 { }
1082};
1083
1084static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1085 .cmd_rcgr = 0x046c,
1086 .mnd_width = 8,
1087 .hid_width = 5,
1088 .parent_map = usb_hsic_clk_src_map,
1089 .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1090 .clkr.hw.init = &(struct clk_init_data){
1091 .name = "usb_hsic_ahb_clk_src",
1092 .parent_names = (const char *[]){
1093 "xo",
1094 "gpll1_vote",
1095 },
1096 .num_parents = 2,
1097 .ops = &clk_rcg2_ops,
1098 },
1099};
1100
1101static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1102 F(9600000, P_XO, 2, 0, 0),
1103 { }
1104};
1105
1106static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1107 .cmd_rcgr = 0x0458,
1108 .hid_width = 5,
1109 .parent_map = gcc_xo_gpll0_map,
1110 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1111 .clkr.hw.init = &(struct clk_init_data){
1112 .name = "usb_hsic_io_cal_clk_src",
1113 .parent_names = gcc_xo_gpll0,
1114 .num_parents = 1,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1120 .halt_reg = 0x1f14,
1121 .clkr = {
1122 .enable_reg = 0x1f14,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(struct clk_init_data){
1125 .name = "gcc_usb_hsic_mock_utmi_clk",
1126 .parent_names = (const char *[]){
1127 "usb_hsic_mock_utmi_clk_src",
1128 },
1129 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_ops,
1132 },
1133 },
1134};
1135
1136static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1137 F(60000000, P_GPLL0, 10, 0, 0),
1138 { }
1139};
1140
1141static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1142 .cmd_rcgr = 0x1f00,
1143 .hid_width = 5,
1144 .parent_map = gcc_xo_gpll0_map,
1145 .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1146 .clkr.hw.init = &(struct clk_init_data){
1147 .name = "usb_hsic_mock_utmi_clk_src",
1148 .parent_names = gcc_xo_gpll0,
1149 .num_parents = 1,
1150 .ops = &clk_rcg2_ops,
1151 },
1152};
1153
1154static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1155 F(75000000, P_GPLL0, 8, 0, 0),
1156 { }
1157};
1158
1159static struct clk_rcg2 usb_hsic_system_clk_src = {
1160 .cmd_rcgr = 0x041c,
1161 .hid_width = 5,
1162 .parent_map = gcc_xo_gpll0_map,
1163 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1164 .clkr.hw.init = &(struct clk_init_data){
1165 .name = "usb_hsic_system_clk_src",
1166 .parent_names = gcc_xo_gpll0,
1167 .num_parents = 2,
1168 .ops = &clk_rcg2_ops,
1169 },
1170};
1171
1172static struct clk_branch gcc_bam_dma_ahb_clk = {
1173 .halt_reg = 0x0d44,
1174 .halt_check = BRANCH_HALT_VOTED,
1175 .clkr = {
1176 .enable_reg = 0x1484,
1177 .enable_mask = BIT(12),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gcc_bam_dma_ahb_clk",
1180 .parent_names = (const char *[]){
1181 "periph_noc_clk_src",
1182 },
1183 .num_parents = 1,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_blsp1_ahb_clk = {
1190 .halt_reg = 0x05c4,
1191 .halt_check = BRANCH_HALT_VOTED,
1192 .clkr = {
1193 .enable_reg = 0x1484,
1194 .enable_mask = BIT(17),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "gcc_blsp1_ahb_clk",
1197 .parent_names = (const char *[]){
1198 "periph_noc_clk_src",
1199 },
1200 .num_parents = 1,
1201 .ops = &clk_branch2_ops,
1202 },
1203 },
1204};
1205
1206static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1207 .halt_reg = 0x0648,
1208 .clkr = {
1209 .enable_reg = 0x0648,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1213 .parent_names = (const char *[]){
1214 "blsp1_qup1_i2c_apps_clk_src",
1215 },
1216 .num_parents = 1,
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1219 },
1220 },
1221};
1222
1223static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1224 .halt_reg = 0x0644,
1225 .clkr = {
1226 .enable_reg = 0x0644,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gcc_blsp1_qup1_spi_apps_clk",
1230 .parent_names = (const char *[]){
1231 "blsp1_qup1_spi_apps_clk_src",
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238};
1239
1240static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1241 .halt_reg = 0x06c8,
1242 .clkr = {
1243 .enable_reg = 0x06c8,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1247 .parent_names = (const char *[]){
1248 "blsp1_qup2_i2c_apps_clk_src",
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1258 .halt_reg = 0x06c4,
1259 .clkr = {
1260 .enable_reg = 0x06c4,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_blsp1_qup2_spi_apps_clk",
1264 .parent_names = (const char *[]){
1265 "blsp1_qup2_spi_apps_clk_src",
1266 },
1267 .num_parents = 1,
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1270 },
1271 },
1272};
1273
1274static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1275 .halt_reg = 0x0748,
1276 .clkr = {
1277 .enable_reg = 0x0748,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1281 .parent_names = (const char *[]){
1282 "blsp1_qup3_i2c_apps_clk_src",
1283 },
1284 .num_parents = 1,
1285 .flags = CLK_SET_RATE_PARENT,
1286 .ops = &clk_branch2_ops,
1287 },
1288 },
1289};
1290
1291static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1292 .halt_reg = 0x0744,
1293 .clkr = {
1294 .enable_reg = 0x0744,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_blsp1_qup3_spi_apps_clk",
1298 .parent_names = (const char *[]){
1299 "blsp1_qup3_spi_apps_clk_src",
1300 },
1301 .num_parents = 1,
1302 .flags = CLK_SET_RATE_PARENT,
1303 .ops = &clk_branch2_ops,
1304 },
1305 },
1306};
1307
1308static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1309 .halt_reg = 0x07c8,
1310 .clkr = {
1311 .enable_reg = 0x07c8,
1312 .enable_mask = BIT(0),
1313 .hw.init = &(struct clk_init_data){
1314 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1315 .parent_names = (const char *[]){
1316 "blsp1_qup4_i2c_apps_clk_src",
1317 },
1318 .num_parents = 1,
1319 .flags = CLK_SET_RATE_PARENT,
1320 .ops = &clk_branch2_ops,
1321 },
1322 },
1323};
1324
1325static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1326 .halt_reg = 0x07c4,
1327 .clkr = {
1328 .enable_reg = 0x07c4,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "gcc_blsp1_qup4_spi_apps_clk",
1332 .parent_names = (const char *[]){
1333 "blsp1_qup4_spi_apps_clk_src",
1334 },
1335 .num_parents = 1,
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1338 },
1339 },
1340};
1341
1342static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1343 .halt_reg = 0x0848,
1344 .clkr = {
1345 .enable_reg = 0x0848,
1346 .enable_mask = BIT(0),
1347 .hw.init = &(struct clk_init_data){
1348 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1349 .parent_names = (const char *[]){
1350 "blsp1_qup5_i2c_apps_clk_src",
1351 },
1352 .num_parents = 1,
1353 .flags = CLK_SET_RATE_PARENT,
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357};
1358
1359static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1360 .halt_reg = 0x0844,
1361 .clkr = {
1362 .enable_reg = 0x0844,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_blsp1_qup5_spi_apps_clk",
1366 .parent_names = (const char *[]){
1367 "blsp1_qup5_spi_apps_clk_src",
1368 },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374};
1375
1376static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1377 .halt_reg = 0x08c8,
1378 .clkr = {
1379 .enable_reg = 0x08c8,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1383 .parent_names = (const char *[]){
1384 "blsp1_qup6_i2c_apps_clk_src",
1385 },
1386 .num_parents = 1,
1387 .flags = CLK_SET_RATE_PARENT,
1388 .ops = &clk_branch2_ops,
1389 },
1390 },
1391};
1392
1393static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1394 .halt_reg = 0x08c4,
1395 .clkr = {
1396 .enable_reg = 0x08c4,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_blsp1_qup6_spi_apps_clk",
1400 .parent_names = (const char *[]){
1401 "blsp1_qup6_spi_apps_clk_src",
1402 },
1403 .num_parents = 1,
1404 .flags = CLK_SET_RATE_PARENT,
1405 .ops = &clk_branch2_ops,
1406 },
1407 },
1408};
1409
1410static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1411 .halt_reg = 0x0684,
1412 .clkr = {
1413 .enable_reg = 0x0684,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data){
1416 .name = "gcc_blsp1_uart1_apps_clk",
1417 .parent_names = (const char *[]){
1418 "blsp1_uart1_apps_clk_src",
1419 },
1420 .num_parents = 1,
1421 .flags = CLK_SET_RATE_PARENT,
1422 .ops = &clk_branch2_ops,
1423 },
1424 },
1425};
1426
1427static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1428 .halt_reg = 0x0704,
1429 .clkr = {
1430 .enable_reg = 0x0704,
1431 .enable_mask = BIT(0),
1432 .hw.init = &(struct clk_init_data){
1433 .name = "gcc_blsp1_uart2_apps_clk",
1434 .parent_names = (const char *[]){
1435 "blsp1_uart2_apps_clk_src",
1436 },
1437 .num_parents = 1,
1438 .flags = CLK_SET_RATE_PARENT,
1439 .ops = &clk_branch2_ops,
1440 },
1441 },
1442};
1443
1444static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1445 .halt_reg = 0x0784,
1446 .clkr = {
1447 .enable_reg = 0x0784,
1448 .enable_mask = BIT(0),
1449 .hw.init = &(struct clk_init_data){
1450 .name = "gcc_blsp1_uart3_apps_clk",
1451 .parent_names = (const char *[]){
1452 "blsp1_uart3_apps_clk_src",
1453 },
1454 .num_parents = 1,
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1462 .halt_reg = 0x0804,
1463 .clkr = {
1464 .enable_reg = 0x0804,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "gcc_blsp1_uart4_apps_clk",
1468 .parent_names = (const char *[]){
1469 "blsp1_uart4_apps_clk_src",
1470 },
1471 .num_parents = 1,
1472 .flags = CLK_SET_RATE_PARENT,
1473 .ops = &clk_branch2_ops,
1474 },
1475 },
1476};
1477
1478static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1479 .halt_reg = 0x0884,
1480 .clkr = {
1481 .enable_reg = 0x0884,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(struct clk_init_data){
1484 .name = "gcc_blsp1_uart5_apps_clk",
1485 .parent_names = (const char *[]){
1486 "blsp1_uart5_apps_clk_src",
1487 },
1488 .num_parents = 1,
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1491 },
1492 },
1493};
1494
1495static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1496 .halt_reg = 0x0904,
1497 .clkr = {
1498 .enable_reg = 0x0904,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_blsp1_uart6_apps_clk",
1502 .parent_names = (const char *[]){
1503 "blsp1_uart6_apps_clk_src",
1504 },
1505 .num_parents = 1,
1506 .flags = CLK_SET_RATE_PARENT,
1507 .ops = &clk_branch2_ops,
1508 },
1509 },
1510};
1511
1512static struct clk_branch gcc_blsp2_ahb_clk = {
1513 .halt_reg = 0x0944,
1514 .halt_check = BRANCH_HALT_VOTED,
1515 .clkr = {
1516 .enable_reg = 0x1484,
1517 .enable_mask = BIT(15),
1518 .hw.init = &(struct clk_init_data){
1519 .name = "gcc_blsp2_ahb_clk",
1520 .parent_names = (const char *[]){
1521 "periph_noc_clk_src",
1522 },
1523 .num_parents = 1,
1524 .ops = &clk_branch2_ops,
1525 },
1526 },
1527};
1528
1529static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1530 .halt_reg = 0x0988,
1531 .clkr = {
1532 .enable_reg = 0x0988,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1536 .parent_names = (const char *[]){
1537 "blsp2_qup1_i2c_apps_clk_src",
1538 },
1539 .num_parents = 1,
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1542 },
1543 },
1544};
1545
1546static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1547 .halt_reg = 0x0984,
1548 .clkr = {
1549 .enable_reg = 0x0984,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(struct clk_init_data){
1552 .name = "gcc_blsp2_qup1_spi_apps_clk",
1553 .parent_names = (const char *[]){
1554 "blsp2_qup1_spi_apps_clk_src",
1555 },
1556 .num_parents = 1,
1557 .flags = CLK_SET_RATE_PARENT,
1558 .ops = &clk_branch2_ops,
1559 },
1560 },
1561};
1562
1563static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1564 .halt_reg = 0x0a08,
1565 .clkr = {
1566 .enable_reg = 0x0a08,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1570 .parent_names = (const char *[]){
1571 "blsp2_qup2_i2c_apps_clk_src",
1572 },
1573 .num_parents = 1,
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1576 },
1577 },
1578};
1579
1580static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1581 .halt_reg = 0x0a04,
1582 .clkr = {
1583 .enable_reg = 0x0a04,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "gcc_blsp2_qup2_spi_apps_clk",
1587 .parent_names = (const char *[]){
1588 "blsp2_qup2_spi_apps_clk_src",
1589 },
1590 .num_parents = 1,
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1593 },
1594 },
1595};
1596
1597static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1598 .halt_reg = 0x0a88,
1599 .clkr = {
1600 .enable_reg = 0x0a88,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1604 .parent_names = (const char *[]){
1605 "blsp2_qup3_i2c_apps_clk_src",
1606 },
1607 .num_parents = 1,
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1610 },
1611 },
1612};
1613
1614static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1615 .halt_reg = 0x0a84,
1616 .clkr = {
1617 .enable_reg = 0x0a84,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_blsp2_qup3_spi_apps_clk",
1621 .parent_names = (const char *[]){
1622 "blsp2_qup3_spi_apps_clk_src",
1623 },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1632 .halt_reg = 0x0b08,
1633 .clkr = {
1634 .enable_reg = 0x0b08,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1638 .parent_names = (const char *[]){
1639 "blsp2_qup4_i2c_apps_clk_src",
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646};
1647
1648static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1649 .halt_reg = 0x0b04,
1650 .clkr = {
1651 .enable_reg = 0x0b04,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "gcc_blsp2_qup4_spi_apps_clk",
1655 .parent_names = (const char *[]){
1656 "blsp2_qup4_spi_apps_clk_src",
1657 },
1658 .num_parents = 1,
1659 .flags = CLK_SET_RATE_PARENT,
1660 .ops = &clk_branch2_ops,
1661 },
1662 },
1663};
1664
1665static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1666 .halt_reg = 0x0b88,
1667 .clkr = {
1668 .enable_reg = 0x0b88,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1672 .parent_names = (const char *[]){
1673 "blsp2_qup5_i2c_apps_clk_src",
1674 },
1675 .num_parents = 1,
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680};
1681
1682static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1683 .halt_reg = 0x0b84,
1684 .clkr = {
1685 .enable_reg = 0x0b84,
1686 .enable_mask = BIT(0),
1687 .hw.init = &(struct clk_init_data){
1688 .name = "gcc_blsp2_qup5_spi_apps_clk",
1689 .parent_names = (const char *[]){
1690 "blsp2_qup5_spi_apps_clk_src",
1691 },
1692 .num_parents = 1,
1693 .flags = CLK_SET_RATE_PARENT,
1694 .ops = &clk_branch2_ops,
1695 },
1696 },
1697};
1698
1699static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1700 .halt_reg = 0x0c08,
1701 .clkr = {
1702 .enable_reg = 0x0c08,
1703 .enable_mask = BIT(0),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1706 .parent_names = (const char *[]){
1707 "blsp2_qup6_i2c_apps_clk_src",
1708 },
1709 .num_parents = 1,
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1717 .halt_reg = 0x0c04,
1718 .clkr = {
1719 .enable_reg = 0x0c04,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "gcc_blsp2_qup6_spi_apps_clk",
1723 .parent_names = (const char *[]){
1724 "blsp2_qup6_spi_apps_clk_src",
1725 },
1726 .num_parents = 1,
1727 .flags = CLK_SET_RATE_PARENT,
1728 .ops = &clk_branch2_ops,
1729 },
1730 },
1731};
1732
1733static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1734 .halt_reg = 0x09c4,
1735 .clkr = {
1736 .enable_reg = 0x09c4,
1737 .enable_mask = BIT(0),
1738 .hw.init = &(struct clk_init_data){
1739 .name = "gcc_blsp2_uart1_apps_clk",
1740 .parent_names = (const char *[]){
1741 "blsp2_uart1_apps_clk_src",
1742 },
1743 .num_parents = 1,
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_branch2_ops,
1746 },
1747 },
1748};
1749
1750static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1751 .halt_reg = 0x0a44,
1752 .clkr = {
1753 .enable_reg = 0x0a44,
1754 .enable_mask = BIT(0),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "gcc_blsp2_uart2_apps_clk",
1757 .parent_names = (const char *[]){
1758 "blsp2_uart2_apps_clk_src",
1759 },
1760 .num_parents = 1,
1761 .flags = CLK_SET_RATE_PARENT,
1762 .ops = &clk_branch2_ops,
1763 },
1764 },
1765};
1766
1767static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1768 .halt_reg = 0x0ac4,
1769 .clkr = {
1770 .enable_reg = 0x0ac4,
1771 .enable_mask = BIT(0),
1772 .hw.init = &(struct clk_init_data){
1773 .name = "gcc_blsp2_uart3_apps_clk",
1774 .parent_names = (const char *[]){
1775 "blsp2_uart3_apps_clk_src",
1776 },
1777 .num_parents = 1,
1778 .flags = CLK_SET_RATE_PARENT,
1779 .ops = &clk_branch2_ops,
1780 },
1781 },
1782};
1783
1784static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1785 .halt_reg = 0x0b44,
1786 .clkr = {
1787 .enable_reg = 0x0b44,
1788 .enable_mask = BIT(0),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "gcc_blsp2_uart4_apps_clk",
1791 .parent_names = (const char *[]){
1792 "blsp2_uart4_apps_clk_src",
1793 },
1794 .num_parents = 1,
1795 .flags = CLK_SET_RATE_PARENT,
1796 .ops = &clk_branch2_ops,
1797 },
1798 },
1799};
1800
1801static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1802 .halt_reg = 0x0bc4,
1803 .clkr = {
1804 .enable_reg = 0x0bc4,
1805 .enable_mask = BIT(0),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "gcc_blsp2_uart5_apps_clk",
1808 .parent_names = (const char *[]){
1809 "blsp2_uart5_apps_clk_src",
1810 },
1811 .num_parents = 1,
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1814 },
1815 },
1816};
1817
1818static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1819 .halt_reg = 0x0c44,
1820 .clkr = {
1821 .enable_reg = 0x0c44,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "gcc_blsp2_uart6_apps_clk",
1825 .parent_names = (const char *[]){
1826 "blsp2_uart6_apps_clk_src",
1827 },
1828 .num_parents = 1,
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833};
1834
1835static struct clk_branch gcc_boot_rom_ahb_clk = {
1836 .halt_reg = 0x0e04,
1837 .halt_check = BRANCH_HALT_VOTED,
1838 .clkr = {
1839 .enable_reg = 0x1484,
1840 .enable_mask = BIT(10),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_boot_rom_ahb_clk",
1843 .parent_names = (const char *[]){
1844 "config_noc_clk_src",
1845 },
1846 .num_parents = 1,
1847 .ops = &clk_branch2_ops,
1848 },
1849 },
1850};
1851
1852static struct clk_branch gcc_ce1_ahb_clk = {
1853 .halt_reg = 0x104c,
1854 .halt_check = BRANCH_HALT_VOTED,
1855 .clkr = {
1856 .enable_reg = 0x1484,
1857 .enable_mask = BIT(3),
1858 .hw.init = &(struct clk_init_data){
1859 .name = "gcc_ce1_ahb_clk",
1860 .parent_names = (const char *[]){
1861 "config_noc_clk_src",
1862 },
1863 .num_parents = 1,
1864 .ops = &clk_branch2_ops,
1865 },
1866 },
1867};
1868
1869static struct clk_branch gcc_ce1_axi_clk = {
1870 .halt_reg = 0x1048,
1871 .halt_check = BRANCH_HALT_VOTED,
1872 .clkr = {
1873 .enable_reg = 0x1484,
1874 .enable_mask = BIT(4),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_ce1_axi_clk",
1877 .parent_names = (const char *[]){
1878 "system_noc_clk_src",
1879 },
1880 .num_parents = 1,
1881 .ops = &clk_branch2_ops,
1882 },
1883 },
1884};
1885
1886static struct clk_branch gcc_ce1_clk = {
1887 .halt_reg = 0x1050,
1888 .halt_check = BRANCH_HALT_VOTED,
1889 .clkr = {
1890 .enable_reg = 0x1484,
1891 .enable_mask = BIT(5),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "gcc_ce1_clk",
1894 .parent_names = (const char *[]){
1895 "ce1_clk_src",
1896 },
1897 .num_parents = 1,
1898 .ops = &clk_branch2_ops,
1899 },
1900 },
1901};
1902
1903static struct clk_branch gcc_ce2_ahb_clk = {
1904 .halt_reg = 0x108c,
1905 .halt_check = BRANCH_HALT_VOTED,
1906 .clkr = {
1907 .enable_reg = 0x1484,
1908 .enable_mask = BIT(0),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "gcc_ce2_ahb_clk",
1911 .parent_names = (const char *[]){
1912 "config_noc_clk_src",
1913 },
1914 .num_parents = 1,
1915 .ops = &clk_branch2_ops,
1916 },
1917 },
1918};
1919
1920static struct clk_branch gcc_ce2_axi_clk = {
1921 .halt_reg = 0x1088,
1922 .halt_check = BRANCH_HALT_VOTED,
1923 .clkr = {
1924 .enable_reg = 0x1484,
1925 .enable_mask = BIT(1),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "gcc_ce2_axi_clk",
1928 .parent_names = (const char *[]){
1929 "system_noc_clk_src",
1930 },
1931 .num_parents = 1,
1932 .ops = &clk_branch2_ops,
1933 },
1934 },
1935};
1936
1937static struct clk_branch gcc_ce2_clk = {
1938 .halt_reg = 0x1090,
1939 .halt_check = BRANCH_HALT_VOTED,
1940 .clkr = {
1941 .enable_reg = 0x1484,
1942 .enable_mask = BIT(2),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "gcc_ce2_clk",
1945 .parent_names = (const char *[]){
1946 "ce2_clk_src",
1947 },
1948 .num_parents = 1,
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_branch2_ops,
1951 },
1952 },
1953};
1954
1955static struct clk_branch gcc_ce3_ahb_clk = {
1956 .halt_reg = 0x1d0c,
1957 .halt_check = BRANCH_HALT_VOTED,
1958 .clkr = {
1959 .enable_reg = 0x1d0c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "gcc_ce3_ahb_clk",
1963 .parent_names = (const char *[]){
1964 "config_noc_clk_src",
1965 },
1966 .num_parents = 1,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970};
1971
1972static struct clk_branch gcc_ce3_axi_clk = {
1973 .halt_reg = 0x1088,
1974 .halt_check = BRANCH_HALT_VOTED,
1975 .clkr = {
1976 .enable_reg = 0x1d08,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_ce3_axi_clk",
1980 .parent_names = (const char *[]){
1981 "system_noc_clk_src",
1982 },
1983 .num_parents = 1,
1984 .ops = &clk_branch2_ops,
1985 },
1986 },
1987};
1988
1989static struct clk_branch gcc_ce3_clk = {
1990 .halt_reg = 0x1090,
1991 .halt_check = BRANCH_HALT_VOTED,
1992 .clkr = {
1993 .enable_reg = 0x1d04,
1994 .enable_mask = BIT(0),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "gcc_ce3_clk",
1997 .parent_names = (const char *[]){
1998 "ce3_clk_src",
1999 },
2000 .num_parents = 1,
2001 .flags = CLK_SET_RATE_PARENT,
2002 .ops = &clk_branch2_ops,
2003 },
2004 },
2005};
2006
2007static struct clk_branch gcc_gp1_clk = {
2008 .halt_reg = 0x1900,
2009 .clkr = {
2010 .enable_reg = 0x1900,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(struct clk_init_data){
2013 .name = "gcc_gp1_clk",
2014 .parent_names = (const char *[]){
2015 "gp1_clk_src",
2016 },
2017 .num_parents = 1,
2018 .flags = CLK_SET_RATE_PARENT,
2019 .ops = &clk_branch2_ops,
2020 },
2021 },
2022};
2023
2024static struct clk_branch gcc_gp2_clk = {
2025 .halt_reg = 0x1940,
2026 .clkr = {
2027 .enable_reg = 0x1940,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_gp2_clk",
2031 .parent_names = (const char *[]){
2032 "gp2_clk_src",
2033 },
2034 .num_parents = 1,
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2037 },
2038 },
2039};
2040
2041static struct clk_branch gcc_gp3_clk = {
2042 .halt_reg = 0x1980,
2043 .clkr = {
2044 .enable_reg = 0x1980,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_gp3_clk",
2048 .parent_names = (const char *[]){
2049 "gp3_clk_src",
2050 },
2051 .num_parents = 1,
2052 .flags = CLK_SET_RATE_PARENT,
2053 .ops = &clk_branch2_ops,
2054 },
2055 },
2056};
2057
2058static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2059 .halt_reg = 0x0248,
2060 .clkr = {
2061 .enable_reg = 0x0248,
2062 .enable_mask = BIT(0),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "gcc_ocmem_noc_cfg_ahb_clk",
2065 .parent_names = (const char *[]){
2066 "config_noc_clk_src",
2067 },
2068 .num_parents = 1,
2069 .ops = &clk_branch2_ops,
2070 },
2071 },
2072};
2073
2074static struct clk_branch gcc_pdm2_clk = {
2075 .halt_reg = 0x0ccc,
2076 .clkr = {
2077 .enable_reg = 0x0ccc,
2078 .enable_mask = BIT(0),
2079 .hw.init = &(struct clk_init_data){
2080 .name = "gcc_pdm2_clk",
2081 .parent_names = (const char *[]){
2082 "pdm2_clk_src",
2083 },
2084 .num_parents = 1,
2085 .flags = CLK_SET_RATE_PARENT,
2086 .ops = &clk_branch2_ops,
2087 },
2088 },
2089};
2090
2091static struct clk_branch gcc_pdm_ahb_clk = {
2092 .halt_reg = 0x0cc4,
2093 .clkr = {
2094 .enable_reg = 0x0cc4,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "gcc_pdm_ahb_clk",
2098 .parent_names = (const char *[]){
2099 "periph_noc_clk_src",
2100 },
2101 .num_parents = 1,
2102 .ops = &clk_branch2_ops,
2103 },
2104 },
2105};
2106
2107static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2108 .halt_reg = 0x01a4,
2109 .clkr = {
2110 .enable_reg = 0x01a4,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2114 .parent_names = (const char *[]){
2115 "usb_hsic_ahb_clk_src",
2116 },
2117 .num_parents = 1,
2118 .flags = CLK_SET_RATE_PARENT,
2119 .ops = &clk_branch2_ops,
2120 },
2121 },
2122};
2123
2124static struct clk_branch gcc_prng_ahb_clk = {
2125 .halt_reg = 0x0d04,
2126 .halt_check = BRANCH_HALT_VOTED,
2127 .clkr = {
2128 .enable_reg = 0x1484,
2129 .enable_mask = BIT(13),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "gcc_prng_ahb_clk",
2132 .parent_names = (const char *[]){
2133 "periph_noc_clk_src",
2134 },
2135 .num_parents = 1,
2136 .ops = &clk_branch2_ops,
2137 },
2138 },
2139};
2140
2141static struct clk_branch gcc_sdcc1_ahb_clk = {
2142 .halt_reg = 0x04c8,
2143 .clkr = {
2144 .enable_reg = 0x04c8,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "gcc_sdcc1_ahb_clk",
2148 .parent_names = (const char *[]){
2149 "periph_noc_clk_src",
2150 },
2151 .num_parents = 1,
2152 .ops = &clk_branch2_ops,
2153 },
2154 },
2155};
2156
2157static struct clk_branch gcc_sdcc1_apps_clk = {
2158 .halt_reg = 0x04c4,
2159 .clkr = {
2160 .enable_reg = 0x04c4,
2161 .enable_mask = BIT(0),
2162 .hw.init = &(struct clk_init_data){
2163 .name = "gcc_sdcc1_apps_clk",
2164 .parent_names = (const char *[]){
2165 "sdcc1_apps_clk_src",
2166 },
2167 .num_parents = 1,
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_branch2_ops,
2170 },
2171 },
2172};
2173
2174static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2175 .halt_reg = 0x04e8,
2176 .clkr = {
2177 .enable_reg = 0x04e8,
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_sdcc1_cdccal_ff_clk",
2181 .parent_names = (const char *[]){
2182 "xo"
2183 },
2184 .num_parents = 1,
2185 .ops = &clk_branch2_ops,
2186 },
2187 },
2188};
2189
2190static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2191 .halt_reg = 0x04e4,
2192 .clkr = {
2193 .enable_reg = 0x04e4,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "gcc_sdcc1_cdccal_sleep_clk",
2197 .parent_names = (const char *[]){
2198 "sleep_clk_src"
2199 },
2200 .num_parents = 1,
2201 .ops = &clk_branch2_ops,
2202 },
2203 },
2204};
2205
2206static struct clk_branch gcc_sdcc2_ahb_clk = {
2207 .halt_reg = 0x0508,
2208 .clkr = {
2209 .enable_reg = 0x0508,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "gcc_sdcc2_ahb_clk",
2213 .parent_names = (const char *[]){
2214 "periph_noc_clk_src",
2215 },
2216 .num_parents = 1,
2217 .ops = &clk_branch2_ops,
2218 },
2219 },
2220};
2221
2222static struct clk_branch gcc_sdcc2_apps_clk = {
2223 .halt_reg = 0x0504,
2224 .clkr = {
2225 .enable_reg = 0x0504,
2226 .enable_mask = BIT(0),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_sdcc2_apps_clk",
2229 .parent_names = (const char *[]){
2230 "sdcc2_apps_clk_src",
2231 },
2232 .num_parents = 1,
2233 .flags = CLK_SET_RATE_PARENT,
2234 .ops = &clk_branch2_ops,
2235 },
2236 },
2237};
2238
2239static struct clk_branch gcc_sdcc3_ahb_clk = {
2240 .halt_reg = 0x0548,
2241 .clkr = {
2242 .enable_reg = 0x0548,
2243 .enable_mask = BIT(0),
2244 .hw.init = &(struct clk_init_data){
2245 .name = "gcc_sdcc3_ahb_clk",
2246 .parent_names = (const char *[]){
2247 "periph_noc_clk_src",
2248 },
2249 .num_parents = 1,
2250 .ops = &clk_branch2_ops,
2251 },
2252 },
2253};
2254
2255static struct clk_branch gcc_sdcc3_apps_clk = {
2256 .halt_reg = 0x0544,
2257 .clkr = {
2258 .enable_reg = 0x0544,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "gcc_sdcc3_apps_clk",
2262 .parent_names = (const char *[]){
2263 "sdcc3_apps_clk_src",
2264 },
2265 .num_parents = 1,
2266 .flags = CLK_SET_RATE_PARENT,
2267 .ops = &clk_branch2_ops,
2268 },
2269 },
2270};
2271
2272static struct clk_branch gcc_sdcc4_ahb_clk = {
2273 .halt_reg = 0x0588,
2274 .clkr = {
2275 .enable_reg = 0x0588,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "gcc_sdcc4_ahb_clk",
2279 .parent_names = (const char *[]){
2280 "periph_noc_clk_src",
2281 },
2282 .num_parents = 1,
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286};
2287
2288static struct clk_branch gcc_sdcc4_apps_clk = {
2289 .halt_reg = 0x0584,
2290 .clkr = {
2291 .enable_reg = 0x0584,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "gcc_sdcc4_apps_clk",
2295 .parent_names = (const char *[]){
2296 "sdcc4_apps_clk_src",
2297 },
2298 .num_parents = 1,
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2301 },
2302 },
2303};
2304
2305static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2306 .halt_reg = 0x0108,
2307 .clkr = {
2308 .enable_reg = 0x0108,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gcc_sys_noc_usb3_axi_clk",
2312 .parent_names = (const char *[]){
2313 "usb30_master_clk_src",
2314 },
2315 .num_parents = 1,
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2318 },
2319 },
2320};
2321
2322static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2323 .halt_reg = 0x0138,
2324 .clkr = {
2325 .enable_reg = 0x0138,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_sys_noc_usb3_sec_axi_clk",
2329 .parent_names = (const char *[]){
2330 "usb30_sec_master_clk_src",
2331 },
2332 .num_parents = 1,
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2335 },
2336 },
2337};
2338
2339static struct clk_branch gcc_tsif_ahb_clk = {
2340 .halt_reg = 0x0d84,
2341 .clkr = {
2342 .enable_reg = 0x0d84,
2343 .enable_mask = BIT(0),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "gcc_tsif_ahb_clk",
2346 .parent_names = (const char *[]){
2347 "periph_noc_clk_src",
2348 },
2349 .num_parents = 1,
2350 .ops = &clk_branch2_ops,
2351 },
2352 },
2353};
2354
2355static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2356 .halt_reg = 0x0d8c,
2357 .clkr = {
2358 .enable_reg = 0x0d8c,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "gcc_tsif_inactivity_timers_clk",
2362 .parent_names = (const char *[]){
2363 "sleep_clk_src",
2364 },
2365 .num_parents = 1,
2366 .flags = CLK_SET_RATE_PARENT,
2367 .ops = &clk_branch2_ops,
2368 },
2369 },
2370};
2371
2372static struct clk_branch gcc_tsif_ref_clk = {
2373 .halt_reg = 0x0d88,
2374 .clkr = {
2375 .enable_reg = 0x0d88,
2376 .enable_mask = BIT(0),
2377 .hw.init = &(struct clk_init_data){
2378 .name = "gcc_tsif_ref_clk",
2379 .parent_names = (const char *[]){
2380 "tsif_ref_clk_src",
2381 },
2382 .num_parents = 1,
2383 .flags = CLK_SET_RATE_PARENT,
2384 .ops = &clk_branch2_ops,
2385 },
2386 },
2387};
2388
2389static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2390 .halt_reg = 0x04ac,
2391 .clkr = {
2392 .enable_reg = 0x04ac,
2393 .enable_mask = BIT(0),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "gcc_usb2a_phy_sleep_clk",
2396 .parent_names = (const char *[]){
2397 "sleep_clk_src",
2398 },
2399 .num_parents = 1,
2400 .ops = &clk_branch2_ops,
2401 },
2402 },
2403};
2404
2405static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2406 .halt_reg = 0x04b4,
2407 .clkr = {
2408 .enable_reg = 0x04b4,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_usb2b_phy_sleep_clk",
2412 .parent_names = (const char *[]){
2413 "sleep_clk_src",
2414 },
2415 .num_parents = 1,
2416 .ops = &clk_branch2_ops,
2417 },
2418 },
2419};
2420
2421static struct clk_branch gcc_usb30_master_clk = {
2422 .halt_reg = 0x03c8,
2423 .clkr = {
2424 .enable_reg = 0x03c8,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_usb30_master_clk",
2428 .parent_names = (const char *[]){
2429 "usb30_master_clk_src",
2430 },
2431 .num_parents = 1,
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2434 },
2435 },
2436};
2437
2438static struct clk_branch gcc_usb30_sec_master_clk = {
2439 .halt_reg = 0x1bc8,
2440 .clkr = {
2441 .enable_reg = 0x1bc8,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "gcc_usb30_sec_master_clk",
2445 .parent_names = (const char *[]){
2446 "usb30_sec_master_clk_src",
2447 },
2448 .num_parents = 1,
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2451 },
2452 },
2453};
2454
2455static struct clk_branch gcc_usb30_mock_utmi_clk = {
2456 .halt_reg = 0x03d0,
2457 .clkr = {
2458 .enable_reg = 0x03d0,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "gcc_usb30_mock_utmi_clk",
2462 .parent_names = (const char *[]){
2463 "usb30_mock_utmi_clk_src",
2464 },
2465 .num_parents = 1,
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2468 },
2469 },
2470};
2471
2472static struct clk_branch gcc_usb30_sleep_clk = {
2473 .halt_reg = 0x03cc,
2474 .clkr = {
2475 .enable_reg = 0x03cc,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_usb30_sleep_clk",
2479 .parent_names = (const char *[]){
2480 "sleep_clk_src",
2481 },
2482 .num_parents = 1,
2483 .ops = &clk_branch2_ops,
2484 },
2485 },
2486};
2487
2488static struct clk_branch gcc_usb_hs_ahb_clk = {
2489 .halt_reg = 0x0488,
2490 .clkr = {
2491 .enable_reg = 0x0488,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(struct clk_init_data){
2494 .name = "gcc_usb_hs_ahb_clk",
2495 .parent_names = (const char *[]){
2496 "periph_noc_clk_src",
2497 },
2498 .num_parents = 1,
2499 .ops = &clk_branch2_ops,
2500 },
2501 },
2502};
2503
2504static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2505 .halt_reg = 0x048c,
2506 .clkr = {
2507 .enable_reg = 0x048c,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_usb_hs_inactivity_timers_clk",
2511 .parent_names = (const char *[]){
2512 "sleep_clk_src",
2513 },
2514 .num_parents = 1,
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2517 },
2518 },
2519};
2520
2521static struct clk_branch gcc_usb_hs_system_clk = {
2522 .halt_reg = 0x0484,
2523 .clkr = {
2524 .enable_reg = 0x0484,
2525 .enable_mask = BIT(0),
2526 .hw.init = &(struct clk_init_data){
2527 .name = "gcc_usb_hs_system_clk",
2528 .parent_names = (const char *[]){
2529 "usb_hs_system_clk_src",
2530 },
2531 .num_parents = 1,
2532 .flags = CLK_SET_RATE_PARENT,
2533 .ops = &clk_branch2_ops,
2534 },
2535 },
2536};
2537
2538static struct clk_branch gcc_usb_hsic_ahb_clk = {
2539 .halt_reg = 0x0408,
2540 .clkr = {
2541 .enable_reg = 0x0408,
2542 .enable_mask = BIT(0),
2543 .hw.init = &(struct clk_init_data){
2544 .name = "gcc_usb_hsic_ahb_clk",
2545 .parent_names = (const char *[]){
2546 "periph_noc_clk_src",
2547 },
2548 .num_parents = 1,
2549 .ops = &clk_branch2_ops,
2550 },
2551 },
2552};
2553
2554static struct clk_branch gcc_usb_hsic_clk = {
2555 .halt_reg = 0x0410,
2556 .clkr = {
2557 .enable_reg = 0x0410,
2558 .enable_mask = BIT(0),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "gcc_usb_hsic_clk",
2561 .parent_names = (const char *[]){
2562 "usb_hsic_clk_src",
2563 },
2564 .num_parents = 1,
2565 .flags = CLK_SET_RATE_PARENT,
2566 .ops = &clk_branch2_ops,
2567 },
2568 },
2569};
2570
2571static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2572 .halt_reg = 0x0414,
2573 .clkr = {
2574 .enable_reg = 0x0414,
2575 .enable_mask = BIT(0),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "gcc_usb_hsic_io_cal_clk",
2578 .parent_names = (const char *[]){
2579 "usb_hsic_io_cal_clk_src",
2580 },
2581 .num_parents = 1,
2582 .flags = CLK_SET_RATE_PARENT,
2583 .ops = &clk_branch2_ops,
2584 },
2585 },
2586};
2587
2588static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2589 .halt_reg = 0x0418,
2590 .clkr = {
2591 .enable_reg = 0x0418,
2592 .enable_mask = BIT(0),
2593 .hw.init = &(struct clk_init_data){
2594 .name = "gcc_usb_hsic_io_cal_sleep_clk",
2595 .parent_names = (const char *[]){
2596 "sleep_clk_src",
2597 },
2598 .num_parents = 1,
2599 .ops = &clk_branch2_ops,
2600 },
2601 },
2602};
2603
2604static struct clk_branch gcc_usb_hsic_system_clk = {
2605 .halt_reg = 0x040c,
2606 .clkr = {
2607 .enable_reg = 0x040c,
2608 .enable_mask = BIT(0),
2609 .hw.init = &(struct clk_init_data){
2610 .name = "gcc_usb_hsic_system_clk",
2611 .parent_names = (const char *[]){
2612 "usb_hsic_system_clk_src",
2613 },
2614 .num_parents = 1,
2615 .flags = CLK_SET_RATE_PARENT,
2616 .ops = &clk_branch2_ops,
2617 },
2618 },
2619};
2620
2621static struct clk_regmap *gcc_apq8084_clocks[] = {
2622 [GPLL0] = &gpll0.clkr,
2623 [GPLL0_VOTE] = &gpll0_vote,
2624 [GPLL1] = &gpll1.clkr,
2625 [GPLL1_VOTE] = &gpll1_vote,
2626 [GPLL4] = &gpll4.clkr,
2627 [GPLL4_VOTE] = &gpll4_vote,
2628 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2629 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2630 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2631 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2632 [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
2633 [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
2634 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2635 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2636 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2637 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2638 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2639 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2640 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2641 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2642 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2643 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2644 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2645 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2646 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2647 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2648 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2649 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2650 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2651 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2652 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2653 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2654 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2655 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2656 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2657 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2658 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2659 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2660 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2661 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2662 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2663 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2664 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2665 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2666 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2667 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2668 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2669 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2670 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2671 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2672 [CE3_CLK_SRC] = &ce3_clk_src.clkr,
2673 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2674 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2675 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2676 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2677 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2678 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2679 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2680 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2681 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2682 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2683 [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
2684 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2685 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2686 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2687 [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
2688 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2689 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2690 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2691 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2692 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2693 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2694 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2695 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2696 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2697 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2698 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2699 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2700 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2701 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2702 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2703 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2704 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2705 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2706 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2707 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2708 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2709 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2710 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2711 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2712 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2713 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2714 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2715 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2716 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2717 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2718 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2719 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2720 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2721 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2722 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2723 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2724 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2725 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2726 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2727 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2728 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2729 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2730 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2731 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2732 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2733 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2734 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2735 [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
2736 [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
2737 [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
2738 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2739 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2740 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2741 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2742 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2743 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2744 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
2745 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2746 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2747 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2748 [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
2749 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
2750 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2751 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2752 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2753 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2754 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2755 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2756 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2757 [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
2758 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2759 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2760 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2761 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2762 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2763 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2764 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2765 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2766 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
2767 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
2768 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
2769 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2770 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
2771 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2772 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2773 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2774 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2775 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2776 [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
2777 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2778};
2779
2780static const struct qcom_reset_map gcc_apq8084_resets[] = {
2781 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2782 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2783 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2784 [GCC_IMEM_BCR] = { 0x0200 },
2785 [GCC_MMSS_BCR] = { 0x0240 },
2786 [GCC_QDSS_BCR] = { 0x0300 },
2787 [GCC_USB_30_BCR] = { 0x03c0 },
2788 [GCC_USB3_PHY_BCR] = { 0x03fc },
2789 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2790 [GCC_USB_HS_BCR] = { 0x0480 },
2791 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2792 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2793 [GCC_SDCC1_BCR] = { 0x04c0 },
2794 [GCC_SDCC2_BCR] = { 0x0500 },
2795 [GCC_SDCC3_BCR] = { 0x0540 },
2796 [GCC_SDCC4_BCR] = { 0x0580 },
2797 [GCC_BLSP1_BCR] = { 0x05c0 },
2798 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2799 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2800 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2801 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2802 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2803 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2804 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2805 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2806 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2807 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2808 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2809 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2810 [GCC_BLSP2_BCR] = { 0x0940 },
2811 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2812 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2813 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2814 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2815 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2816 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2817 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2818 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2819 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2820 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2821 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2822 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2823 [GCC_PDM_BCR] = { 0x0cc0 },
2824 [GCC_PRNG_BCR] = { 0x0d00 },
2825 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2826 [GCC_TSIF_BCR] = { 0x0d80 },
2827 [GCC_TCSR_BCR] = { 0x0dc0 },
2828 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2829 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2830 [GCC_TLMM_BCR] = { 0x0e80 },
2831 [GCC_MPM_BCR] = { 0x0ec0 },
2832 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2833 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2834 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2835 [GCC_SPMI_BCR] = { 0x0fc0 },
2836 [GCC_SPDM_BCR] = { 0x1000 },
2837 [GCC_CE1_BCR] = { 0x1040 },
2838 [GCC_CE2_BCR] = { 0x1080 },
2839 [GCC_BIMC_BCR] = { 0x1100 },
2840 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2841 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2842 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2843 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2844 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2845 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2846 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2847 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2848 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2849 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2850 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2851 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2852 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2853 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2854 [GCC_DEHR_BCR] = { 0x1300 },
2855 [GCC_RBCPR_BCR] = { 0x1380 },
2856 [GCC_MSS_RESTART] = { 0x1680 },
2857 [GCC_LPASS_RESTART] = { 0x16c0 },
2858 [GCC_WCSS_RESTART] = { 0x1700 },
2859 [GCC_VENUS_RESTART] = { 0x1740 },
2860 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
2861 [GCC_SPSS_BCR] = { 0x1a80 },
2862 [GCC_PCIE_0_BCR] = { 0x1ac0 },
2863 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
2864 [GCC_PCIE_1_BCR] = { 0x1b40 },
2865 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
2866 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
2867 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
2868 [GCC_SATA_BCR] = { 0x1c40 },
2869 [GCC_CE3_BCR] = { 0x1d00 },
2870 [GCC_UFS_BCR] = { 0x1d40 },
2871 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
2872};
2873
2874static const struct regmap_config gcc_apq8084_regmap_config = {
2875 .reg_bits = 32,
2876 .reg_stride = 4,
2877 .val_bits = 32,
2878 .max_register = 0x1fc0,
2879 .fast_io = true,
2880};
2881
2882static const struct qcom_cc_desc gcc_apq8084_desc = {
2883 .config = &gcc_apq8084_regmap_config,
2884 .clks = gcc_apq8084_clocks,
2885 .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
2886 .resets = gcc_apq8084_resets,
2887 .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
2888};
2889
2890static const struct of_device_id gcc_apq8084_match_table[] = {
2891 { .compatible = "qcom,gcc-apq8084" },
2892 { }
2893};
2894MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
2895
2896static int gcc_apq8084_probe(struct platform_device *pdev)
2897{
2898 struct clk *clk;
2899 struct device *dev = &pdev->dev;
2900
2901 /* Temporary until RPM clocks supported */
2902 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2903 if (IS_ERR(clk))
2904 return PTR_ERR(clk);
2905
2906 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2907 CLK_IS_ROOT, 32768);
2908 if (IS_ERR(clk))
2909 return PTR_ERR(clk);
2910
2911 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
2912}
2913
2914static int gcc_apq8084_remove(struct platform_device *pdev)
2915{
2916 qcom_cc_remove(pdev);
2917 return 0;
2918}
2919
2920static struct platform_driver gcc_apq8084_driver = {
2921 .probe = gcc_apq8084_probe,
2922 .remove = gcc_apq8084_remove,
2923 .driver = {
2924 .name = "gcc-apq8084",
2925 .owner = THIS_MODULE,
2926 .of_match_table = gcc_apq8084_match_table,
2927 },
2928};
2929
2930static int __init gcc_apq8084_init(void)
2931{
2932 return platform_driver_register(&gcc_apq8084_driver);
2933}
2934core_initcall(gcc_apq8084_init);
2935
2936static void __exit gcc_apq8084_exit(void)
2937{
2938 platform_driver_unregister(&gcc_apq8084_driver);
2939}
2940module_exit(gcc_apq8084_exit);
2941
2942MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
2943MODULE_LICENSE("GPL v2");
2944MODULE_ALIAS("platform:gcc-apq8084");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 17:05:52 -0400