diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2014-03-12 11:01:07 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2014-03-12 11:01:07 -0400 |
commit | ffb12cf002edbc5927079f51bebde428d601f723 (patch) | |
tree | 1f04d80df9db8883037d59c81f5836770eecfdc6 /drivers/clk/mvebu/dove.c | |
parent | 1a75b8e64571a85d5e648cfdf4c40e0d9923abc5 (diff) | |
parent | c1bacbae8192dd2a9ebadd22d793b68054f6c6e5 (diff) |
Merge branch 'irq/for-gpio' into irq/core
Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/clk/mvebu/dove.c')
-rw-r--r-- | drivers/clk/mvebu/dove.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c index 38aee1e3f242..b8c2424ac926 100644 --- a/drivers/clk/mvebu/dove.c +++ b/drivers/clk/mvebu/dove.c | |||
@@ -154,12 +154,6 @@ static const struct coreclk_soc_desc dove_coreclks = { | |||
154 | .num_ratios = ARRAY_SIZE(dove_coreclk_ratios), | 154 | .num_ratios = ARRAY_SIZE(dove_coreclk_ratios), |
155 | }; | 155 | }; |
156 | 156 | ||
157 | static void __init dove_coreclk_init(struct device_node *np) | ||
158 | { | ||
159 | mvebu_coreclk_setup(np, &dove_coreclks); | ||
160 | } | ||
161 | CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init); | ||
162 | |||
163 | /* | 157 | /* |
164 | * Clock Gating Control | 158 | * Clock Gating Control |
165 | */ | 159 | */ |
@@ -186,9 +180,14 @@ static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = { | |||
186 | { } | 180 | { } |
187 | }; | 181 | }; |
188 | 182 | ||
189 | static void __init dove_clk_gating_init(struct device_node *np) | 183 | static void __init dove_clk_init(struct device_node *np) |
190 | { | 184 | { |
191 | mvebu_clk_gating_setup(np, dove_gating_desc); | 185 | struct device_node *cgnp = |
186 | of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock"); | ||
187 | |||
188 | mvebu_coreclk_setup(np, &dove_coreclks); | ||
189 | |||
190 | if (cgnp) | ||
191 | mvebu_clk_gating_setup(cgnp, dove_gating_desc); | ||
192 | } | 192 | } |
193 | CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock", | 193 | CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init); |
194 | dove_clk_gating_init); | ||