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authorHaojian Zhuang <haojian.zhuang@gmail.com>2013-11-12 19:51:23 -0500
committerHaojian Zhuang <haojian.zhuang@gmail.com>2013-12-04 05:36:45 -0500
commit0aa0c95f743a06893dbc494b2a75fbf7093330d4 (patch)
tree79608f2bdc02486b7faad8d451b53428d40a348e /drivers/clk/hisilicon
parent6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff)
clk: hisilicon: add common clock support
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'drivers/clk/hisilicon')
-rw-r--r--drivers/clk/hisilicon/Makefile5
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c242
-rw-r--r--drivers/clk/hisilicon/clk.c171
-rw-r--r--drivers/clk/hisilicon/clk.h103
-rw-r--r--drivers/clk/hisilicon/clkgate-separated.c130
5 files changed, 651 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
new file mode 100644
index 000000000000..a049108341fc
--- /dev/null
+++ b/drivers/clk/hisilicon/Makefile
@@ -0,0 +1,5 @@
1#
2# Hisilicon Clock specific Makefile
3#
4
5obj-y += clk.o clkgate-separated.o clk-hi3620.o
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
new file mode 100644
index 000000000000..b66b074fbda5
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -0,0 +1,242 @@
1/*
2 * Hisilicon Hi3620 clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/io.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_device.h>
33#include <linux/slab.h>
34#include <linux/clk.h>
35
36#include <dt-bindings/clock/hi3620-clock.h>
37
38#include "clk.h"
39
40/* clock parent list */
41static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
42static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
43static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
44static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
45static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
46static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
47static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
48static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
49static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
50static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
51static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
52static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
53static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
54static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
55static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
56static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
57static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
58static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
59/* share axi parent */
60static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
61static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
62static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
63static const char *sd_mux_p[] __initdata = { "armpll3", "armpll2", };
64static const char *mmc1_mux_p[] __initdata = { "armpll3", "armpll2", };
65static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
66static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
67static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
68static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
69static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
70static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
71static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
72 "armpll3", "armpll5", };
73static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
74static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
75 "armpll3", "armpll5", };
76static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
77static const char *mmc2_mux_p[] __initdata = { "armpll3", "armpll2", };
78static const char *mmc3_mux_p[] __initdata = { "armpll3", "armpll2", };
79
80
81/* fixed rate clocks */
82static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
83 { HI3620_OSC32K, "osc32k", NULL, CLK_IS_ROOT, 32768, },
84 { HI3620_OSC26M, "osc26m", NULL, CLK_IS_ROOT, 26000000, },
85 { HI3620_PCLK, "pclk", NULL, CLK_IS_ROOT, 26000000, },
86 { HI3620_PLL_ARM0, "armpll0", NULL, CLK_IS_ROOT, 1600000000, },
87 { HI3620_PLL_ARM1, "armpll1", NULL, CLK_IS_ROOT, 1600000000, },
88 { HI3620_PLL_PERI, "armpll2", NULL, CLK_IS_ROOT, 1440000000, },
89 { HI3620_PLL_USB, "armpll3", NULL, CLK_IS_ROOT, 1440000000, },
90 { HI3620_PLL_HDMI, "armpll4", NULL, CLK_IS_ROOT, 1188000000, },
91 { HI3620_PLL_GPU, "armpll5", NULL, CLK_IS_ROOT, 1300000000, },
92};
93
94/* fixed factor clocks */
95static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = {
96 { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, },
97 { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, },
98 { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, },
99};
100
101static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
102 { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, },
103 { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, },
104 { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, },
105 { HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0, 21, 2, 0, },
106 { HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x18, 0, 2, 0, },
107 { HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x18, 2, 2, 0, },
108 { HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x18, 4, 2, 0, },
109 { HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x18, 6, 2, 0, },
110 { HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x18, 8, 2, 0, },
111 { HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x18, 10, 2, 0, },
112 { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
113 { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
114 { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },
115 { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
116 { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
117 { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
118 { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
119 { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
120 { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
121 { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
122 { HI3620_PWM1_MUX, "pwm1_mux", pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, },
123 { HI3620_SD_MUX, "sd_mux", sd_mux_p, ARRAY_SIZE(sd_mux_p), CLK_SET_RATE_PARENT, 0x108, 4, 1, CLK_MUX_HIWORD_MASK, },
124 { HI3620_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p), CLK_SET_RATE_PARENT, 0x108, 9, 1, CLK_MUX_HIWORD_MASK, },
125 { HI3620_MMC1_MUX2, "mmc1_mux2", mmc1_mux2_p, ARRAY_SIZE(mmc1_mux2_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, },
126 { HI3620_G2D_MUX, "g2d_mux", g2d_mux_p, ARRAY_SIZE(g2d_mux_p), CLK_SET_RATE_PARENT, 0x10c, 5, 1, CLK_MUX_HIWORD_MASK, },
127 { HI3620_VENC_MUX, "venc_mux", venc_mux_p, ARRAY_SIZE(venc_mux_p), CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, },
128 { HI3620_VDEC_MUX, "vdec_mux", vdec_mux_p, ARRAY_SIZE(vdec_mux_p), CLK_SET_RATE_PARENT, 0x110, 5, 1, CLK_MUX_HIWORD_MASK, },
129 { HI3620_VPP_MUX, "vpp_mux", vpp_mux_p, ARRAY_SIZE(vpp_mux_p), CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, },
130 { HI3620_EDC0_MUX, "edc0_mux", edc0_mux_p, ARRAY_SIZE(edc0_mux_p), CLK_SET_RATE_PARENT, 0x114, 6, 1, CLK_MUX_HIWORD_MASK, },
131 { HI3620_LDI0_MUX, "ldi0_mux", ldi0_mux_p, ARRAY_SIZE(ldi0_mux_p), CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, },
132 { HI3620_EDC1_MUX, "edc1_mux", edc1_mux_p, ARRAY_SIZE(edc1_mux_p), CLK_SET_RATE_PARENT, 0x118, 6, 1, CLK_MUX_HIWORD_MASK, },
133 { HI3620_LDI1_MUX, "ldi1_mux", ldi1_mux_p, ARRAY_SIZE(ldi1_mux_p), CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, },
134 { HI3620_RCLK_HSIC, "rclk_hsic", rclk_hsic_p, ARRAY_SIZE(rclk_hsic_p), CLK_SET_RATE_PARENT, 0x130, 2, 1, CLK_MUX_HIWORD_MASK, },
135 { HI3620_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), CLK_SET_RATE_PARENT, 0x140, 4, 1, CLK_MUX_HIWORD_MASK, },
136 { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, },
137};
138
139static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
140 { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_MUX_HIWORD_MASK, NULL, },
141 { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_MUX_HIWORD_MASK, NULL, },
142 { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_MUX_HIWORD_MASK, NULL, },
143 { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_MUX_HIWORD_MASK, NULL, },
144 { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_MUX_HIWORD_MASK, NULL, },
145 { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_MUX_HIWORD_MASK, NULL, },
146 { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_MUX_HIWORD_MASK, NULL, },
147};
148
149static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = {
150 { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", 0, 0x20, 0, 0, },
151 { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", 0, 0x20, 1, 0, },
152 { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", 0, 0x20, 2, 0, },
153 { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", 0, 0x20, 3, 0, },
154 { HI3620_RTCCLK, "rtcclk", "pclk", 0, 0x20, 5, 0, },
155 { HI3620_KPC_CLK, "kpc_clk", "pclk", 0, 0x20, 6, 0, },
156 { HI3620_GPIOCLK0, "gpioclk0", "pclk", 0, 0x20, 8, 0, },
157 { HI3620_GPIOCLK1, "gpioclk1", "pclk", 0, 0x20, 9, 0, },
158 { HI3620_GPIOCLK2, "gpioclk2", "pclk", 0, 0x20, 10, 0, },
159 { HI3620_GPIOCLK3, "gpioclk3", "pclk", 0, 0x20, 11, 0, },
160 { HI3620_GPIOCLK4, "gpioclk4", "pclk", 0, 0x20, 12, 0, },
161 { HI3620_GPIOCLK5, "gpioclk5", "pclk", 0, 0x20, 13, 0, },
162 { HI3620_GPIOCLK6, "gpioclk6", "pclk", 0, 0x20, 14, 0, },
163 { HI3620_GPIOCLK7, "gpioclk7", "pclk", 0, 0x20, 15, 0, },
164 { HI3620_GPIOCLK8, "gpioclk8", "pclk", 0, 0x20, 16, 0, },
165 { HI3620_GPIOCLK9, "gpioclk9", "pclk", 0, 0x20, 17, 0, },
166 { HI3620_GPIOCLK10, "gpioclk10", "pclk", 0, 0x20, 18, 0, },
167 { HI3620_GPIOCLK11, "gpioclk11", "pclk", 0, 0x20, 19, 0, },
168 { HI3620_GPIOCLK12, "gpioclk12", "pclk", 0, 0x20, 20, 0, },
169 { HI3620_GPIOCLK13, "gpioclk13", "pclk", 0, 0x20, 21, 0, },
170 { HI3620_GPIOCLK14, "gpioclk14", "pclk", 0, 0x20, 22, 0, },
171 { HI3620_GPIOCLK15, "gpioclk15", "pclk", 0, 0x20, 23, 0, },
172 { HI3620_GPIOCLK16, "gpioclk16", "pclk", 0, 0x20, 24, 0, },
173 { HI3620_GPIOCLK17, "gpioclk17", "pclk", 0, 0x20, 25, 0, },
174 { HI3620_GPIOCLK18, "gpioclk18", "pclk", 0, 0x20, 26, 0, },
175 { HI3620_GPIOCLK19, "gpioclk19", "pclk", 0, 0x20, 27, 0, },
176 { HI3620_GPIOCLK20, "gpioclk20", "pclk", 0, 0x20, 28, 0, },
177 { HI3620_GPIOCLK21, "gpioclk21", "pclk", 0, 0x20, 29, 0, },
178 { HI3620_DPHY0_CLK, "dphy0_clk", "osc26m", 0, 0x30, 15, 0, },
179 { HI3620_DPHY1_CLK, "dphy1_clk", "osc26m", 0, 0x30, 16, 0, },
180 { HI3620_DPHY2_CLK, "dphy2_clk", "osc26m", 0, 0x30, 17, 0, },
181 { HI3620_USBPHY_CLK, "usbphy_clk", "rclk_pico", 0, 0x30, 24, 0, },
182 { HI3620_ACP_CLK, "acp_clk", "rclk_cfgaxi", 0, 0x30, 28, 0, },
183 { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", 0, 0x40, 3, 0, },
184 { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", 0, 0x40, 4, 0, },
185 { HI3620_TIMERCLK89, "timerclk89", "rclk_tcxo", 0, 0x40, 5, 0, },
186 { HI3620_PWMCLK0, "pwmclk0", "pwm0_mux", 0, 0x40, 7, 0, },
187 { HI3620_PWMCLK1, "pwmclk1", "pwm1_mux", 0, 0x40, 8, 0, },
188 { HI3620_UARTCLK0, "uartclk0", "uart0_mux", 0, 0x40, 16, 0, },
189 { HI3620_UARTCLK1, "uartclk1", "uart1_mux", 0, 0x40, 17, 0, },
190 { HI3620_UARTCLK2, "uartclk2", "uart2_mux", 0, 0x40, 18, 0, },
191 { HI3620_UARTCLK3, "uartclk3", "uart3_mux", 0, 0x40, 19, 0, },
192 { HI3620_UARTCLK4, "uartclk4", "uart4_mux", 0, 0x40, 20, 0, },
193 { HI3620_SPICLK0, "spiclk0", "spi0_mux", 0, 0x40, 21, 0, },
194 { HI3620_SPICLK1, "spiclk1", "spi1_mux", 0, 0x40, 22, 0, },
195 { HI3620_SPICLK2, "spiclk2", "spi2_mux", 0, 0x40, 23, 0, },
196 { HI3620_I2CCLK0, "i2cclk0", "pclk", 0, 0x40, 24, 0, },
197 { HI3620_I2CCLK1, "i2cclk1", "pclk", 0, 0x40, 25, 0, },
198 { HI3620_SCI_CLK, "sci_clk", "osc26m", 0, 0x40, 26, 0, },
199 { HI3620_I2CCLK2, "i2cclk2", "pclk", 0, 0x40, 28, 0, },
200 { HI3620_I2CCLK3, "i2cclk3", "pclk", 0, 0x40, 29, 0, },
201 { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi", 0, 0x50, 9, 0, },
202 { HI3620_DMAC_CLK, "dmac_clk", "rclk_cfgaxi", 0, 0x50, 10, 0, },
203 { HI3620_USB2DVC_CLK, "usb2dvc_clk", "rclk_cfgaxi", 0, 0x50, 17, 0, },
204 { HI3620_SD_CLK, "sd_clk", "sd_div", 0, 0x50, 20, 0, },
205 { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", 0, 0x50, 21, 0, },
206 { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", 0, 0x50, 22, 0, },
207 { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", 0, 0x50, 23, 0, },
208 { HI3620_MCU_CLK, "mcu_clk", "acp_clk", 0, 0x50, 24, 0, },
209};
210
211static void __init hi3620_clk_init(struct device_node *np)
212{
213 void __iomem *base;
214
215 if (np) {
216 base = of_iomap(np, 0);
217 if (!base) {
218 pr_err("failed to map Hi3620 clock registers\n");
219 return;
220 }
221 } else {
222 pr_err("failed to find Hi3620 clock node in DTS\n");
223 return;
224 }
225
226 hisi_clk_init(np, HI3620_NR_CLKS);
227
228 hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
229 ARRAY_SIZE(hi3620_fixed_rate_clks),
230 base);
231 hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
232 ARRAY_SIZE(hi3620_fixed_factor_clks),
233 base);
234 hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
235 base);
236 hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
237 base);
238 hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,
239 ARRAY_SIZE(hi3620_seperated_gate_clks),
240 base);
241}
242CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
new file mode 100644
index 000000000000..a3a7152c92d9
--- /dev/null
+++ b/drivers/clk/hisilicon/clk.c
@@ -0,0 +1,171 @@
1/*
2 * Hisilicon clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/delay.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_device.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36
37#include "clk.h"
38
39static DEFINE_SPINLOCK(hisi_clk_lock);
40static struct clk **clk_table;
41static struct clk_onecell_data clk_data;
42
43void __init hisi_clk_init(struct device_node *np, int nr_clks)
44{
45 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
46 if (!clk_table) {
47 pr_err("%s: could not allocate clock lookup table\n", __func__);
48 return;
49 }
50 clk_data.clks = clk_table;
51 clk_data.clk_num = nr_clks;
52 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
53}
54
55void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
56 int nums, void __iomem *base)
57{
58 struct clk *clk;
59 int i;
60
61 for (i = 0; i < nums; i++) {
62 clk = clk_register_fixed_rate(NULL, clks[i].name,
63 clks[i].parent_name,
64 clks[i].flags,
65 clks[i].fixed_rate);
66 if (IS_ERR(clk)) {
67 pr_err("%s: failed to register clock %s\n",
68 __func__, clks[i].name);
69 continue;
70 }
71 }
72}
73
74void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
75 int nums, void __iomem *base)
76{
77 struct clk *clk;
78 int i;
79
80 for (i = 0; i < nums; i++) {
81 clk = clk_register_fixed_factor(NULL, clks[i].name,
82 clks[i].parent_name,
83 clks[i].flags, clks[i].mult,
84 clks[i].div);
85 if (IS_ERR(clk)) {
86 pr_err("%s: failed to register clock %s\n",
87 __func__, clks[i].name);
88 continue;
89 }
90 }
91}
92
93void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
94 int nums, void __iomem *base)
95{
96 struct clk *clk;
97 int i;
98
99 for (i = 0; i < nums; i++) {
100 clk = clk_register_mux(NULL, clks[i].name, clks[i].parent_names,
101 clks[i].num_parents, clks[i].flags,
102 base + clks[i].offset, clks[i].shift,
103 clks[i].width, clks[i].mux_flags,
104 &hisi_clk_lock);
105 if (IS_ERR(clk)) {
106 pr_err("%s: failed to register clock %s\n",
107 __func__, clks[i].name);
108 continue;
109 }
110
111 if (clks[i].alias)
112 clk_register_clkdev(clk, clks[i].alias, NULL);
113
114 clk_table[clks[i].id] = clk;
115 }
116}
117
118void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
119 int nums, void __iomem *base)
120{
121 struct clk *clk;
122 int i;
123
124 for (i = 0; i < nums; i++) {
125 clk = clk_register_divider_table(NULL, clks[i].name,
126 clks[i].parent_name,
127 clks[i].flags,
128 base + clks[i].offset,
129 clks[i].shift, clks[i].width,
130 clks[i].div_flags,
131 clks[i].table,
132 &hisi_clk_lock);
133 if (IS_ERR(clk)) {
134 pr_err("%s: failed to register clock %s\n",
135 __func__, clks[i].name);
136 continue;
137 }
138
139 if (clks[i].alias)
140 clk_register_clkdev(clk, clks[i].alias, NULL);
141
142 clk_table[clks[i].id] = clk;
143 }
144}
145
146void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
147 int nums, void __iomem *base)
148{
149 struct clk *clk;
150 int i;
151
152 for (i = 0; i < nums; i++) {
153 clk = hisi_register_clkgate_sep(NULL, clks[i].name,
154 clks[i].parent_name,
155 clks[i].flags,
156 base + clks[i].offset,
157 clks[i].bit_idx,
158 clks[i].gate_flags,
159 &hisi_clk_lock);
160 if (IS_ERR(clk)) {
161 pr_err("%s: failed to register clock %s\n",
162 __func__, clks[i].name);
163 continue;
164 }
165
166 if (clks[i].alias)
167 clk_register_clkdev(clk, clks[i].alias, NULL);
168
169 clk_table[clks[i].id] = clk;
170 }
171}
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
new file mode 100644
index 000000000000..4a6beebefb7a
--- /dev/null
+++ b/drivers/clk/hisilicon/clk.h
@@ -0,0 +1,103 @@
1/*
2 * Hisilicon Hi3620 clock gate driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#ifndef __HISI_CLK_H
27#define __HISI_CLK_H
28
29#include <linux/clk-provider.h>
30#include <linux/io.h>
31#include <linux/spinlock.h>
32
33struct hisi_fixed_rate_clock {
34 unsigned int id;
35 char *name;
36 const char *parent_name;
37 unsigned long flags;
38 unsigned long fixed_rate;
39};
40
41struct hisi_fixed_factor_clock {
42 unsigned int id;
43 char *name;
44 const char *parent_name;
45 unsigned long mult;
46 unsigned long div;
47 unsigned long flags;
48};
49
50struct hisi_mux_clock {
51 unsigned int id;
52 const char *name;
53 const char **parent_names;
54 u8 num_parents;
55 unsigned long flags;
56 unsigned long offset;
57 u8 shift;
58 u8 width;
59 u8 mux_flags;
60 const char *alias;
61};
62
63struct hisi_divider_clock {
64 unsigned int id;
65 const char *name;
66 const char *parent_name;
67 unsigned long flags;
68 unsigned long offset;
69 u8 shift;
70 u8 width;
71 u8 div_flags;
72 struct clk_div_table *table;
73 const char *alias;
74};
75
76struct hisi_gate_clock {
77 unsigned int id;
78 const char *name;
79 const char *parent_name;
80 unsigned long flags;
81 unsigned long offset;
82 u8 bit_idx;
83 u8 gate_flags;
84 const char *alias;
85};
86
87struct clk *hisi_register_clkgate_sep(struct device *, const char *,
88 const char *, unsigned long,
89 void __iomem *, u8,
90 u8, spinlock_t *);
91
92void __init hisi_clk_init(struct device_node *, int);
93void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
94 int, void __iomem *);
95void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
96 int, void __iomem *);
97void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
98 void __iomem *);
99void __init hisi_clk_register_divider(struct hisi_divider_clock *,
100 int, void __iomem *);
101void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
102 int, void __iomem *);
103#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c
new file mode 100644
index 000000000000..b03d5a7246f9
--- /dev/null
+++ b/drivers/clk/hisilicon/clkgate-separated.c
@@ -0,0 +1,130 @@
1/*
2 * Hisilicon clock separated gate driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/io.h>
30#include <linux/slab.h>
31#include <linux/clk.h>
32
33#include "clk.h"
34
35/* clock separated gate register offset */
36#define CLKGATE_SEPERATED_ENABLE 0x0
37#define CLKGATE_SEPERATED_DISABLE 0x4
38#define CLKGATE_SEPERATED_STATUS 0x8
39
40struct clkgate_separated {
41 struct clk_hw hw;
42 void __iomem *enable; /* enable register */
43 u8 bit_idx; /* bits in enable/disable register */
44 u8 flags;
45 spinlock_t *lock;
46};
47
48static int clkgate_separated_enable(struct clk_hw *hw)
49{
50 struct clkgate_separated *sclk;
51 unsigned long flags = 0;
52 u32 reg;
53
54 sclk = container_of(hw, struct clkgate_separated, hw);
55 if (sclk->lock)
56 spin_lock_irqsave(sclk->lock, flags);
57 reg = BIT(sclk->bit_idx);
58 writel_relaxed(reg, sclk->enable);
59 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
60 if (sclk->lock)
61 spin_unlock_irqrestore(sclk->lock, flags);
62 return 0;
63}
64
65static void clkgate_separated_disable(struct clk_hw *hw)
66{
67 struct clkgate_separated *sclk;
68 unsigned long flags = 0;
69 u32 reg;
70
71 sclk = container_of(hw, struct clkgate_separated, hw);
72 if (sclk->lock)
73 spin_lock_irqsave(sclk->lock, flags);
74 reg = BIT(sclk->bit_idx);
75 writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
76 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
77 if (sclk->lock)
78 spin_unlock_irqrestore(sclk->lock, flags);
79}
80
81static int clkgate_separated_is_enabled(struct clk_hw *hw)
82{
83 struct clkgate_separated *sclk;
84 u32 reg;
85
86 sclk = container_of(hw, struct clkgate_separated, hw);
87 reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
88 reg &= BIT(sclk->bit_idx);
89
90 return reg ? 1 : 0;
91}
92
93static struct clk_ops clkgate_separated_ops = {
94 .enable = clkgate_separated_enable,
95 .disable = clkgate_separated_disable,
96 .is_enabled = clkgate_separated_is_enabled,
97};
98
99struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
100 const char *parent_name,
101 unsigned long flags,
102 void __iomem *reg, u8 bit_idx,
103 u8 clk_gate_flags, spinlock_t *lock)
104{
105 struct clkgate_separated *sclk;
106 struct clk *clk;
107 struct clk_init_data init;
108
109 sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
110 if (!sclk) {
111 pr_err("%s: fail to allocate separated gated clk\n", __func__);
112 return ERR_PTR(-ENOMEM);
113 }
114
115 init.name = name;
116 init.ops = &clkgate_separated_ops;
117 init.flags = flags | CLK_IS_BASIC;
118 init.parent_names = (parent_name ? &parent_name : NULL);
119 init.num_parents = (parent_name ? 1 : 0);
120
121 sclk->enable = reg + CLKGATE_SEPERATED_ENABLE;
122 sclk->bit_idx = bit_idx;
123 sclk->flags = clk_gate_flags;
124 sclk->hw.init = &init;
125
126 clk = clk_register(dev, &sclk->hw);
127 if (IS_ERR(clk))
128 kfree(sclk);
129 return clk;
130}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 01:20:40 -0400