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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-03-28 17:01:21 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-03-28 17:01:21 -0400
commitd0a9af809124c432297a7c4a3bcf98cbfdb4036a (patch)
treef11ed44faa2a4085d9bef84fc5eee89bc488dfd1 /drivers/char
parentc203b33d2ee34594f6656c033cddd4f5860eb06c (diff)
parenta71775147f6ae2a2901e7b917c0a76df353f8801 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [VIDEO]: Fix section mismatch in cg3.c [SPARC]: sparc64 gcc-4.2.0 20070317 -Werror failure [VIDEO] ffb: Fix two DAC handling bugs. [SPARC32]: Fix SMP build regression [DRM]: Delete sparc64 FFB driver code that never gets built.
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/drm/Makefile2
-rw-r--r--drivers/char/drm/ffb_context.c544
-rw-r--r--drivers/char/drm/ffb_drv.c355
-rw-r--r--drivers/char/drm/ffb_drv.h379
4 files changed, 0 insertions, 1280 deletions
diff --git a/drivers/char/drm/Makefile b/drivers/char/drm/Makefile
index 3ad0f648c6b2..6915a0599dfb 100644
--- a/drivers/char/drm/Makefile
+++ b/drivers/char/drm/Makefile
@@ -15,7 +15,6 @@ i810-objs := i810_drv.o i810_dma.o
15i830-objs := i830_drv.o i830_dma.o i830_irq.o 15i830-objs := i830_drv.o i830_dma.o i830_irq.o
16i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o 16i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o
17radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o 17radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
18ffb-objs := ffb_drv.o ffb_context.o
19sis-objs := sis_drv.o sis_mm.o 18sis-objs := sis_drv.o sis_mm.o
20savage-objs := savage_drv.o savage_bci.o savage_state.o 19savage-objs := savage_drv.o savage_bci.o savage_state.o
21via-objs := via_irq.o via_drv.o via_map.o via_mm.o via_dma.o via_verifier.o via_video.o via_dmablit.o 20via-objs := via_irq.o via_drv.o via_map.o via_mm.o via_dma.o via_verifier.o via_video.o via_dmablit.o
@@ -36,7 +35,6 @@ obj-$(CONFIG_DRM_MGA) += mga.o
36obj-$(CONFIG_DRM_I810) += i810.o 35obj-$(CONFIG_DRM_I810) += i810.o
37obj-$(CONFIG_DRM_I830) += i830.o 36obj-$(CONFIG_DRM_I830) += i830.o
38obj-$(CONFIG_DRM_I915) += i915.o 37obj-$(CONFIG_DRM_I915) += i915.o
39obj-$(CONFIG_DRM_FFB) += ffb.o
40obj-$(CONFIG_DRM_SIS) += sis.o 38obj-$(CONFIG_DRM_SIS) += sis.o
41obj-$(CONFIG_DRM_SAVAGE)+= savage.o 39obj-$(CONFIG_DRM_SAVAGE)+= savage.o
42obj-$(CONFIG_DRM_VIA) +=via.o 40obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/char/drm/ffb_context.c b/drivers/char/drm/ffb_context.c
deleted file mode 100644
index ac9ab40d57aa..000000000000
--- a/drivers/char/drm/ffb_context.c
+++ /dev/null
@@ -1,544 +0,0 @@
1/* $Id: ffb_context.c,v 1.5 2001/08/09 17:47:51 davem Exp $
2 * ffb_context.c: Creator/Creator3D DRI/DRM context switching.
3 *
4 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
5 *
6 * Almost entirely stolen from tdfx_context.c, see there
7 * for authors.
8 */
9
10#include <asm/upa.h>
11
12#include "ffb.h"
13#include "drmP.h"
14
15#include "ffb_drv.h"
16
17static int DRM(alloc_queue) (drm_device_t * dev, int is_2d_only) {
18 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
19 int i;
20
21 for (i = 0; i < FFB_MAX_CTXS; i++) {
22 if (fpriv->hw_state[i] == NULL)
23 break;
24 }
25 if (i == FFB_MAX_CTXS)
26 return -1;
27
28 fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL);
29 if (fpriv->hw_state[i] == NULL)
30 return -1;
31
32 fpriv->hw_state[i]->is_2d_only = is_2d_only;
33
34 /* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */
35 return i + 1;
36}
37
38static void ffb_save_context(ffb_dev_priv_t * fpriv, int idx)
39{
40 ffb_fbcPtr ffb = fpriv->regs;
41 struct ffb_hw_context *ctx;
42 int i;
43
44 ctx = fpriv->hw_state[idx - 1];
45 if (idx == 0 || ctx == NULL)
46 return;
47
48 if (ctx->is_2d_only) {
49 /* 2D applications only care about certain pieces
50 * of state.
51 */
52 ctx->drawop = upa_readl(&ffb->drawop);
53 ctx->ppc = upa_readl(&ffb->ppc);
54 ctx->wid = upa_readl(&ffb->wid);
55 ctx->fg = upa_readl(&ffb->fg);
56 ctx->bg = upa_readl(&ffb->bg);
57 ctx->xclip = upa_readl(&ffb->xclip);
58 ctx->fbc = upa_readl(&ffb->fbc);
59 ctx->rop = upa_readl(&ffb->rop);
60 ctx->cmp = upa_readl(&ffb->cmp);
61 ctx->matchab = upa_readl(&ffb->matchab);
62 ctx->magnab = upa_readl(&ffb->magnab);
63 ctx->pmask = upa_readl(&ffb->pmask);
64 ctx->xpmask = upa_readl(&ffb->xpmask);
65 ctx->lpat = upa_readl(&ffb->lpat);
66 ctx->fontxy = upa_readl(&ffb->fontxy);
67 ctx->fontw = upa_readl(&ffb->fontw);
68 ctx->fontinc = upa_readl(&ffb->fontinc);
69
70 /* stencil/stencilctl only exists on FFB2+ and later
71 * due to the introduction of 3DRAM-III.
72 */
73 if (fpriv->ffb_type == ffb2_vertical_plus ||
74 fpriv->ffb_type == ffb2_horizontal_plus) {
75 ctx->stencil = upa_readl(&ffb->stencil);
76 ctx->stencilctl = upa_readl(&ffb->stencilctl);
77 }
78
79 for (i = 0; i < 32; i++)
80 ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
81 ctx->ucsr = upa_readl(&ffb->ucsr);
82 return;
83 }
84
85 /* Fetch drawop. */
86 ctx->drawop = upa_readl(&ffb->drawop);
87
88 /* If we were saving the vertex registers, this is where
89 * we would do it. We would save 32 32-bit words starting
90 * at ffb->suvtx.
91 */
92
93 /* Capture rendering attributes. */
94
95 ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */
96 ctx->wid = upa_readl(&ffb->wid); /* Current WID */
97 ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */
98 ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */
99 ctx->consty = upa_readl(&ffb->consty); /* Constant Y */
100 ctx->constz = upa_readl(&ffb->constz); /* Constant Z */
101 ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */
102 ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */
103 ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */
104 ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */
105 ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */
106 ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */
107 ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */
108 ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */
109 ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */
110 ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */
111 ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */
112 ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */
113 ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */
114 ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */
115 ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */
116 ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */
117 ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */
118 ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */
119 ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */
120 ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */
121 ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */
122 ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */
123 ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */
124 ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */
125
126 /* Auxiliary Clips. */
127 ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min);
128 ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max);
129 ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min);
130 ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max);
131 ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min);
132 ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max);
133 ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min);
134 ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max);
135
136 ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */
137 ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */
138 ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */
139 ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */
140
141 /* These registers/features only exist on FFB2 and later chips. */
142 if (fpriv->ffb_type >= ffb2_prototype) {
143 ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */
144 ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */
145 ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */
146 ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */
147 ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */
148 ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */
149 ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */
150 ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */
151 ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */
152
153 /* And stencil/stencilctl only exists on FFB2+ and later
154 * due to the introduction of 3DRAM-III.
155 */
156 if (fpriv->ffb_type == ffb2_vertical_plus ||
157 fpriv->ffb_type == ffb2_horizontal_plus) {
158 ctx->stencil = upa_readl(&ffb->stencil);
159 ctx->stencilctl = upa_readl(&ffb->stencilctl);
160 }
161 }
162
163 /* Save the 32x32 area pattern. */
164 for (i = 0; i < 32; i++)
165 ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
166
167 /* Finally, stash away the User Constol/Status Register. */
168 ctx->ucsr = upa_readl(&ffb->ucsr);
169}
170
171static void ffb_restore_context(ffb_dev_priv_t * fpriv, int old, int idx)
172{
173 ffb_fbcPtr ffb = fpriv->regs;
174 struct ffb_hw_context *ctx;
175 int i;
176
177 ctx = fpriv->hw_state[idx - 1];
178 if (idx == 0 || ctx == NULL)
179 return;
180
181 if (ctx->is_2d_only) {
182 /* 2D applications only care about certain pieces
183 * of state.
184 */
185 upa_writel(ctx->drawop, &ffb->drawop);
186
187 /* If we were restoring the vertex registers, this is where
188 * we would do it. We would restore 32 32-bit words starting
189 * at ffb->suvtx.
190 */
191
192 upa_writel(ctx->ppc, &ffb->ppc);
193 upa_writel(ctx->wid, &ffb->wid);
194 upa_writel(ctx->fg, &ffb->fg);
195 upa_writel(ctx->bg, &ffb->bg);
196 upa_writel(ctx->xclip, &ffb->xclip);
197 upa_writel(ctx->fbc, &ffb->fbc);
198 upa_writel(ctx->rop, &ffb->rop);
199 upa_writel(ctx->cmp, &ffb->cmp);
200 upa_writel(ctx->matchab, &ffb->matchab);
201 upa_writel(ctx->magnab, &ffb->magnab);
202 upa_writel(ctx->pmask, &ffb->pmask);
203 upa_writel(ctx->xpmask, &ffb->xpmask);
204 upa_writel(ctx->lpat, &ffb->lpat);
205 upa_writel(ctx->fontxy, &ffb->fontxy);
206 upa_writel(ctx->fontw, &ffb->fontw);
207 upa_writel(ctx->fontinc, &ffb->fontinc);
208
209 /* stencil/stencilctl only exists on FFB2+ and later
210 * due to the introduction of 3DRAM-III.
211 */
212 if (fpriv->ffb_type == ffb2_vertical_plus ||
213 fpriv->ffb_type == ffb2_horizontal_plus) {
214 upa_writel(ctx->stencil, &ffb->stencil);
215 upa_writel(ctx->stencilctl, &ffb->stencilctl);
216 upa_writel(0x80000000, &ffb->fbc);
217 upa_writel((ctx->stencilctl | 0x80000),
218 &ffb->rawstencilctl);
219 upa_writel(ctx->fbc, &ffb->fbc);
220 }
221
222 for (i = 0; i < 32; i++)
223 upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
224 upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
225 return;
226 }
227
228 /* Restore drawop. */
229 upa_writel(ctx->drawop, &ffb->drawop);
230
231 /* If we were restoring the vertex registers, this is where
232 * we would do it. We would restore 32 32-bit words starting
233 * at ffb->suvtx.
234 */
235
236 /* Restore rendering attributes. */
237
238 upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */
239 upa_writel(ctx->wid, &ffb->wid); /* Current WID */
240 upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */
241 upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */
242 upa_writel(ctx->consty, &ffb->consty); /* Constant Y */
243 upa_writel(ctx->constz, &ffb->constz); /* Constant Z */
244 upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */
245 upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */
246 upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */
247 upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */
248 upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */
249 upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */
250 upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */
251 upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */
252 upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */
253 upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */
254 upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */
255 upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */
256 upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */
257 upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */
258 upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */
259 upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */
260 upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */
261 upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */
262 upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */
263 upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */
264 upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */
265 upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */
266 upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */
267 upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */
268
269 /* Auxiliary Clips. */
270 upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min);
271 upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max);
272 upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min);
273 upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max);
274 upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min);
275 upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max);
276 upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min);
277 upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max);
278
279 upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */
280 upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */
281 upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */
282 upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */
283
284 /* These registers/features only exist on FFB2 and later chips. */
285 if (fpriv->ffb_type >= ffb2_prototype) {
286 upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */
287 upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */
288 upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */
289 upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */
290 upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */
291 upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */
292 upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */
293 upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */
294 upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */
295
296 /* And stencil/stencilctl only exists on FFB2+ and later
297 * due to the introduction of 3DRAM-III.
298 */
299 if (fpriv->ffb_type == ffb2_vertical_plus ||
300 fpriv->ffb_type == ffb2_horizontal_plus) {
301 /* Unfortunately, there is a hardware bug on
302 * the FFB2+ chips which prevents a normal write
303 * to the stencil control register from working
304 * as it should.
305 *
306 * The state controlled by the FFB stencilctl register
307 * really gets transferred to the per-buffer instances
308 * of the stencilctl register in the 3DRAM chips.
309 *
310 * The bug is that FFB does not update buffer C correctly,
311 * so we have to do it by hand for them.
312 */
313
314 /* This will update buffers A and B. */
315 upa_writel(ctx->stencil, &ffb->stencil);
316 upa_writel(ctx->stencilctl, &ffb->stencilctl);
317
318 /* Force FFB to use buffer C 3dram regs. */
319 upa_writel(0x80000000, &ffb->fbc);
320 upa_writel((ctx->stencilctl | 0x80000),
321 &ffb->rawstencilctl);
322
323 /* Now restore the correct FBC controls. */
324 upa_writel(ctx->fbc, &ffb->fbc);
325 }
326 }
327
328 /* Restore the 32x32 area pattern. */
329 for (i = 0; i < 32; i++)
330 upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
331
332 /* Finally, stash away the User Constol/Status Register.
333 * The only state we really preserve here is the picking
334 * control.
335 */
336 upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
337}
338
339#define FFB_UCSR_FB_BUSY 0x01000000
340#define FFB_UCSR_RP_BUSY 0x02000000
341#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
342
343static void FFBWait(ffb_fbcPtr ffb)
344{
345 int limit = 100000;
346
347 do {
348 u32 regval = upa_readl(&ffb->ucsr);
349
350 if ((regval & FFB_UCSR_ALL_BUSY) == 0)
351 break;
352 } while (--limit);
353}
354
355int ffb_driver_context_switch(drm_device_t * dev, int old, int new)
356{
357 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
358
359#ifdef DRM_DMA_HISTOGRAM
360 dev->ctx_start = get_cycles();
361#endif
362
363 DRM_DEBUG("Context switch from %d to %d\n", old, new);
364
365 if (new == dev->last_context || dev->last_context == 0) {
366 dev->last_context = new;
367 return 0;
368 }
369
370 FFBWait(fpriv->regs);
371 ffb_save_context(fpriv, old);
372 ffb_restore_context(fpriv, old, new);
373 FFBWait(fpriv->regs);
374
375 dev->last_context = new;
376
377 return 0;
378}
379
380int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
381 unsigned long arg)
382{
383 drm_ctx_res_t res;
384 drm_ctx_t ctx;
385 int i;
386
387 DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
388 if (copy_from_user(&res, (drm_ctx_res_t __user *) arg, sizeof(res)))
389 return -EFAULT;
390 if (res.count >= DRM_RESERVED_CONTEXTS) {
391 memset(&ctx, 0, sizeof(ctx));
392 for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
393 ctx.handle = i;
394 if (copy_to_user(&res.contexts[i], &i, sizeof(i)))
395 return -EFAULT;
396 }
397 }
398 res.count = DRM_RESERVED_CONTEXTS;
399 if (copy_to_user((drm_ctx_res_t __user *) arg, &res, sizeof(res)))
400 return -EFAULT;
401 return 0;
402}
403
404int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
405 unsigned long arg)
406{
407 drm_file_t *priv = filp->private_data;
408 drm_device_t *dev = priv->dev;
409 drm_ctx_t ctx;
410 int idx;
411
412 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
413 return -EFAULT;
414 idx = DRM(alloc_queue) (dev, (ctx.flags & _DRM_CONTEXT_2DONLY));
415 if (idx < 0)
416 return -ENFILE;
417
418 DRM_DEBUG("%d\n", ctx.handle);
419 ctx.handle = idx;
420 if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx)))
421 return -EFAULT;
422 return 0;
423}
424
425int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
426 unsigned long arg)
427{
428 drm_file_t *priv = filp->private_data;
429 drm_device_t *dev = priv->dev;
430 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
431 struct ffb_hw_context *hwctx;
432 drm_ctx_t ctx;
433 int idx;
434
435 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
436 return -EFAULT;
437
438 idx = ctx.handle;
439 if (idx <= 0 || idx >= FFB_MAX_CTXS)
440 return -EINVAL;
441
442 hwctx = fpriv->hw_state[idx - 1];
443 if (hwctx == NULL)
444 return -EINVAL;
445
446 if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0)
447 hwctx->is_2d_only = 0;
448 else
449 hwctx->is_2d_only = 1;
450
451 return 0;
452}
453
454int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
455 unsigned long arg)
456{
457 drm_file_t *priv = filp->private_data;
458 drm_device_t *dev = priv->dev;
459 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
460 struct ffb_hw_context *hwctx;
461 drm_ctx_t ctx;
462 int idx;
463
464 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
465 return -EFAULT;
466
467 idx = ctx.handle;
468 if (idx <= 0 || idx >= FFB_MAX_CTXS)
469 return -EINVAL;
470
471 hwctx = fpriv->hw_state[idx - 1];
472 if (hwctx == NULL)
473 return -EINVAL;
474
475 if (hwctx->is_2d_only != 0)
476 ctx.flags = _DRM_CONTEXT_2DONLY;
477 else
478 ctx.flags = 0;
479
480 if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx)))
481 return -EFAULT;
482
483 return 0;
484}
485
486int ffb_driver_switchctx(struct inode *inode, struct file *filp,
487 unsigned int cmd, unsigned long arg)
488{
489 drm_file_t *priv = filp->private_data;
490 drm_device_t *dev = priv->dev;
491 drm_ctx_t ctx;
492
493 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
494 return -EFAULT;
495 DRM_DEBUG("%d\n", ctx.handle);
496 return ffb_driver_context_switch(dev, dev->last_context, ctx.handle);
497}
498
499int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
500 unsigned long arg)
501{
502 drm_ctx_t ctx;
503
504 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
505 return -EFAULT;
506 DRM_DEBUG("%d\n", ctx.handle);
507
508 return 0;
509}
510
511int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
512 unsigned long arg)
513{
514 drm_ctx_t ctx;
515 drm_file_t *priv = filp->private_data;
516 drm_device_t *dev = priv->dev;
517 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
518 int idx;
519
520 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
521 return -EFAULT;
522 DRM_DEBUG("%d\n", ctx.handle);
523
524 idx = ctx.handle - 1;
525 if (idx < 0 || idx >= FFB_MAX_CTXS)
526 return -EINVAL;
527
528 kfree(fpriv->hw_state[idx]);
529 fpriv->hw_state[idx] = NULL;
530 return 0;
531}
532
533void ffb_set_context_ioctls(void)
534{
535 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)].func = ffb_driver_addctx;
536 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx;
537 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx;
538 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx;
539 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func =
540 ffb_driver_switchctx;
541 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx;
542 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx;
543
544}
diff --git a/drivers/char/drm/ffb_drv.c b/drivers/char/drm/ffb_drv.c
deleted file mode 100644
index 9a19879e3b68..000000000000
--- a/drivers/char/drm/ffb_drv.c
+++ /dev/null
@@ -1,355 +0,0 @@
1/* $Id: ffb_drv.c,v 1.16 2001/10/18 16:00:24 davem Exp $
2 * ffb_drv.c: Creator/Creator3D direct rendering driver.
3 *
4 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
5 */
6
7#include "ffb.h"
8#include "drmP.h"
9
10#include "ffb_drv.h"
11
12#include <linux/smp_lock.h>
13#include <asm/shmparam.h>
14#include <asm/oplib.h>
15#include <asm/upa.h>
16
17#define DRIVER_AUTHOR "David S. Miller"
18
19#define DRIVER_NAME "ffb"
20#define DRIVER_DESC "Creator/Creator3D"
21#define DRIVER_DATE "20000517"
22
23#define DRIVER_MAJOR 0
24#define DRIVER_MINOR 0
25#define DRIVER_PATCHLEVEL 1
26
27typedef struct _ffb_position_t {
28 int node;
29 int root;
30} ffb_position_t;
31
32static ffb_position_t *ffb_position;
33
34static void get_ffb_type(ffb_dev_priv_t * ffb_priv, int instance)
35{
36 volatile unsigned char *strap_bits;
37 unsigned char val;
38
39 strap_bits = (volatile unsigned char *)
40 (ffb_priv->card_phys_base + 0x00200000UL);
41
42 /* Don't ask, you have to read the value twice for whatever
43 * reason to get correct contents.
44 */
45 val = upa_readb(strap_bits);
46 val = upa_readb(strap_bits);
47 switch (val & 0x78) {
48 case (0x0 << 5) | (0x0 << 3):
49 ffb_priv->ffb_type = ffb1_prototype;
50 printk("ffb%d: Detected FFB1 pre-FCS prototype\n", instance);
51 break;
52 case (0x0 << 5) | (0x1 << 3):
53 ffb_priv->ffb_type = ffb1_standard;
54 printk("ffb%d: Detected FFB1\n", instance);
55 break;
56 case (0x0 << 5) | (0x3 << 3):
57 ffb_priv->ffb_type = ffb1_speedsort;
58 printk("ffb%d: Detected FFB1-SpeedSort\n", instance);
59 break;
60 case (0x1 << 5) | (0x0 << 3):
61 ffb_priv->ffb_type = ffb2_prototype;
62 printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n",
63 instance);
64 break;
65 case (0x1 << 5) | (0x1 << 3):
66 ffb_priv->ffb_type = ffb2_vertical;
67 printk("ffb%d: Detected FFB2/vertical\n", instance);
68 break;
69 case (0x1 << 5) | (0x2 << 3):
70 ffb_priv->ffb_type = ffb2_vertical_plus;
71 printk("ffb%d: Detected FFB2+/vertical\n", instance);
72 break;
73 case (0x2 << 5) | (0x0 << 3):
74 ffb_priv->ffb_type = ffb2_horizontal;
75 printk("ffb%d: Detected FFB2/horizontal\n", instance);
76 break;
77 case (0x2 << 5) | (0x2 << 3):
78 ffb_priv->ffb_type = ffb2_horizontal;
79 printk("ffb%d: Detected FFB2+/horizontal\n", instance);
80 break;
81 default:
82 ffb_priv->ffb_type = ffb2_vertical;
83 printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n",
84 instance, val);
85 break;
86 };
87}
88
89static void ffb_apply_upa_parent_ranges(int parent,
90 struct linux_prom64_registers *regs)
91{
92 struct linux_prom64_ranges ranges[PROMREG_MAX];
93 char name[128];
94 int len, i;
95
96 prom_getproperty(parent, "name", name, sizeof(name));
97 if (strcmp(name, "upa") != 0)
98 return;
99
100 len =
101 prom_getproperty(parent, "ranges", (void *)ranges, sizeof(ranges));
102 if (len <= 0)
103 return;
104
105 len /= sizeof(struct linux_prom64_ranges);
106 for (i = 0; i < len; i++) {
107 struct linux_prom64_ranges *rng = &ranges[i];
108 u64 phys_addr = regs->phys_addr;
109
110 if (phys_addr >= rng->ot_child_base &&
111 phys_addr < (rng->ot_child_base + rng->or_size)) {
112 regs->phys_addr -= rng->ot_child_base;
113 regs->phys_addr += rng->ot_parent_base;
114 return;
115 }
116 }
117
118 return;
119}
120
121static int ffb_init_one(drm_device_t * dev, int prom_node, int parent_node,
122 int instance)
123{
124 struct linux_prom64_registers regs[2 * PROMREG_MAX];
125 ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private;
126 int i;
127
128 ffb_priv->prom_node = prom_node;
129 if (prom_getproperty(ffb_priv->prom_node, "reg",
130 (void *)regs, sizeof(regs)) <= 0) {
131 return -EINVAL;
132 }
133 ffb_apply_upa_parent_ranges(parent_node, &regs[0]);
134 ffb_priv->card_phys_base = regs[0].phys_addr;
135 ffb_priv->regs = (ffb_fbcPtr)
136 (regs[0].phys_addr + 0x00600000UL);
137 get_ffb_type(ffb_priv, instance);
138 for (i = 0; i < FFB_MAX_CTXS; i++)
139 ffb_priv->hw_state[i] = NULL;
140
141 return 0;
142}
143
144static drm_map_t *ffb_find_map(struct file *filp, unsigned long off)
145{
146 drm_file_t *priv = filp->private_data;
147 drm_device_t *dev;
148 drm_map_list_t *r_list;
149 struct list_head *list;
150 drm_map_t *map;
151
152 if (!priv || (dev = priv->dev) == NULL)
153 return NULL;
154
155 list_for_each(list, &dev->maplist->head) {
156 r_list = (drm_map_list_t *) list;
157 map = r_list->map;
158 if (!map)
159 continue;
160 if (r_list->user_token == off)
161 return map;
162 }
163
164 return NULL;
165}
166
167unsigned long ffb_get_unmapped_area(struct file *filp,
168 unsigned long hint,
169 unsigned long len,
170 unsigned long pgoff, unsigned long flags)
171{
172 drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT);
173 unsigned long addr = -ENOMEM;
174
175 if (!map)
176 return get_unmapped_area(NULL, hint, len, pgoff, flags);
177
178 if (map->type == _DRM_FRAME_BUFFER || map->type == _DRM_REGISTERS) {
179#ifdef HAVE_ARCH_FB_UNMAPPED_AREA
180 addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags);
181#else
182 addr = get_unmapped_area(NULL, hint, len, pgoff, flags);
183#endif
184 } else if (map->type == _DRM_SHM && SHMLBA > PAGE_SIZE) {
185 unsigned long slack = SHMLBA - PAGE_SIZE;
186
187 addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags);
188 if (!(addr & ~PAGE_MASK)) {
189 unsigned long kvirt = (unsigned long)map->handle;
190
191 if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
192 unsigned long koff, aoff;
193
194 koff = kvirt & (SHMLBA - 1);
195 aoff = addr & (SHMLBA - 1);
196 if (koff < aoff)
197 koff += SHMLBA;
198
199 addr += (koff - aoff);
200 }
201 }
202 } else {
203 addr = get_unmapped_area(NULL, hint, len, pgoff, flags);
204 }
205
206 return addr;
207}
208
209static int ffb_presetup(drm_device_t * dev)
210{
211 ffb_dev_priv_t *ffb_priv;
212 int ret = 0;
213 int i = 0;
214
215 /* Check for the case where no device was found. */
216 if (ffb_position == NULL)
217 return -ENODEV;
218
219 /* code used to use numdevs no numdevs anymore */
220 ffb_priv = kmalloc(sizeof(ffb_dev_priv_t), GFP_KERNEL);
221 if (!ffb_priv)
222 return -ENOMEM;
223 memset(ffb_priv, 0, sizeof(*ffb_priv));
224 dev->dev_private = ffb_priv;
225
226 ret = ffb_init_one(dev, ffb_position[i].node, ffb_position[i].root, i);
227 return ret;
228}
229
230static void ffb_driver_release(drm_device_t * dev, struct file *filp)
231{
232 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
233 int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock);
234 int idx;
235
236 idx = context - 1;
237 if (fpriv &&
238 context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) {
239 kfree(fpriv->hw_state[idx]);
240 fpriv->hw_state[idx] = NULL;
241 }
242}
243
244static void ffb_driver_pretakedown(drm_device_t * dev)
245{
246 kfree(dev->dev_private);
247}
248
249static int ffb_driver_postcleanup(drm_device_t * dev)
250{
251 kfree(ffb_position);
252 return 0;
253}
254
255static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev,
256 drm_lock_t * lock)
257{
258 dev->lock.filp = 0;
259 {
260 __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock;
261 unsigned int old, new, prev, ctx;
262
263 ctx = lock->context;
264 do {
265 old = *plock;
266 new = ctx;
267 prev = cmpxchg(plock, old, new);
268 } while (prev != old);
269 }
270 wake_up_interruptible(&dev->lock.lock_queue);
271}
272
273static unsigned long ffb_driver_get_map_ofs(drm_map_t * map)
274{
275 return (map->offset & 0xffffffff);
276}
277
278static unsigned long ffb_driver_get_reg_ofs(drm_device_t * dev)
279{
280 ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private;
281
282 if (ffb_priv)
283 return ffb_priv->card_phys_base;
284
285 return 0;
286}
287
288static int postinit(struct drm_device *dev, unsigned long flags)
289{
290 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
291 DRIVER_NAME,
292 DRIVER_MAJOR,
293 DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE, dev->minor);
294 return 0;
295}
296
297static int version(drm_version_t * version)
298{
299 int len;
300
301 version->version_major = DRIVER_MAJOR;
302 version->version_minor = DRIVER_MINOR;
303 version->version_patchlevel = DRIVER_PATCHLEVEL;
304 DRM_COPY(version->name, DRIVER_NAME);
305 DRM_COPY(version->date, DRIVER_DATE);
306 DRM_COPY(version->desc, DRIVER_DESC);
307 return 0;
308}
309
310static drm_ioctl_desc_t ioctls[] = {
311
312};
313
314static struct drm_driver driver = {
315 .driver_features = 0,
316 .dev_priv_size = sizeof(u32),
317 .release = ffb_driver_release,
318 .presetup = ffb_presetup,
319 .pretakedown = ffb_driver_pretakedown,
320 .postcleanup = ffb_driver_postcleanup,
321 .kernel_context_switch = ffb_driver_context_switch,
322 .kernel_context_switch_unlock = ffb_driver_kernel_context_switch_unlock,
323 .get_map_ofs = ffb_driver_get_map_ofs,
324 .get_reg_ofs = ffb_driver_get_reg_ofs,
325 .postinit = postinit,
326 .version = version,
327 .ioctls = ioctls,
328 .num_ioctls = DRM_ARRAY_SIZE(ioctls),
329 .fops = {
330 .owner = THIS_MODULE,
331 .open = drm_open,
332 .release = drm_release,
333 .ioctl = drm_ioctl,
334 .mmap = drm_mmap,
335 .poll = drm_poll,
336 .fasync = drm_fasync,
337 }
338 ,
339};
340
341static int __init ffb_init(void)
342{
343 return -ENODEV;
344}
345
346static void __exit ffb_exit(void)
347{
348}
349
350module_init(ffb_init);
351module_exit(ffb_exit);
352
353MODULE_AUTHOR(DRIVER_AUTHOR);
354MODULE_DESCRIPTION(DRIVER_DESC);
355MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/ffb_drv.h b/drivers/char/drm/ffb_drv.h
deleted file mode 100644
index 582afa6dd2b4..000000000000
--- a/drivers/char/drm/ffb_drv.h
+++ /dev/null
@@ -1,379 +0,0 @@
1/* $Id: ffb_drv.h,v 1.1 2000/06/01 04:24:39 davem Exp $
2 * ffb_drv.h: Creator/Creator3D direct rendering driver.
3 *
4 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
5 */
6
7/* Auxilliary clips. */
8typedef struct {
9 volatile unsigned int min;
10 volatile unsigned int max;
11} ffb_auxclip, *ffb_auxclipPtr;
12
13/* FFB register set. */
14typedef struct _ffb_fbc {
15 /* Next vertex registers, on the right we list which drawops
16 * use said register and the logical name the register has in
17 * that context.
18 *//* DESCRIPTION DRAWOP(NAME) */
19 /*0x00*/ unsigned int pad1[3];
20 /* Reserved */
21 /*0x0c*/ volatile unsigned int alpha;
22 /* ALPHA Transparency */
23 /*0x10*/ volatile unsigned int red;
24 /* RED */
25 /*0x14*/ volatile unsigned int green;
26 /* GREEN */
27 /*0x18*/ volatile unsigned int blue;
28 /* BLUE */
29 /*0x1c*/ volatile unsigned int z;
30 /* DEPTH */
31 /*0x20*/ volatile unsigned int y;
32 /* Y triangle(DOYF) */
33 /* aadot(DYF) */
34 /* ddline(DYF) */
35 /* aaline(DYF) */
36 /*0x24*/ volatile unsigned int x;
37 /* X triangle(DOXF) */
38 /* aadot(DXF) */
39 /* ddline(DXF) */
40 /* aaline(DXF) */
41 /*0x28*/ unsigned int pad2[2];
42 /* Reserved */
43 /*0x30*/ volatile unsigned int ryf;
44 /* Y (alias to DOYF) ddline(RYF) */
45 /* aaline(RYF) */
46 /* triangle(RYF) */
47 /*0x34*/ volatile unsigned int rxf;
48 /* X ddline(RXF) */
49 /* aaline(RXF) */
50 /* triangle(RXF) */
51 /*0x38*/ unsigned int pad3[2];
52 /* Reserved */
53 /*0x40*/ volatile unsigned int dmyf;
54 /* Y (alias to DOYF) triangle(DMYF) */
55 /*0x44*/ volatile unsigned int dmxf;
56 /* X triangle(DMXF) */
57 /*0x48*/ unsigned int pad4[2];
58 /* Reserved */
59 /*0x50*/ volatile unsigned int ebyi;
60 /* Y (alias to RYI) polygon(EBYI) */
61 /*0x54*/ volatile unsigned int ebxi;
62 /* X polygon(EBXI) */
63 /*0x58*/ unsigned int pad5[2];
64 /* Reserved */
65 /*0x60*/ volatile unsigned int by;
66 /* Y brline(RYI) */
67 /* fastfill(OP) */
68 /* polygon(YI) */
69 /* rectangle(YI) */
70 /* bcopy(SRCY) */
71 /* vscroll(SRCY) */
72 /*0x64*/ volatile unsigned int bx;
73 /* X brline(RXI) */
74 /* polygon(XI) */
75 /* rectangle(XI) */
76 /* bcopy(SRCX) */
77 /* vscroll(SRCX) */
78 /* fastfill(GO) */
79 /*0x68*/ volatile unsigned int dy;
80 /* destination Y fastfill(DSTY) */
81 /* bcopy(DSRY) */
82 /* vscroll(DSRY) */
83 /*0x6c*/ volatile unsigned int dx;
84 /* destination X fastfill(DSTX) */
85 /* bcopy(DSTX) */
86 /* vscroll(DSTX) */
87 /*0x70*/ volatile unsigned int bh;
88 /* Y (alias to RYI) brline(DYI) */
89 /* dot(DYI) */
90 /* polygon(ETYI) */
91 /* Height fastfill(H) */
92 /* bcopy(H) */
93 /* vscroll(H) */
94 /* Y count fastfill(NY) */
95 /*0x74*/ volatile unsigned int bw;
96 /* X dot(DXI) */
97 /* brline(DXI) */
98 /* polygon(ETXI) */
99 /* fastfill(W) */
100 /* bcopy(W) */
101 /* vscroll(W) */
102 /* fastfill(NX) */
103 /*0x78*/ unsigned int pad6[2];
104 /* Reserved */
105 /*0x80*/ unsigned int pad7[32];
106 /* Reserved */
107
108 /* Setup Unit's vertex state register */
109/*100*/ volatile unsigned int suvtx;
110 /*104*/ unsigned int pad8[63];
111 /* Reserved */
112
113 /* Frame Buffer Control Registers */
114 /*200*/ volatile unsigned int ppc;
115 /* Pixel Processor Control */
116 /*204*/ volatile unsigned int wid;
117 /* Current WID */
118 /*208*/ volatile unsigned int fg;
119 /* FG data */
120 /*20c*/ volatile unsigned int bg;
121 /* BG data */
122 /*210*/ volatile unsigned int consty;
123 /* Constant Y */
124 /*214*/ volatile unsigned int constz;
125 /* Constant Z */
126 /*218*/ volatile unsigned int xclip;
127 /* X Clip */
128 /*21c*/ volatile unsigned int dcss;
129 /* Depth Cue Scale Slope */
130 /*220*/ volatile unsigned int vclipmin;
131 /* Viewclip XY Min Bounds */
132 /*224*/ volatile unsigned int vclipmax;
133 /* Viewclip XY Max Bounds */
134 /*228*/ volatile unsigned int vclipzmin;
135 /* Viewclip Z Min Bounds */
136 /*22c*/ volatile unsigned int vclipzmax;
137 /* Viewclip Z Max Bounds */
138 /*230*/ volatile unsigned int dcsf;
139 /* Depth Cue Scale Front Bound */
140 /*234*/ volatile unsigned int dcsb;
141 /* Depth Cue Scale Back Bound */
142 /*238*/ volatile unsigned int dczf;
143 /* Depth Cue Z Front */
144 /*23c*/ volatile unsigned int dczb;
145 /* Depth Cue Z Back */
146 /*240*/ unsigned int pad9;
147 /* Reserved */
148 /*244*/ volatile unsigned int blendc;
149 /* Alpha Blend Control */
150 /*248*/ volatile unsigned int blendc1;
151 /* Alpha Blend Color 1 */
152 /*24c*/ volatile unsigned int blendc2;
153 /* Alpha Blend Color 2 */
154 /*250*/ volatile unsigned int fbramitc;
155 /* FB RAM Interleave Test Control */
156 /*254*/ volatile unsigned int fbc;
157 /* Frame Buffer Control */
158 /*258*/ volatile unsigned int rop;
159 /* Raster OPeration */
160 /*25c*/ volatile unsigned int cmp;
161 /* Frame Buffer Compare */
162 /*260*/ volatile unsigned int matchab;
163 /* Buffer AB Match Mask */
164 /*264*/ volatile unsigned int matchc;
165 /* Buffer C(YZ) Match Mask */
166 /*268*/ volatile unsigned int magnab;
167 /* Buffer AB Magnitude Mask */
168 /*26c*/ volatile unsigned int magnc;
169 /* Buffer C(YZ) Magnitude Mask */
170 /*270*/ volatile unsigned int fbcfg0;
171 /* Frame Buffer Config 0 */
172 /*274*/ volatile unsigned int fbcfg1;
173 /* Frame Buffer Config 1 */
174 /*278*/ volatile unsigned int fbcfg2;
175 /* Frame Buffer Config 2 */
176 /*27c*/ volatile unsigned int fbcfg3;
177 /* Frame Buffer Config 3 */
178 /*280*/ volatile unsigned int ppcfg;
179 /* Pixel Processor Config */
180 /*284*/ volatile unsigned int pick;
181 /* Picking Control */
182 /*288*/ volatile unsigned int fillmode;
183 /* FillMode */
184 /*28c*/ volatile unsigned int fbramwac;
185 /* FB RAM Write Address Control */
186 /*290*/ volatile unsigned int pmask;
187 /* RGB PlaneMask */
188 /*294*/ volatile unsigned int xpmask;
189 /* X PlaneMask */
190 /*298*/ volatile unsigned int ypmask;
191 /* Y PlaneMask */
192 /*29c*/ volatile unsigned int zpmask;
193 /* Z PlaneMask */
194 /*2a0*/ ffb_auxclip auxclip[4];
195 /* Auxilliary Viewport Clip */
196
197 /* New 3dRAM III support regs */
198/*2c0*/ volatile unsigned int rawblend2;
199/*2c4*/ volatile unsigned int rawpreblend;
200/*2c8*/ volatile unsigned int rawstencil;
201/*2cc*/ volatile unsigned int rawstencilctl;
202/*2d0*/ volatile unsigned int threedram1;
203/*2d4*/ volatile unsigned int threedram2;
204/*2d8*/ volatile unsigned int passin;
205/*2dc*/ volatile unsigned int rawclrdepth;
206/*2e0*/ volatile unsigned int rawpmask;
207/*2e4*/ volatile unsigned int rawcsrc;
208/*2e8*/ volatile unsigned int rawmatch;
209/*2ec*/ volatile unsigned int rawmagn;
210/*2f0*/ volatile unsigned int rawropblend;
211/*2f4*/ volatile unsigned int rawcmp;
212/*2f8*/ volatile unsigned int rawwac;
213/*2fc*/ volatile unsigned int fbramid;
214
215 /*300*/ volatile unsigned int drawop;
216 /* Draw OPeration */
217 /*304*/ unsigned int pad10[2];
218 /* Reserved */
219 /*30c*/ volatile unsigned int lpat;
220 /* Line Pattern control */
221 /*310*/ unsigned int pad11;
222 /* Reserved */
223 /*314*/ volatile unsigned int fontxy;
224 /* XY Font coordinate */
225 /*318*/ volatile unsigned int fontw;
226 /* Font Width */
227 /*31c*/ volatile unsigned int fontinc;
228 /* Font Increment */
229 /*320*/ volatile unsigned int font;
230 /* Font bits */
231 /*324*/ unsigned int pad12[3];
232 /* Reserved */
233/*330*/ volatile unsigned int blend2;
234/*334*/ volatile unsigned int preblend;
235/*338*/ volatile unsigned int stencil;
236/*33c*/ volatile unsigned int stencilctl;
237
238 /*340*/ unsigned int pad13[4];
239 /* Reserved */
240 /*350*/ volatile unsigned int dcss1;
241 /* Depth Cue Scale Slope 1 */
242 /*354*/ volatile unsigned int dcss2;
243 /* Depth Cue Scale Slope 2 */
244 /*358*/ volatile unsigned int dcss3;
245 /* Depth Cue Scale Slope 3 */
246/*35c*/ volatile unsigned int widpmask;
247/*360*/ volatile unsigned int dcs2;
248/*364*/ volatile unsigned int dcs3;
249/*368*/ volatile unsigned int dcs4;
250 /*36c*/ unsigned int pad14;
251 /* Reserved */
252/*370*/ volatile unsigned int dcd2;
253/*374*/ volatile unsigned int dcd3;
254/*378*/ volatile unsigned int dcd4;
255 /*37c*/ unsigned int pad15;
256 /* Reserved */
257 /*380*/ volatile unsigned int pattern[32];
258 /* area Pattern */
259 /*400*/ unsigned int pad16[8];
260 /* Reserved */
261 /*420*/ volatile unsigned int reset;
262 /* chip RESET */
263 /*424*/ unsigned int pad17[247];
264 /* Reserved */
265 /*800*/ volatile unsigned int devid;
266 /* Device ID */
267 /*804*/ unsigned int pad18[63];
268 /* Reserved */
269 /*900*/ volatile unsigned int ucsr;
270 /* User Control & Status Register */
271 /*904*/ unsigned int pad19[31];
272 /* Reserved */
273 /*980*/ volatile unsigned int mer;
274 /* Mode Enable Register */
275 /*984*/ unsigned int pad20[1439];
276 /* Reserved */
277} ffb_fbc, *ffb_fbcPtr;
278
279struct ffb_hw_context {
280 int is_2d_only;
281
282 unsigned int ppc;
283 unsigned int wid;
284 unsigned int fg;
285 unsigned int bg;
286 unsigned int consty;
287 unsigned int constz;
288 unsigned int xclip;
289 unsigned int dcss;
290 unsigned int vclipmin;
291 unsigned int vclipmax;
292 unsigned int vclipzmin;
293 unsigned int vclipzmax;
294 unsigned int dcsf;
295 unsigned int dcsb;
296 unsigned int dczf;
297 unsigned int dczb;
298 unsigned int blendc;
299 unsigned int blendc1;
300 unsigned int blendc2;
301 unsigned int fbc;
302 unsigned int rop;
303 unsigned int cmp;
304 unsigned int matchab;
305 unsigned int matchc;
306 unsigned int magnab;
307 unsigned int magnc;
308 unsigned int pmask;
309 unsigned int xpmask;
310 unsigned int ypmask;
311 unsigned int zpmask;
312 unsigned int auxclip0min;
313 unsigned int auxclip0max;
314 unsigned int auxclip1min;
315 unsigned int auxclip1max;
316 unsigned int auxclip2min;
317 unsigned int auxclip2max;
318 unsigned int auxclip3min;
319 unsigned int auxclip3max;
320 unsigned int drawop;
321 unsigned int lpat;
322 unsigned int fontxy;
323 unsigned int fontw;
324 unsigned int fontinc;
325 unsigned int area_pattern[32];
326 unsigned int ucsr;
327 unsigned int stencil;
328 unsigned int stencilctl;
329 unsigned int dcss1;
330 unsigned int dcss2;
331 unsigned int dcss3;
332 unsigned int dcs2;
333 unsigned int dcs3;
334 unsigned int dcs4;
335 unsigned int dcd2;
336 unsigned int dcd3;
337 unsigned int dcd4;
338 unsigned int mer;
339};
340
341#define FFB_MAX_CTXS 32
342
343enum ffb_chip_type {
344 ffb1_prototype = 0, /* Early pre-FCS FFB */
345 ffb1_standard, /* First FCS FFB, 100Mhz UPA, 66MHz gclk */
346 ffb1_speedsort, /* Second FCS FFB, 100Mhz UPA, 75MHz gclk */
347 ffb2_prototype, /* Early pre-FCS vertical FFB2 */
348 ffb2_vertical, /* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk,
349 75(SingleBuffer)/83(DoubleBuffer) MHz fclk */
350 ffb2_vertical_plus, /* Second FCS FFB2/vertical, same timings */
351 ffb2_horizontal, /* First FCS FFB2/horizontal, same timings as FFB2/vert */
352 ffb2_horizontal_plus, /* Second FCS FFB2/horizontal, same timings */
353 afb_m3, /* FCS Elite3D, 3 float chips */
354 afb_m6 /* FCS Elite3D, 6 float chips */
355};
356
357typedef struct ffb_dev_priv {
358 /* Misc software state. */
359 int prom_node;
360 enum ffb_chip_type ffb_type;
361 u64 card_phys_base;
362 struct miscdevice miscdev;
363
364 /* Controller registers. */
365 ffb_fbcPtr regs;
366
367 /* Context table. */
368 struct ffb_hw_context *hw_state[FFB_MAX_CTXS];
369} ffb_dev_priv_t;
370
371extern unsigned long ffb_get_unmapped_area(struct file *filp,
372 unsigned long hint,
373 unsigned long len,
374 unsigned long pgoff,
375 unsigned long flags);
376extern void ffb_set_context_ioctls(void);
377extern drm_ioctl_desc_t DRM(ioctls)[];
378
379extern int ffb_driver_context_switch(drm_device_t * dev, int old, int new);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 23:02:45 -0500