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authorDavid Hardeman <david@2gen.com>2005-08-17 03:07:44 -0400
committerWim Van Sebroeck <wim@iguana.be>2005-09-11 15:39:45 -0400
commitcc90ef0f9b24d1b017c8cfa22db5195c17b5c968 (patch)
treefd36afe9e9293c5387487af01247ee4c3cdb48b7 /drivers/char
parent3be10211abcb631ba9631274d6cfe6e5b1e8559c (diff)
[WATCHDOG] i6300esb.patch
I wrote earlier to the list[1] asking for a driver for the watchdog included in the 6300ESB chipset. I got a 2.4 driver via private email from Ross Biro which I've changed into what I hope resembles a 2.6 driver (which was done by looking a lot at the watchdog drivers already in the 2.6 tree). I've attached the result, and I'm hoping to get some feedback on the coding as a first step. I can't actually test it on the hardware right now as I won't have physical access until April. So my own tests have been limited to "compiles-without-warnings" and "can-be-insmodded-in-other-machine-without-oops". [1] http://marc.theaimsgroup.com/?l=linux-kernel&m=110711079825794&w=2 [2] http://marc.theaimsgroup.com/?l=linux-kernel&m=110711973917746&w=2 Signed-off-by: David Hardeman <david@2gen.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/watchdog/Kconfig10
-rw-r--r--drivers/char/watchdog/Makefile1
-rw-r--r--drivers/char/watchdog/i6300esb.c508
-rw-r--r--drivers/char/watchdog/i6300esb.h62
4 files changed, 581 insertions, 0 deletions
diff --git a/drivers/char/watchdog/Kconfig b/drivers/char/watchdog/Kconfig
index e8ad14d9a7fd..742c9c5bb1a6 100644
--- a/drivers/char/watchdog/Kconfig
+++ b/drivers/char/watchdog/Kconfig
@@ -234,6 +234,16 @@ config WAFER_WDT
234 To compile this driver as a module, choose M here: the 234 To compile this driver as a module, choose M here: the
235 module will be called wafer5823wdt. 235 module will be called wafer5823wdt.
236 236
237config I6300ESB_WDT
238 tristate "Intel 6300ESB Timer/Watchdog"
239 depends on WATCHDOG && X86 && PCI
240 ---help---
241 Hardware driver for the watchdog timer built into the Intel
242 6300ESB controller hub.
243
244 To compile this driver as a module, choose M here: the
245 module will be called i6300esb.
246
237config I8XX_TCO 247config I8XX_TCO
238 tristate "Intel i8xx TCO Timer/Watchdog" 248 tristate "Intel i8xx TCO Timer/Watchdog"
239 depends on WATCHDOG && (X86 || IA64) && PCI 249 depends on WATCHDOG && (X86 || IA64) && PCI
diff --git a/drivers/char/watchdog/Makefile b/drivers/char/watchdog/Makefile
index 2373e1710ae7..2f45ba6a6d16 100644
--- a/drivers/char/watchdog/Makefile
+++ b/drivers/char/watchdog/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
39obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o 39obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
40obj-$(CONFIG_IB700_WDT) += ib700wdt.o 40obj-$(CONFIG_IB700_WDT) += ib700wdt.o
41obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o 41obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
42obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o
42obj-$(CONFIG_I8XX_TCO) += i8xx_tco.o 43obj-$(CONFIG_I8XX_TCO) += i8xx_tco.o
43obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o 44obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
44obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o 45obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
diff --git a/drivers/char/watchdog/i6300esb.c b/drivers/char/watchdog/i6300esb.c
new file mode 100644
index 000000000000..87273839aead
--- /dev/null
+++ b/drivers/char/watchdog/i6300esb.c
@@ -0,0 +1,508 @@
1/*
2 * i6300esb 0.03: Watchdog timer driver for Intel 6300ESB chipset
3 *
4 * (c) Copyright 2004 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * based on i810-tco.c which is
12 *
13 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>
14 * developed for
15 * Jentro AG, Haar/Munich (Germany)
16 *
17 * which is in turn based on softdog.c by Alan Cox <alan@redhat.com>
18 *
19 * The timer is implemented in the following I/O controller hubs:
20 * (See the intel documentation on http://developer.intel.com.)
21 * 6300ESB chip : document number 300641-003
22 *
23 * 2004YYZZ Ross Biro
24 * Initial version 0.01
25 * 2004YYZZ Ross Biro
26 * Version 0.02
27 * 20050210 David Härdeman <david@2gen.com>
28 * Ported driver to kernel 2.6
29 */
30
31/*
32 * Includes, defines, variables, module parameters, ...
33 */
34
35#include <linux/module.h>
36#include <linux/types.h>
37#include <linux/kernel.h>
38#include <linux/fs.h>
39#include <linux/mm.h>
40#include <linux/miscdevice.h>
41#include <linux/watchdog.h>
42#include <linux/reboot.h>
43#include <linux/init.h>
44#include <linux/pci.h>
45#include <linux/ioport.h>
46
47#include <asm/uaccess.h>
48#include <asm/io.h>
49
50#include "i6300esb.h"
51
52/* Module and version information */
53#define ESB_VERSION "0.03"
54#define ESB_MODULE_NAME "i6300ESB timer"
55#define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
56#define PFX ESB_MODULE_NAME ": "
57
58/* internal variables */
59static void __iomem *BASEADDR;
60static spinlock_t esb_lock; /* Guards the hardware */
61static unsigned long timer_alive;
62static struct pci_dev *esb_pci;
63static unsigned short triggered; /* The status of the watchdog upon boot */
64static char esb_expect_close;
65
66/* module parameters */
67#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat (1<heartbeat<2*1023) */
68static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
69module_param(heartbeat, int, 0);
70MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (1<heartbeat<2046, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
71
72#ifdef CONFIG_WATCHDOG_NOWAYOUT
73static int nowayout = 1;
74#else
75static int nowayout = 0;
76#endif
77module_param(nowayout, int, 0);
78MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
79
80/*
81 * Some i6300ESB specific functions
82 */
83
84/*
85 * Prepare for reloading the timer by unlocking the proper registers.
86 * This is performed by first writing 0x80 followed by 0x86 to the
87 * reload register. After this the appropriate registers can be written
88 * to once before they need to be unlocked again.
89 */
90static inline void esb_unlock_registers(void) {
91 writeb(ESB_UNLOCK1, ESB_RELOAD_REG);
92 writeb(ESB_UNLOCK2, ESB_RELOAD_REG);
93}
94
95static void esb_timer_start(void)
96{
97 u8 val;
98
99 /* Enable or Enable + Lock? */
100 val = 0x02 | nowayout ? 0x01 : 0x00;
101
102 pci_write_config_byte(esb_pci, ESB_LOCK_REG, val);
103}
104
105static int esb_timer_stop(void)
106{
107 u8 val;
108
109 spin_lock(&esb_lock);
110 /* First, reset timers as suggested by the docs */
111 esb_unlock_registers();
112 writew(0x10, ESB_RELOAD_REG);
113 /* Then disable the WDT */
114 pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
115 pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
116 spin_unlock(&esb_lock);
117
118 /* Returns 0 if the timer was disabled, non-zero otherwise */
119 return (val & 0x01);
120}
121
122static void esb_timer_keepalive(void)
123{
124 spin_lock(&esb_lock);
125 esb_unlock_registers();
126 writew(0x10, ESB_RELOAD_REG);
127 /* FIXME: Do we need to flush anything here? */
128 spin_unlock(&esb_lock);
129}
130
131static int esb_timer_set_heartbeat(int time)
132{
133 u32 val;
134
135 if (time < 0x1 || time > (2 * 0x03ff))
136 return -EINVAL;
137
138 spin_lock(&esb_lock);
139
140 /* We shift by 9, so if we are passed a value of 1 sec,
141 * val will be 1 << 9 = 512, then write that to two
142 * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
143 */
144 val = time << 9;
145
146 /* Write timer 1 */
147 esb_unlock_registers();
148 writel(val, ESB_TIMER1_REG);
149
150 /* Write timer 2 */
151 esb_unlock_registers();
152 writel(val, ESB_TIMER2_REG);
153
154 /* Reload */
155 esb_unlock_registers();
156 writew(0x10, ESB_RELOAD_REG);
157
158 /* FIXME: Do we need to flush everything out? */
159
160 /* Done */
161 heartbeat = time;
162 spin_unlock(&esb_lock);
163 return 0;
164}
165
166static int esb_timer_read (void)
167{
168 u32 count;
169
170 /* This isn't documented, and doesn't take into
171 * acount which stage is running, but it looks
172 * like a 20 bit count down, so we might as well report it.
173 */
174 pci_read_config_dword(esb_pci, 0x64, &count);
175 return (int)count;
176}
177
178/*
179 * /dev/watchdog handling
180 */
181
182static int esb_open (struct inode *inode, struct file *file)
183{
184 /* /dev/watchdog can only be opened once */
185 if (test_and_set_bit(0, &timer_alive))
186 return -EBUSY;
187
188 /* Reload and activate timer */
189 esb_timer_keepalive ();
190 esb_timer_start ();
191
192 return nonseekable_open(inode, file);
193}
194
195static int esb_release (struct inode *inode, struct file *file)
196{
197 /* Shut off the timer. */
198 if (esb_expect_close == 42) {
199 esb_timer_stop ();
200 } else {
201 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
202 esb_timer_keepalive ();
203 }
204 clear_bit(0, &timer_alive);
205 esb_expect_close = 0;
206 return 0;
207}
208
209static ssize_t esb_write (struct file *file, const char __user *data,
210 size_t len, loff_t * ppos)
211{
212 /* See if we got the magic character 'V' and reload the timer */
213 if (len) {
214 if (!nowayout) {
215 size_t i;
216
217 /* note: just in case someone wrote the magic character
218 * five months ago... */
219 esb_expect_close = 0;
220
221 /* scan to see whether or not we got the magic character */
222 for (i = 0; i != len; i++) {
223 char c;
224 if(get_user(c, data+i))
225 return -EFAULT;
226 if (c == 'V')
227 esb_expect_close = 42;
228 }
229 }
230
231 /* someone wrote to us, we should reload the timer */
232 esb_timer_keepalive ();
233 }
234 return len;
235}
236
237static int esb_ioctl (struct inode *inode, struct file *file,
238 unsigned int cmd, unsigned long arg)
239{
240 int new_options, retval = -EINVAL;
241 int new_heartbeat;
242 void __user *argp = (void __user *)arg;
243 int __user *p = argp;
244 static struct watchdog_info ident = {
245 .options = WDIOF_SETTIMEOUT |
246 WDIOF_KEEPALIVEPING |
247 WDIOF_MAGICCLOSE,
248 .firmware_version = 0,
249 .identity = ESB_MODULE_NAME,
250 };
251
252 switch (cmd) {
253 case WDIOC_GETSUPPORT:
254 return copy_to_user(argp, &ident,
255 sizeof (ident)) ? -EFAULT : 0;
256
257 case WDIOC_GETSTATUS:
258 return put_user (esb_timer_read(), p);
259
260 case WDIOC_GETBOOTSTATUS:
261 return put_user (triggered, p);
262
263 case WDIOC_KEEPALIVE:
264 esb_timer_keepalive ();
265 return 0;
266
267 case WDIOC_SETOPTIONS:
268 {
269 if (get_user (new_options, p))
270 return -EFAULT;
271
272 if (new_options & WDIOS_DISABLECARD) {
273 esb_timer_stop ();
274 retval = 0;
275 }
276
277 if (new_options & WDIOS_ENABLECARD) {
278 esb_timer_keepalive ();
279 esb_timer_start ();
280 retval = 0;
281 }
282
283 return retval;
284 }
285
286 case WDIOC_SETTIMEOUT:
287 {
288 if (get_user(new_heartbeat, p))
289 return -EFAULT;
290
291 if (esb_timer_set_heartbeat(new_heartbeat))
292 return -EINVAL;
293
294 esb_timer_keepalive ();
295 /* Fall */
296 }
297
298 case WDIOC_GETTIMEOUT:
299 return put_user(heartbeat, p);
300
301 default:
302 return -ENOIOCTLCMD;
303 }
304}
305
306/*
307 * Notify system
308 */
309
310static int esb_notify_sys (struct notifier_block *this, unsigned long code, void *unused)
311{
312 if (code==SYS_DOWN || code==SYS_HALT) {
313 /* Turn the WDT off */
314 esb_timer_stop ();
315 }
316
317 return NOTIFY_DONE;
318}
319
320/*
321 * Kernel Interfaces
322 */
323
324static struct file_operations esb_fops = {
325 .owner = THIS_MODULE,
326 .llseek = no_llseek,
327 .write = esb_write,
328 .ioctl = esb_ioctl,
329 .open = esb_open,
330 .release = esb_release,
331};
332
333static struct miscdevice esb_miscdev = {
334 .minor = WATCHDOG_MINOR,
335 .name = "watchdog",
336 .fops = &esb_fops,
337};
338
339static struct notifier_block esb_notifier = {
340 .notifier_call = esb_notify_sys,
341};
342
343/*
344 * Data for PCI driver interface
345 *
346 * This data only exists for exporting the supported
347 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
348 * register a pci_driver, because someone else might one day
349 * want to register another driver on the same PCI id.
350 */
351static struct pci_device_id esb_pci_tbl[] = {
352 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9, PCI_ANY_ID, PCI_ANY_ID, },
353 { 0, }, /* End of list */
354};
355MODULE_DEVICE_TABLE (pci, esb_pci_tbl);
356
357/*
358 * Init & exit routines
359 */
360
361static unsigned char __init esb_getdevice (void)
362{
363 u8 val1;
364 unsigned short val2;
365
366 struct pci_dev *dev = NULL;
367 /*
368 * Find the PCI device
369 */
370
371 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
372 if (pci_match_device(esb_pci_tbl, dev)) {
373 esb_pci = dev;
374 break;
375 }
376 }
377
378 if (esb_pci) {
379 if (pci_enable_device(esb_pci)) {
380 printk (KERN_ERR PFX "failed to enable device\n");
381 goto out;
382 }
383
384 if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) {
385 printk (KERN_ERR PFX "failed to request region\n");
386 goto err_disable;
387 }
388
389 BASEADDR = ioremap(pci_resource_start(esb_pci, 0),
390 pci_resource_len(esb_pci, 0));
391 if (BASEADDR == NULL) {
392 /* Something's wrong here, BASEADDR has to be set */
393 printk (KERN_ERR PFX "failed to get BASEADDR\n");
394 goto err_release;
395 }
396
397 /*
398 * The watchdog has two timers, it can be setup so that the
399 * expiry of timer1 results in an interrupt and the expiry of
400 * timer2 results in a reboot. We set it to not generate
401 * any interrupts as there is not much we can do with it
402 * right now.
403 *
404 * We also enable reboots and set the timer frequency to
405 * the PCI clock divided by 2^15 (approx 1KHz).
406 */
407 pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003);
408
409 /* Check that the WDT isn't already locked */
410 pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1);
411 if (val1 & ESB_WDT_LOCK)
412 printk (KERN_WARNING PFX "nowayout already set\n");
413
414 /* Set the timer to watchdog mode and disable it for now */
415 pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00);
416
417 /* Check if the watchdog was previously triggered */
418 esb_unlock_registers();
419 val2 = readw(ESB_RELOAD_REG);
420 triggered = (val2 & (0x01 << 9) >> 9);
421
422 /* Reset trigger flag and timers */
423 esb_unlock_registers();
424 writew((0x11 << 8), ESB_RELOAD_REG);
425
426 /* Done */
427 return 1;
428
429err_release:
430 pci_release_region(esb_pci, 0);
431err_disable:
432 pci_disable_device(esb_pci);
433 }
434out:
435 return 0;
436}
437
438static int __init watchdog_init (void)
439{
440 int ret;
441
442 spin_lock_init(&esb_lock);
443
444 /* Check whether or not the hardware watchdog is there */
445 if (!esb_getdevice () || esb_pci == NULL)
446 return -ENODEV;
447
448 /* Check that the heartbeat value is within it's range ; if not reset to the default */
449 if (esb_timer_set_heartbeat (heartbeat)) {
450 esb_timer_set_heartbeat (WATCHDOG_HEARTBEAT);
451 printk(KERN_INFO PFX "heartbeat value must be 1<heartbeat<2046, using %d\n",
452 heartbeat);
453 }
454
455 ret = register_reboot_notifier(&esb_notifier);
456 if (ret != 0) {
457 printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n",
458 ret);
459 goto err_unmap;
460 }
461
462 ret = misc_register(&esb_miscdev);
463 if (ret != 0) {
464 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
465 WATCHDOG_MINOR, ret);
466 goto err_notifier;
467 }
468
469 esb_timer_stop ();
470
471 printk (KERN_INFO PFX "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
472 BASEADDR, heartbeat, nowayout);
473
474 return 0;
475
476err_notifier:
477 unregister_reboot_notifier(&esb_notifier);
478err_unmap:
479 iounmap(BASEADDR);
480/* err_release: */
481 pci_release_region(esb_pci, 0);
482/* err_disable: */
483 pci_disable_device(esb_pci);
484/* out: */
485 return ret;
486}
487
488static void __exit watchdog_cleanup (void)
489{
490 /* Stop the timer before we leave */
491 if (!nowayout)
492 esb_timer_stop ();
493
494 /* Deregister */
495 misc_deregister(&esb_miscdev);
496 unregister_reboot_notifier(&esb_notifier);
497 iounmap(BASEADDR);
498 pci_release_region(esb_pci, 0);
499 pci_disable_device(esb_pci);
500}
501
502module_init(watchdog_init);
503module_exit(watchdog_cleanup);
504
505MODULE_AUTHOR("Ross Biro and David Härdeman");
506MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
507MODULE_LICENSE("GPL");
508MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/drivers/char/watchdog/i6300esb.h b/drivers/char/watchdog/i6300esb.h
new file mode 100644
index 000000000000..b5b47e3dda1a
--- /dev/null
+++ b/drivers/char/watchdog/i6300esb.h
@@ -0,0 +1,62 @@
1/*
2 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
3 *
4 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights Reserved.
5 * http://www.kernelconcepts.de
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * Neither kernel concepts nor Nils Faerber admit liability nor provide
13 * warranty for any of this software. This material is provided
14 * "AS-IS" and at no charge.
15 *
16 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>
17 * developed for
18 * Jentro AG, Haar/Munich (Germany)
19 *
20 * TCO timer driver for i8xx chipsets
21 * based on softdog.c by Alan Cox <alan@redhat.com>
22 *
23 * For history and the complete list of supported I/O Controller Hub's
24 * see i8xx_tco.c
25 */
26
27
28/*
29 * Some address definitions for the TCO
30 */
31
32/* PCI configuration registers */
33#define ESB_CONFIG_REG 0x60 /* Config register */
34#define ESB_LOCK_REG 0x68 /* WDT lock register */
35
36/* Memory mapped registers */
37#define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */
38#define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */
39#define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */
40#define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */
41
42
43/*
44 * Some register bits
45 */
46
47/* Lock register bits */
48#define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */
49#define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */
50#define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */
51
52/* Config register bits */
53#define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */
54#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
55#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
56
57
58/*
59 * Some magic constants
60 */
61#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
62#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */