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authorJim Cromie <jim.cromie@gmail.com>2006-07-10 07:45:35 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-10 16:24:26 -0400
commit4f197842d0f3dd994882407f8760f2eda9005191 (patch)
tree3eed7508d8ae1df7aabbaea3f80f6520c695f54d /drivers/char
parent1a87d9425e0347c0e880254816d8e9f41a0e2b0c (diff)
[PATCH] pc8736x_gpio: fix re-modprobe errors: define and use constants
add constant defines - preparatory patch - adds #define CONSTs for max-pin, gpio-addr-range (for reserving region) - fix wrong max-pin check in gpio_open() - add 'Winbond' to module description. NSC sold the product, Winbond has supported us / lm-sensors Signed-off-by: Jim Cromie <jim.cromie@gmail.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/pc8736x_gpio.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/char/pc8736x_gpio.c b/drivers/char/pc8736x_gpio.c
index 4005ee0aa11e..5b09efcf60a6 100644
--- a/drivers/char/pc8736x_gpio.c
+++ b/drivers/char/pc8736x_gpio.c
@@ -25,7 +25,7 @@
25#define DEVNAME "pc8736x_gpio" 25#define DEVNAME "pc8736x_gpio"
26 26
27MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>"); 27MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
28MODULE_DESCRIPTION("NatSemi PC-8736x GPIO Pin Driver"); 28MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
29MODULE_LICENSE("GPL"); 29MODULE_LICENSE("GPL");
30 30
31static int major; /* default to dynamic major */ 31static int major; /* default to dynamic major */
@@ -38,14 +38,14 @@ static u8 pc8736x_gpio_shadow[4];
38 38
39#define SIO_BASE1 0x2E /* 1st command-reg to check */ 39#define SIO_BASE1 0x2E /* 1st command-reg to check */
40#define SIO_BASE2 0x4E /* alt command-reg to check */ 40#define SIO_BASE2 0x4E /* alt command-reg to check */
41#define SIO_BASE_OFFSET 0x20
42 41
43#define SIO_SID 0x20 /* SuperI/O ID Register */ 42#define SIO_SID 0x20 /* SuperI/O ID Register */
44#define SIO_SID_VALUE 0xe9 /* Expected value in SuperI/O ID Register */ 43#define SIO_SID_VALUE 0xe9 /* Expected value in SuperI/O ID Register */
45 44
46#define SIO_CF1 0x21 /* chip config, bit0 is chip enable */ 45#define SIO_CF1 0x21 /* chip config, bit0 is chip enable */
47 46
48#define PC8736X_GPIO_SIZE 16 47#define PC8736X_GPIO_RANGE 16 /* ioaddr range */
48#define PC8736X_GPIO_CT 32 /* minors matching 4 8 bit ports */
49 49
50#define SIO_UNIT_SEL 0x7 /* unit select reg */ 50#define SIO_UNIT_SEL 0x7 /* unit select reg */
51#define SIO_UNIT_ACT 0x30 /* unit enable */ 51#define SIO_UNIT_ACT 0x30 /* unit enable */
@@ -231,7 +231,7 @@ static int pc8736x_gpio_open(struct inode *inode, struct file *file)
231 231
232 dev_dbg(&pdev->dev, "open %d\n", m); 232 dev_dbg(&pdev->dev, "open %d\n", m);
233 233
234 if (m > 63) 234 if (m >= PC8736X_GPIO_CT)
235 return -EINVAL; 235 return -EINVAL;
236 return nonseekable_open(inode, file); 236 return nonseekable_open(inode, file);
237} 237}
@@ -297,7 +297,7 @@ static int __init pc8736x_gpio_init(void)
297 pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8 297 pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
298 | superio_inb(SIO_BASE_LADDR)); 298 | superio_inb(SIO_BASE_LADDR));
299 299
300 if (!request_region(pc8736x_gpio_base, 16, DEVNAME)) { 300 if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
301 rc = -ENODEV; 301 rc = -ENODEV;
302 dev_err(&pdev->dev, "GPIO ioport %x busy\n", 302 dev_err(&pdev->dev, "GPIO ioport %x busy\n",
303 pc8736x_gpio_base); 303 pc8736x_gpio_base);