agp/intel: map more registers for use by the GTT code

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
register for doing so is above the range we normally map.  Map the whole
register space to make sure we can get it.

v2: only map the larger space on gen7+ (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac2d401..269cb0287b10 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
 static int i9xx_setup(void)
 {
         u32 reg_addr;
+        int size = KB(512);
 
         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
 
         reg_addr &= 0xfff80000;
 
-        intel_private.registers = ioremap(reg_addr, 128 * 4096);
+        if (INTEL_GTT_GEN >= 7)
+                size = MB(2);
+
+        intel_private.registers = ioremap(reg_addr, size);
         if (!intel_private.registers)
                 return -ENOMEM;