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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-09-12 10:38:55 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:40:28 -0400
commit22533b494ff6a812b3e97248cc6c062858396182 (patch)
tree5033e66110618dedbcdc6ff7cd3beab582c92984 /drivers/char
parent0af9e92e779602bdd6d4d19acf63b4802fab91b6 (diff)
intel-gtt: store the dma mask size in intel_gtt_driver
Storing this explicitly makes for clearer code and hopefully less further confusion. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-gtt.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 4f84063bccdd..f82a2a688bcc 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -73,6 +73,7 @@ struct intel_gtt_driver {
73 unsigned int is_g33 : 1; 73 unsigned int is_g33 : 1;
74 unsigned int is_pineview : 1; 74 unsigned int is_pineview : 1;
75 unsigned int is_ironlake : 1; 75 unsigned int is_ironlake : 1;
76 unsigned int dma_mask_size : 8;
76 /* Chipset specific GTT setup */ 77 /* Chipset specific GTT setup */
77 int (*setup)(void); 78 int (*setup)(void);
78 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 79 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
@@ -1309,11 +1310,13 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
1309 1310
1310static const struct intel_gtt_driver i81x_gtt_driver = { 1311static const struct intel_gtt_driver i81x_gtt_driver = {
1311 .gen = 1, 1312 .gen = 1,
1313 .dma_mask_size = 32,
1312}; 1314};
1313static const struct intel_gtt_driver i8xx_gtt_driver = { 1315static const struct intel_gtt_driver i8xx_gtt_driver = {
1314 .gen = 2, 1316 .gen = 2,
1315 .setup = i830_setup, 1317 .setup = i830_setup,
1316 .write_entry = i830_write_entry, 1318 .write_entry = i830_write_entry,
1319 .dma_mask_size = 32,
1317 .check_flags = i830_check_flags, 1320 .check_flags = i830_check_flags,
1318 .chipset_flush = i830_chipset_flush, 1321 .chipset_flush = i830_chipset_flush,
1319}; 1322};
@@ -1322,6 +1325,7 @@ static const struct intel_gtt_driver i915_gtt_driver = {
1322 .setup = i9xx_setup, 1325 .setup = i9xx_setup,
1323 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1326 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1324 .write_entry = i830_write_entry, 1327 .write_entry = i830_write_entry,
1328 .dma_mask_size = 32,
1325 .check_flags = i830_check_flags, 1329 .check_flags = i830_check_flags,
1326 .chipset_flush = i9xx_chipset_flush, 1330 .chipset_flush = i9xx_chipset_flush,
1327}; 1331};
@@ -1330,6 +1334,7 @@ static const struct intel_gtt_driver g33_gtt_driver = {
1330 .is_g33 = 1, 1334 .is_g33 = 1,
1331 .setup = i9xx_setup, 1335 .setup = i9xx_setup,
1332 .write_entry = i965_write_entry, 1336 .write_entry = i965_write_entry,
1337 .dma_mask_size = 36,
1333 .check_flags = i830_check_flags, 1338 .check_flags = i830_check_flags,
1334 .chipset_flush = i9xx_chipset_flush, 1339 .chipset_flush = i9xx_chipset_flush,
1335}; 1340};
@@ -1338,6 +1343,7 @@ static const struct intel_gtt_driver pineview_gtt_driver = {
1338 .is_pineview = 1, .is_g33 = 1, 1343 .is_pineview = 1, .is_g33 = 1,
1339 .setup = i9xx_setup, 1344 .setup = i9xx_setup,
1340 .write_entry = i965_write_entry, 1345 .write_entry = i965_write_entry,
1346 .dma_mask_size = 36,
1341 .check_flags = i830_check_flags, 1347 .check_flags = i830_check_flags,
1342 .chipset_flush = i9xx_chipset_flush, 1348 .chipset_flush = i9xx_chipset_flush,
1343}; 1349};
@@ -1345,6 +1351,7 @@ static const struct intel_gtt_driver i965_gtt_driver = {
1345 .gen = 4, 1351 .gen = 4,
1346 .setup = i9xx_setup, 1352 .setup = i9xx_setup,
1347 .write_entry = i965_write_entry, 1353 .write_entry = i965_write_entry,
1354 .dma_mask_size = 36,
1348 .check_flags = i830_check_flags, 1355 .check_flags = i830_check_flags,
1349 .chipset_flush = i9xx_chipset_flush, 1356 .chipset_flush = i9xx_chipset_flush,
1350}; 1357};
@@ -1352,6 +1359,7 @@ static const struct intel_gtt_driver g4x_gtt_driver = {
1352 .gen = 5, 1359 .gen = 5,
1353 .setup = i9xx_setup, 1360 .setup = i9xx_setup,
1354 .write_entry = i965_write_entry, 1361 .write_entry = i965_write_entry,
1362 .dma_mask_size = 36,
1355 .check_flags = i830_check_flags, 1363 .check_flags = i830_check_flags,
1356 .chipset_flush = i9xx_chipset_flush, 1364 .chipset_flush = i9xx_chipset_flush,
1357}; 1365};
@@ -1360,6 +1368,7 @@ static const struct intel_gtt_driver ironlake_gtt_driver = {
1360 .is_ironlake = 1, 1368 .is_ironlake = 1,
1361 .setup = i9xx_setup, 1369 .setup = i9xx_setup,
1362 .write_entry = i965_write_entry, 1370 .write_entry = i965_write_entry,
1371 .dma_mask_size = 36,
1363 .check_flags = i830_check_flags, 1372 .check_flags = i830_check_flags,
1364 .chipset_flush = i9xx_chipset_flush, 1373 .chipset_flush = i9xx_chipset_flush,
1365}; 1374};
@@ -1367,6 +1376,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
1367 .gen = 6, 1376 .gen = 6,
1368 .setup = i9xx_setup, 1377 .setup = i9xx_setup,
1369 .write_entry = gen6_write_entry, 1378 .write_entry = gen6_write_entry,
1379 .dma_mask_size = 40,
1370 .check_flags = gen6_check_flags, 1380 .check_flags = gen6_check_flags,
1371 .chipset_flush = i9xx_chipset_flush, 1381 .chipset_flush = i9xx_chipset_flush,
1372}; 1382};
@@ -1511,13 +1521,7 @@ int intel_gmch_probe(struct pci_dev *pdev,
1511 1521
1512 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 1522 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1513 1523
1514 if (intel_private.driver->write_entry == gen6_write_entry) 1524 mask = intel_private.driver->dma_mask_size;
1515 mask = 40;
1516 else if (intel_private.driver->write_entry == i965_write_entry)
1517 mask = 36;
1518 else
1519 mask = 32;
1520
1521 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 1525 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1522 dev_err(&intel_private.pcidev->dev, 1526 dev_err(&intel_private.pcidev->dev,
1523 "set gfx device dma mask %d-bit failed!\n", mask); 1527 "set gfx device dma mask %d-bit failed!\n", mask);