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authorPatrick McHardy <kaber@trash.net>2011-01-19 17:51:37 -0500
committerPatrick McHardy <kaber@trash.net>2011-01-19 17:51:37 -0500
commit14f0290ba44de6ed435fea24bba26e7868421c66 (patch)
tree449d32e4848007e3edbcab14fa8e09fdc66608ed /drivers/char
parentf5c88f56b35599ab9ff2d3398e0153e4cd4a4c82 (diff)
parenta5db219f4cf9f67995eabd53b81a1232c82f5852 (diff)
Merge branch 'master' of /repos/git/net-next-2.6
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/Kconfig9
-rw-r--r--drivers/char/Makefile1
-rw-r--r--drivers/char/agp/agp.h1
-rw-r--r--drivers/char/agp/compat_ioctl.c1
-rw-r--r--drivers/char/agp/compat_ioctl.h1
-rw-r--r--drivers/char/agp/frontend.c8
-rw-r--r--drivers/char/agp/generic.c27
-rw-r--r--drivers/char/agp/intel-agp.c9
-rw-r--r--drivers/char/agp/intel-agp.h16
-rw-r--r--drivers/char/agp/intel-gtt.c789
-rw-r--r--drivers/char/cs5535_gpio.c259
-rw-r--r--drivers/char/hvc_vio.c2
-rw-r--r--drivers/char/hw_random/via-rng.c10
-rw-r--r--drivers/char/ipmi/ipmi_msghandler.c27
-rw-r--r--drivers/char/ipmi/ipmi_si_intf.c33
-rw-r--r--drivers/char/ipmi/ipmi_watchdog.c2
-rw-r--r--drivers/char/ramoops.c13
-rw-r--r--drivers/char/raw.c14
-rw-r--r--drivers/char/snsc.h1
-rw-r--r--drivers/char/tpm/tpm.c20
-rw-r--r--drivers/char/tpm/tpm.h5
21 files changed, 472 insertions, 776 deletions
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index d4a7776f4b77..0f175a866ef0 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -1047,15 +1047,6 @@ config NSC_GPIO
1047 pc8736x_gpio drivers. If those drivers are built as 1047 pc8736x_gpio drivers. If those drivers are built as
1048 modules, this one will be too, named nsc_gpio 1048 modules, this one will be too, named nsc_gpio
1049 1049
1050config CS5535_GPIO
1051 tristate "AMD CS5535/CS5536 GPIO (Geode Companion Device)"
1052 depends on X86_32
1053 help
1054 Give userspace access to the GPIO pins on the AMD CS5535 and
1055 CS5536 Geode companion devices.
1056
1057 If compiled as a module, it will be called cs5535_gpio.
1058
1059config RAW_DRIVER 1050config RAW_DRIVER
1060 tristate "RAW driver (/dev/raw/rawN)" 1051 tristate "RAW driver (/dev/raw/rawN)"
1061 depends on BLOCK 1052 depends on BLOCK
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index fa0b824b7a65..1e9dffb33778 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -82,7 +82,6 @@ obj-$(CONFIG_NWFLASH) += nwflash.o
82obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o 82obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
83obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o 83obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o
84obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o 84obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o
85obj-$(CONFIG_CS5535_GPIO) += cs5535_gpio.o
86obj-$(CONFIG_GPIO_TB0219) += tb0219.o 85obj-$(CONFIG_GPIO_TB0219) += tb0219.o
87obj-$(CONFIG_TELCLOCK) += tlclk.o 86obj-$(CONFIG_TELCLOCK) += tlclk.o
88 87
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 5259065f3c79..3e67ddde9e16 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -120,7 +120,6 @@ struct agp_bridge_driver {
120 void (*agp_destroy_page)(struct page *, int flags); 120 void (*agp_destroy_page)(struct page *, int flags);
121 void (*agp_destroy_pages)(struct agp_memory *); 121 void (*agp_destroy_pages)(struct agp_memory *);
122 int (*agp_type_to_mask_type) (struct agp_bridge_data *, int); 122 int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
123 void (*chipset_flush)(struct agp_bridge_data *);
124}; 123};
125 124
126struct agp_bridge_data { 125struct agp_bridge_data {
diff --git a/drivers/char/agp/compat_ioctl.c b/drivers/char/agp/compat_ioctl.c
index 9d2c97a69cdd..a48e05b31593 100644
--- a/drivers/char/agp/compat_ioctl.c
+++ b/drivers/char/agp/compat_ioctl.c
@@ -276,7 +276,6 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
276 break; 276 break;
277 277
278 case AGPIOC_CHIPSET_FLUSH32: 278 case AGPIOC_CHIPSET_FLUSH32:
279 ret_val = agpioc_chipset_flush_wrap(curr_priv);
280 break; 279 break;
281 } 280 }
282 281
diff --git a/drivers/char/agp/compat_ioctl.h b/drivers/char/agp/compat_ioctl.h
index 0c9678ac0371..f30e0fd97963 100644
--- a/drivers/char/agp/compat_ioctl.h
+++ b/drivers/char/agp/compat_ioctl.h
@@ -102,6 +102,5 @@ void agp_free_memory_wrap(struct agp_memory *memory);
102struct agp_memory *agp_allocate_memory_wrap(size_t pg_count, u32 type); 102struct agp_memory *agp_allocate_memory_wrap(size_t pg_count, u32 type);
103struct agp_memory *agp_find_mem_by_key(int key); 103struct agp_memory *agp_find_mem_by_key(int key);
104struct agp_client *agp_find_client_by_pid(pid_t id); 104struct agp_client *agp_find_client_by_pid(pid_t id);
105int agpioc_chipset_flush_wrap(struct agp_file_private *priv);
106 105
107#endif /* _AGP_COMPAT_H */ 106#endif /* _AGP_COMPAT_H */
diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c
index 3cb4539a98b2..2e044338753c 100644
--- a/drivers/char/agp/frontend.c
+++ b/drivers/char/agp/frontend.c
@@ -957,13 +957,6 @@ static int agpioc_unbind_wrap(struct agp_file_private *priv, void __user *arg)
957 return agp_unbind_memory(memory); 957 return agp_unbind_memory(memory);
958} 958}
959 959
960int agpioc_chipset_flush_wrap(struct agp_file_private *priv)
961{
962 DBG("");
963 agp_flush_chipset(agp_bridge);
964 return 0;
965}
966
967static long agp_ioctl(struct file *file, 960static long agp_ioctl(struct file *file,
968 unsigned int cmd, unsigned long arg) 961 unsigned int cmd, unsigned long arg)
969{ 962{
@@ -1039,7 +1032,6 @@ static long agp_ioctl(struct file *file,
1039 break; 1032 break;
1040 1033
1041 case AGPIOC_CHIPSET_FLUSH: 1034 case AGPIOC_CHIPSET_FLUSH:
1042 ret_val = agpioc_chipset_flush_wrap(curr_priv);
1043 break; 1035 break;
1044 } 1036 }
1045 1037
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index 4956f1c8f9d5..012cba0d6d96 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -81,13 +81,6 @@ static int agp_get_key(void)
81 return -1; 81 return -1;
82} 82}
83 83
84void agp_flush_chipset(struct agp_bridge_data *bridge)
85{
86 if (bridge->driver->chipset_flush)
87 bridge->driver->chipset_flush(bridge);
88}
89EXPORT_SYMBOL(agp_flush_chipset);
90
91/* 84/*
92 * Use kmalloc if possible for the page list. Otherwise fall back to 85 * Use kmalloc if possible for the page list. Otherwise fall back to
93 * vmalloc. This speeds things up and also saves memory for small AGP 86 * vmalloc. This speeds things up and also saves memory for small AGP
@@ -487,26 +480,6 @@ int agp_unbind_memory(struct agp_memory *curr)
487} 480}
488EXPORT_SYMBOL(agp_unbind_memory); 481EXPORT_SYMBOL(agp_unbind_memory);
489 482
490/**
491 * agp_rebind_emmory - Rewrite the entire GATT, useful on resume
492 */
493int agp_rebind_memory(void)
494{
495 struct agp_memory *curr;
496 int ret_val = 0;
497
498 spin_lock(&agp_bridge->mapped_lock);
499 list_for_each_entry(curr, &agp_bridge->mapped_list, mapped_list) {
500 ret_val = curr->bridge->driver->insert_memory(curr,
501 curr->pg_start,
502 curr->type);
503 if (ret_val != 0)
504 break;
505 }
506 spin_unlock(&agp_bridge->mapped_lock);
507 return ret_val;
508}
509EXPORT_SYMBOL(agp_rebind_memory);
510 483
511/* End - Routines for handling swapping of agp_memory into the GATT */ 484/* End - Routines for handling swapping of agp_memory into the GATT */
512 485
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index e72f49d52202..857df10c0428 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -717,8 +717,8 @@ static const struct intel_agp_driver_description {
717 { PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver }, 717 { PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
718 { PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver }, 718 { PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
719 { PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver }, 719 { PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
720 { PCI_DEVICE_ID_INTEL_82845_HB, "845G", &intel_845_driver }, 720 { PCI_DEVICE_ID_INTEL_82845_HB, "i845", &intel_845_driver },
721 { PCI_DEVICE_ID_INTEL_82845G_HB, "830M", &intel_845_driver }, 721 { PCI_DEVICE_ID_INTEL_82845G_HB, "845G", &intel_845_driver },
722 { PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver }, 722 { PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
723 { PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver }, 723 { PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
724 { PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver }, 724 { PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
@@ -828,14 +828,9 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
828static int agp_intel_resume(struct pci_dev *pdev) 828static int agp_intel_resume(struct pci_dev *pdev)
829{ 829{
830 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 830 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
831 int ret_val;
832 831
833 bridge->driver->configure(); 832 bridge->driver->configure();
834 833
835 ret_val = agp_rebind_memory();
836 if (ret_val != 0)
837 return ret_val;
838
839 return 0; 834 return 0;
840} 835}
841#endif 836#endif
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 90539df02504..c195bfeade11 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -75,6 +75,8 @@
75#define I810_GMS_DISABLE 0x00000000 75#define I810_GMS_DISABLE 0x00000000
76#define I810_PGETBL_CTL 0x2020 76#define I810_PGETBL_CTL 0x2020
77#define I810_PGETBL_ENABLED 0x00000001 77#define I810_PGETBL_ENABLED 0x00000001
78/* Note: PGETBL_CTL2 has a different offset on G33. */
79#define I965_PGETBL_CTL2 0x20c4
78#define I965_PGETBL_SIZE_MASK 0x0000000e 80#define I965_PGETBL_SIZE_MASK 0x0000000e
79#define I965_PGETBL_SIZE_512KB (0 << 1) 81#define I965_PGETBL_SIZE_512KB (0 << 1)
80#define I965_PGETBL_SIZE_256KB (1 << 1) 82#define I965_PGETBL_SIZE_256KB (1 << 1)
@@ -82,9 +84,17 @@
82#define I965_PGETBL_SIZE_1MB (3 << 1) 84#define I965_PGETBL_SIZE_1MB (3 << 1)
83#define I965_PGETBL_SIZE_2MB (4 << 1) 85#define I965_PGETBL_SIZE_2MB (4 << 1)
84#define I965_PGETBL_SIZE_1_5MB (5 << 1) 86#define I965_PGETBL_SIZE_1_5MB (5 << 1)
85#define G33_PGETBL_SIZE_MASK (3 << 8) 87#define G33_GMCH_SIZE_MASK (3 << 8)
86#define G33_PGETBL_SIZE_1M (1 << 8) 88#define G33_GMCH_SIZE_1M (1 << 8)
87#define G33_PGETBL_SIZE_2M (2 << 8) 89#define G33_GMCH_SIZE_2M (2 << 8)
90#define G4x_GMCH_SIZE_MASK (0xf << 8)
91#define G4x_GMCH_SIZE_1M (0x1 << 8)
92#define G4x_GMCH_SIZE_2M (0x3 << 8)
93#define G4x_GMCH_SIZE_VT_1M (0x9 << 8)
94#define G4x_GMCH_SIZE_VT_1_5M (0xa << 8)
95#define G4x_GMCH_SIZE_VT_2M (0xc << 8)
96
97#define GFX_FLSH_CNTL 0x2170 /* 915+ */
88 98
89#define I810_DRAM_CTL 0x3000 99#define I810_DRAM_CTL 0x3000
90#define I810_DRAM_ROW_0 0x00000001 100#define I810_DRAM_ROW_0 0x00000001
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 29ac6d499fa6..826ab0939a12 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -24,7 +24,6 @@
24#include <asm/smp.h> 24#include <asm/smp.h>
25#include "agp.h" 25#include "agp.h"
26#include "intel-agp.h" 26#include "intel-agp.h"
27#include <linux/intel-gtt.h>
28#include <drm/intel-gtt.h> 27#include <drm/intel-gtt.h>
29 28
30/* 29/*
@@ -39,40 +38,12 @@
39#define USE_PCI_DMA_API 0 38#define USE_PCI_DMA_API 0
40#endif 39#endif
41 40
42/* Max amount of stolen space, anything above will be returned to Linux */
43int intel_max_stolen = 32 * 1024 * 1024;
44
45static const struct aper_size_info_fixed intel_i810_sizes[] =
46{
47 {64, 16384, 4},
48 /* The 32M mode still requires a 64k gatt */
49 {32, 8192, 4}
50};
51
52#define AGP_DCACHE_MEMORY 1
53#define AGP_PHYS_MEMORY 2
54#define INTEL_AGP_CACHED_MEMORY 3
55
56static struct gatt_mask intel_i810_masks[] =
57{
58 {.mask = I810_PTE_VALID, .type = 0},
59 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
60 {.mask = I810_PTE_VALID, .type = 0},
61 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
62 .type = INTEL_AGP_CACHED_MEMORY}
63};
64
65#define INTEL_AGP_UNCACHED_MEMORY 0
66#define INTEL_AGP_CACHED_MEMORY_LLC 1
67#define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
68#define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
69#define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70
71struct intel_gtt_driver { 41struct intel_gtt_driver {
72 unsigned int gen : 8; 42 unsigned int gen : 8;
73 unsigned int is_g33 : 1; 43 unsigned int is_g33 : 1;
74 unsigned int is_pineview : 1; 44 unsigned int is_pineview : 1;
75 unsigned int is_ironlake : 1; 45 unsigned int is_ironlake : 1;
46 unsigned int has_pgtbl_enable : 1;
76 unsigned int dma_mask_size : 8; 47 unsigned int dma_mask_size : 8;
77 /* Chipset specific GTT setup */ 48 /* Chipset specific GTT setup */
78 int (*setup)(void); 49 int (*setup)(void);
@@ -95,13 +66,14 @@ static struct _intel_private {
95 u8 __iomem *registers; 66 u8 __iomem *registers;
96 phys_addr_t gtt_bus_addr; 67 phys_addr_t gtt_bus_addr;
97 phys_addr_t gma_bus_addr; 68 phys_addr_t gma_bus_addr;
98 phys_addr_t pte_bus_addr; 69 u32 PGETBL_save;
99 u32 __iomem *gtt; /* I915G */ 70 u32 __iomem *gtt; /* I915G */
100 int num_dcache_entries; 71 int num_dcache_entries;
101 union { 72 union {
102 void __iomem *i9xx_flush_page; 73 void __iomem *i9xx_flush_page;
103 void *i8xx_flush_page; 74 void *i8xx_flush_page;
104 }; 75 };
76 char *i81x_gtt_table;
105 struct page *i8xx_page; 77 struct page *i8xx_page;
106 struct resource ifp_resource; 78 struct resource ifp_resource;
107 int resource_valid; 79 int resource_valid;
@@ -113,42 +85,31 @@ static struct _intel_private {
113#define IS_G33 intel_private.driver->is_g33 85#define IS_G33 intel_private.driver->is_g33
114#define IS_PINEVIEW intel_private.driver->is_pineview 86#define IS_PINEVIEW intel_private.driver->is_pineview
115#define IS_IRONLAKE intel_private.driver->is_ironlake 87#define IS_IRONLAKE intel_private.driver->is_ironlake
88#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
116 89
117static void intel_agp_free_sglist(struct agp_memory *mem) 90int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
118{ 91 struct scatterlist **sg_list, int *num_sg)
119 struct sg_table st;
120
121 st.sgl = mem->sg_list;
122 st.orig_nents = st.nents = mem->page_count;
123
124 sg_free_table(&st);
125
126 mem->sg_list = NULL;
127 mem->num_sg = 0;
128}
129
130static int intel_agp_map_memory(struct agp_memory *mem)
131{ 92{
132 struct sg_table st; 93 struct sg_table st;
133 struct scatterlist *sg; 94 struct scatterlist *sg;
134 int i; 95 int i;
135 96
136 if (mem->sg_list) 97 if (*sg_list)
137 return 0; /* already mapped (for e.g. resume */ 98 return 0; /* already mapped (for e.g. resume */
138 99
139 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 100 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
140 101
141 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 102 if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
142 goto err; 103 goto err;
143 104
144 mem->sg_list = sg = st.sgl; 105 *sg_list = sg = st.sgl;
145 106
146 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 107 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
147 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 108 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
148 109
149 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 110 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
150 mem->page_count, PCI_DMA_BIDIRECTIONAL); 111 num_entries, PCI_DMA_BIDIRECTIONAL);
151 if (unlikely(!mem->num_sg)) 112 if (unlikely(!*num_sg))
152 goto err; 113 goto err;
153 114
154 return 0; 115 return 0;
@@ -157,90 +118,22 @@ err:
157 sg_free_table(&st); 118 sg_free_table(&st);
158 return -ENOMEM; 119 return -ENOMEM;
159} 120}
121EXPORT_SYMBOL(intel_gtt_map_memory);
160 122
161static void intel_agp_unmap_memory(struct agp_memory *mem) 123void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
162{ 124{
125 struct sg_table st;
163 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 126 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
164 127
165 pci_unmap_sg(intel_private.pcidev, mem->sg_list, 128 pci_unmap_sg(intel_private.pcidev, sg_list,
166 mem->page_count, PCI_DMA_BIDIRECTIONAL); 129 num_sg, PCI_DMA_BIDIRECTIONAL);
167 intel_agp_free_sglist(mem);
168}
169
170static int intel_i810_fetch_size(void)
171{
172 u32 smram_miscc;
173 struct aper_size_info_fixed *values;
174
175 pci_read_config_dword(intel_private.bridge_dev,
176 I810_SMRAM_MISCC, &smram_miscc);
177 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
178
179 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
180 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
181 return 0;
182 }
183 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
184 agp_bridge->current_size = (void *) (values + 1);
185 agp_bridge->aperture_size_idx = 1;
186 return values[1].size;
187 } else {
188 agp_bridge->current_size = (void *) (values);
189 agp_bridge->aperture_size_idx = 0;
190 return values[0].size;
191 }
192 130
193 return 0; 131 st.sgl = sg_list;
194} 132 st.orig_nents = st.nents = num_sg;
195 133
196static int intel_i810_configure(void) 134 sg_free_table(&st);
197{
198 struct aper_size_info_fixed *current_size;
199 u32 temp;
200 int i;
201
202 current_size = A_SIZE_FIX(agp_bridge->current_size);
203
204 if (!intel_private.registers) {
205 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
206 temp &= 0xfff80000;
207
208 intel_private.registers = ioremap(temp, 128 * 4096);
209 if (!intel_private.registers) {
210 dev_err(&intel_private.pcidev->dev,
211 "can't remap memory\n");
212 return -ENOMEM;
213 }
214 }
215
216 if ((readl(intel_private.registers+I810_DRAM_CTL)
217 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
218 /* This will need to be dynamically assigned */
219 dev_info(&intel_private.pcidev->dev,
220 "detected 4MB dedicated video ram\n");
221 intel_private.num_dcache_entries = 1024;
222 }
223 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
224 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
225 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
226 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
227
228 if (agp_bridge->driver->needs_scratch_page) {
229 for (i = 0; i < current_size->num_entries; i++) {
230 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
231 }
232 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
233 }
234 global_cache_flush();
235 return 0;
236}
237
238static void intel_i810_cleanup(void)
239{
240 writel(0, intel_private.registers+I810_PGETBL_CTL);
241 readl(intel_private.registers); /* PCI Posting. */
242 iounmap(intel_private.registers);
243} 135}
136EXPORT_SYMBOL(intel_gtt_unmap_memory);
244 137
245static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 138static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
246{ 139{
@@ -277,80 +170,64 @@ static void i8xx_destroy_pages(struct page *page)
277 atomic_dec(&agp_bridge->current_memory_agp); 170 atomic_dec(&agp_bridge->current_memory_agp);
278} 171}
279 172
280static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 173#define I810_GTT_ORDER 4
281 int type) 174static int i810_setup(void)
282{ 175{
283 int i, j, num_entries; 176 u32 reg_addr;
284 void *temp; 177 char *gtt_table;
285 int ret = -EINVAL;
286 int mask_type;
287
288 if (mem->page_count == 0)
289 goto out;
290
291 temp = agp_bridge->current_size;
292 num_entries = A_SIZE_FIX(temp)->num_entries;
293 178
294 if ((pg_start + mem->page_count) > num_entries) 179 /* i81x does not preallocate the gtt. It's always 64kb in size. */
295 goto out_err; 180 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
181 if (gtt_table == NULL)
182 return -ENOMEM;
183 intel_private.i81x_gtt_table = gtt_table;
296 184
185 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
186 reg_addr &= 0xfff80000;
297 187
298 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 188 intel_private.registers = ioremap(reg_addr, KB(64));
299 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 189 if (!intel_private.registers)
300 ret = -EBUSY; 190 return -ENOMEM;
301 goto out_err;
302 }
303 }
304 191
305 if (type != mem->type) 192 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
306 goto out_err; 193 intel_private.registers+I810_PGETBL_CTL);
307 194
308 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 195 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
309 196
310 switch (mask_type) { 197 if ((readl(intel_private.registers+I810_DRAM_CTL)
311 case AGP_DCACHE_MEMORY: 198 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
312 if (!mem->is_flushed) 199 dev_info(&intel_private.pcidev->dev,
313 global_cache_flush(); 200 "detected 4MB dedicated video ram\n");
314 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 201 intel_private.num_dcache_entries = 1024;
315 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
316 intel_private.registers+I810_PTE_BASE+(i*4));
317 }
318 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
319 break;
320 case AGP_PHYS_MEMORY:
321 case AGP_NORMAL_MEMORY:
322 if (!mem->is_flushed)
323 global_cache_flush();
324 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
325 writel(agp_bridge->driver->mask_memory(agp_bridge,
326 page_to_phys(mem->pages[i]), mask_type),
327 intel_private.registers+I810_PTE_BASE+(j*4));
328 }
329 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
330 break;
331 default:
332 goto out_err;
333 } 202 }
334 203
335out: 204 return 0;
336 ret = 0;
337out_err:
338 mem->is_flushed = true;
339 return ret;
340} 205}
341 206
342static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 207static void i810_cleanup(void)
343 int type) 208{
209 writel(0, intel_private.registers+I810_PGETBL_CTL);
210 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
211}
212
213static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
214 int type)
344{ 215{
345 int i; 216 int i;
346 217
347 if (mem->page_count == 0) 218 if ((pg_start + mem->page_count)
348 return 0; 219 > intel_private.num_dcache_entries)
220 return -EINVAL;
349 221
350 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 222 if (!mem->is_flushed)
351 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 223 global_cache_flush();
224
225 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
226 dma_addr_t addr = i << PAGE_SHIFT;
227 intel_private.driver->write_entry(addr,
228 i, type);
352 } 229 }
353 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 230 readl(intel_private.gtt+i-1);
354 231
355 return 0; 232 return 0;
356} 233}
@@ -397,29 +274,6 @@ static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
397 return new; 274 return new;
398} 275}
399 276
400static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
401{
402 struct agp_memory *new;
403
404 if (type == AGP_DCACHE_MEMORY) {
405 if (pg_count != intel_private.num_dcache_entries)
406 return NULL;
407
408 new = agp_create_memory(1);
409 if (new == NULL)
410 return NULL;
411
412 new->type = AGP_DCACHE_MEMORY;
413 new->page_count = pg_count;
414 new->num_scratch_pages = 0;
415 agp_free_page_array(new);
416 return new;
417 }
418 if (type == AGP_PHYS_MEMORY)
419 return alloc_agpphysmem_i8xx(pg_count, type);
420 return NULL;
421}
422
423static void intel_i810_free_by_type(struct agp_memory *curr) 277static void intel_i810_free_by_type(struct agp_memory *curr)
424{ 278{
425 agp_free_key(curr->key); 279 agp_free_key(curr->key);
@@ -437,13 +291,6 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
437 kfree(curr); 291 kfree(curr);
438} 292}
439 293
440static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
441 dma_addr_t addr, int type)
442{
443 /* Type checking must be done elsewhere */
444 return addr | bridge->driver->masks[type].mask;
445}
446
447static int intel_gtt_setup_scratch_page(void) 294static int intel_gtt_setup_scratch_page(void)
448{ 295{
449 struct page *page; 296 struct page *page;
@@ -455,7 +302,7 @@ static int intel_gtt_setup_scratch_page(void)
455 get_page(page); 302 get_page(page);
456 set_pages_uc(page, 1); 303 set_pages_uc(page, 1);
457 304
458 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { 305 if (intel_private.base.needs_dmar) {
459 dma_addr = pci_map_page(intel_private.pcidev, page, 0, 306 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
460 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 307 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
461 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 308 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
@@ -470,34 +317,45 @@ static int intel_gtt_setup_scratch_page(void)
470 return 0; 317 return 0;
471} 318}
472 319
473static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = { 320static void i810_write_entry(dma_addr_t addr, unsigned int entry,
321 unsigned int flags)
322{
323 u32 pte_flags = I810_PTE_VALID;
324
325 switch (flags) {
326 case AGP_DCACHE_MEMORY:
327 pte_flags |= I810_PTE_LOCAL;
328 break;
329 case AGP_USER_CACHED_MEMORY:
330 pte_flags |= I830_PTE_SYSTEM_CACHED;
331 break;
332 }
333
334 writel(addr | pte_flags, intel_private.gtt + entry);
335}
336
337static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
338 {32, 8192, 3},
339 {64, 16384, 4},
474 {128, 32768, 5}, 340 {128, 32768, 5},
475 /* The 64M mode still requires a 128k gatt */
476 {64, 16384, 5},
477 {256, 65536, 6}, 341 {256, 65536, 6},
478 {512, 131072, 7}, 342 {512, 131072, 7},
479}; 343};
480 344
481static unsigned int intel_gtt_stolen_entries(void) 345static unsigned int intel_gtt_stolen_size(void)
482{ 346{
483 u16 gmch_ctrl; 347 u16 gmch_ctrl;
484 u8 rdct; 348 u8 rdct;
485 int local = 0; 349 int local = 0;
486 static const int ddt[4] = { 0, 16, 32, 64 }; 350 static const int ddt[4] = { 0, 16, 32, 64 };
487 unsigned int overhead_entries, stolen_entries;
488 unsigned int stolen_size = 0; 351 unsigned int stolen_size = 0;
489 352
353 if (INTEL_GTT_GEN == 1)
354 return 0; /* no stolen mem on i81x */
355
490 pci_read_config_word(intel_private.bridge_dev, 356 pci_read_config_word(intel_private.bridge_dev,
491 I830_GMCH_CTRL, &gmch_ctrl); 357 I830_GMCH_CTRL, &gmch_ctrl);
492 358
493 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
494 overhead_entries = 0;
495 else
496 overhead_entries = intel_private.base.gtt_mappable_entries
497 / 1024;
498
499 overhead_entries += 1; /* BIOS popup */
500
501 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 359 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
502 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 360 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
503 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 361 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
@@ -623,12 +481,7 @@ static unsigned int intel_gtt_stolen_entries(void)
623 } 481 }
624 } 482 }
625 483
626 if (!local && stolen_size > intel_max_stolen) { 484 if (stolen_size > 0) {
627 dev_info(&intel_private.bridge_dev->dev,
628 "detected %dK stolen memory, trimming to %dK\n",
629 stolen_size / KB(1), intel_max_stolen / KB(1));
630 stolen_size = intel_max_stolen;
631 } else if (stolen_size > 0) {
632 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 485 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
633 stolen_size / KB(1), local ? "local" : "stolen"); 486 stolen_size / KB(1), local ? "local" : "stolen");
634 } else { 487 } else {
@@ -637,46 +490,88 @@ static unsigned int intel_gtt_stolen_entries(void)
637 stolen_size = 0; 490 stolen_size = 0;
638 } 491 }
639 492
640 stolen_entries = stolen_size/KB(4) - overhead_entries; 493 return stolen_size;
494}
641 495
642 return stolen_entries; 496static void i965_adjust_pgetbl_size(unsigned int size_flag)
497{
498 u32 pgetbl_ctl, pgetbl_ctl2;
499
500 /* ensure that ppgtt is disabled */
501 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
502 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
503 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
504
505 /* write the new ggtt size */
506 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
507 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
508 pgetbl_ctl |= size_flag;
509 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
643} 510}
644 511
645static unsigned int intel_gtt_total_entries(void) 512static unsigned int i965_gtt_total_entries(void)
646{ 513{
647 int size; 514 int size;
515 u32 pgetbl_ctl;
516 u16 gmch_ctl;
648 517
649 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) { 518 pci_read_config_word(intel_private.bridge_dev,
650 u32 pgetbl_ctl; 519 I830_GMCH_CTRL, &gmch_ctl);
651 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
652 520
653 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 521 if (INTEL_GTT_GEN == 5) {
654 case I965_PGETBL_SIZE_128KB: 522 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
655 size = KB(128); 523 case G4x_GMCH_SIZE_1M:
524 case G4x_GMCH_SIZE_VT_1M:
525 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
656 break; 526 break;
657 case I965_PGETBL_SIZE_256KB: 527 case G4x_GMCH_SIZE_VT_1_5M:
658 size = KB(256); 528 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
659 break; 529 break;
660 case I965_PGETBL_SIZE_512KB: 530 case G4x_GMCH_SIZE_2M:
661 size = KB(512); 531 case G4x_GMCH_SIZE_VT_2M:
532 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
662 break; 533 break;
663 case I965_PGETBL_SIZE_1MB:
664 size = KB(1024);
665 break;
666 case I965_PGETBL_SIZE_2MB:
667 size = KB(2048);
668 break;
669 case I965_PGETBL_SIZE_1_5MB:
670 size = KB(1024 + 512);
671 break;
672 default:
673 dev_info(&intel_private.pcidev->dev,
674 "unknown page table size, assuming 512KB\n");
675 size = KB(512);
676 } 534 }
535 }
677 536
678 return size/4; 537 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
679 } else if (INTEL_GTT_GEN == 6) { 538
539 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
540 case I965_PGETBL_SIZE_128KB:
541 size = KB(128);
542 break;
543 case I965_PGETBL_SIZE_256KB:
544 size = KB(256);
545 break;
546 case I965_PGETBL_SIZE_512KB:
547 size = KB(512);
548 break;
549 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
550 case I965_PGETBL_SIZE_1MB:
551 size = KB(1024);
552 break;
553 case I965_PGETBL_SIZE_2MB:
554 size = KB(2048);
555 break;
556 case I965_PGETBL_SIZE_1_5MB:
557 size = KB(1024 + 512);
558 break;
559 default:
560 dev_info(&intel_private.pcidev->dev,
561 "unknown page table size, assuming 512KB\n");
562 size = KB(512);
563 }
564
565 return size/4;
566}
567
568static unsigned int intel_gtt_total_entries(void)
569{
570 int size;
571
572 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
573 return i965_gtt_total_entries();
574 else if (INTEL_GTT_GEN == 6) {
680 u16 snb_gmch_ctl; 575 u16 snb_gmch_ctl;
681 576
682 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 577 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
@@ -706,7 +601,18 @@ static unsigned int intel_gtt_mappable_entries(void)
706{ 601{
707 unsigned int aperture_size; 602 unsigned int aperture_size;
708 603
709 if (INTEL_GTT_GEN == 2) { 604 if (INTEL_GTT_GEN == 1) {
605 u32 smram_miscc;
606
607 pci_read_config_dword(intel_private.bridge_dev,
608 I810_SMRAM_MISCC, &smram_miscc);
609
610 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
611 == I810_GFX_MEM_WIN_32M)
612 aperture_size = MB(32);
613 else
614 aperture_size = MB(64);
615 } else if (INTEL_GTT_GEN == 2) {
710 u16 gmch_ctrl; 616 u16 gmch_ctrl;
711 617
712 pci_read_config_word(intel_private.bridge_dev, 618 pci_read_config_word(intel_private.bridge_dev,
@@ -739,7 +645,7 @@ static void intel_gtt_cleanup(void)
739 645
740 iounmap(intel_private.gtt); 646 iounmap(intel_private.gtt);
741 iounmap(intel_private.registers); 647 iounmap(intel_private.registers);
742 648
743 intel_gtt_teardown_scratch_page(); 649 intel_gtt_teardown_scratch_page();
744} 650}
745 651
@@ -755,6 +661,14 @@ static int intel_gtt_init(void)
755 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 661 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
756 intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 662 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
757 663
664 /* save the PGETBL reg for resume */
665 intel_private.PGETBL_save =
666 readl(intel_private.registers+I810_PGETBL_CTL)
667 & ~I810_PGETBL_ENABLED;
668 /* we only ever restore the register when enabling the PGTBL... */
669 if (HAS_PGTBL_EN)
670 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
671
758 dev_info(&intel_private.bridge_dev->dev, 672 dev_info(&intel_private.bridge_dev->dev,
759 "detected gtt size: %dK total, %dK mappable\n", 673 "detected gtt size: %dK total, %dK mappable\n",
760 intel_private.base.gtt_total_entries * 4, 674 intel_private.base.gtt_total_entries * 4,
@@ -772,14 +686,9 @@ static int intel_gtt_init(void)
772 686
773 global_cache_flush(); /* FIXME: ? */ 687 global_cache_flush(); /* FIXME: ? */
774 688
775 /* we have to call this as early as possible after the MMIO base address is known */ 689 intel_private.base.stolen_size = intel_gtt_stolen_size();
776 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); 690
777 if (intel_private.base.gtt_stolen_entries == 0) { 691 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
778 intel_private.driver->cleanup();
779 iounmap(intel_private.registers);
780 iounmap(intel_private.gtt);
781 return -ENOMEM;
782 }
783 692
784 ret = intel_gtt_setup_scratch_page(); 693 ret = intel_gtt_setup_scratch_page();
785 if (ret != 0) { 694 if (ret != 0) {
@@ -862,25 +771,19 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,
862 unsigned int flags) 771 unsigned int flags)
863{ 772{
864 u32 pte_flags = I810_PTE_VALID; 773 u32 pte_flags = I810_PTE_VALID;
865 774
866 switch (flags) { 775 if (flags == AGP_USER_CACHED_MEMORY)
867 case AGP_DCACHE_MEMORY:
868 pte_flags |= I810_PTE_LOCAL;
869 break;
870 case AGP_USER_CACHED_MEMORY:
871 pte_flags |= I830_PTE_SYSTEM_CACHED; 776 pte_flags |= I830_PTE_SYSTEM_CACHED;
872 break;
873 }
874 777
875 writel(addr | pte_flags, intel_private.gtt + entry); 778 writel(addr | pte_flags, intel_private.gtt + entry);
876} 779}
877 780
878static void intel_enable_gtt(void) 781static bool intel_enable_gtt(void)
879{ 782{
880 u32 gma_addr; 783 u32 gma_addr;
881 u16 gmch_ctrl; 784 u8 __iomem *reg;
882 785
883 if (INTEL_GTT_GEN == 2) 786 if (INTEL_GTT_GEN <= 2)
884 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 787 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
885 &gma_addr); 788 &gma_addr);
886 else 789 else
@@ -889,13 +792,47 @@ static void intel_enable_gtt(void)
889 792
890 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 793 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
891 794
892 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); 795 if (INTEL_GTT_GEN >= 6)
893 gmch_ctrl |= I830_GMCH_ENABLED; 796 return true;
894 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
895 797
896 writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED, 798 if (INTEL_GTT_GEN == 2) {
897 intel_private.registers+I810_PGETBL_CTL); 799 u16 gmch_ctrl;
898 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 800
801 pci_read_config_word(intel_private.bridge_dev,
802 I830_GMCH_CTRL, &gmch_ctrl);
803 gmch_ctrl |= I830_GMCH_ENABLED;
804 pci_write_config_word(intel_private.bridge_dev,
805 I830_GMCH_CTRL, gmch_ctrl);
806
807 pci_read_config_word(intel_private.bridge_dev,
808 I830_GMCH_CTRL, &gmch_ctrl);
809 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
810 dev_err(&intel_private.pcidev->dev,
811 "failed to enable the GTT: GMCH_CTRL=%x\n",
812 gmch_ctrl);
813 return false;
814 }
815 }
816
817 /* On the resume path we may be adjusting the PGTBL value, so
818 * be paranoid and flush all chipset write buffers...
819 */
820 if (INTEL_GTT_GEN >= 3)
821 writel(0, intel_private.registers+GFX_FLSH_CNTL);
822
823 reg = intel_private.registers+I810_PGETBL_CTL;
824 writel(intel_private.PGETBL_save, reg);
825 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
826 dev_err(&intel_private.pcidev->dev,
827 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
828 readl(reg), intel_private.PGETBL_save);
829 return false;
830 }
831
832 if (INTEL_GTT_GEN >= 3)
833 writel(0, intel_private.registers+GFX_FLSH_CNTL);
834
835 return true;
899} 836}
900 837
901static int i830_setup(void) 838static int i830_setup(void)
@@ -910,8 +847,6 @@ static int i830_setup(void)
910 return -ENOMEM; 847 return -ENOMEM;
911 848
912 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 849 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
913 intel_private.pte_bus_addr =
914 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
915 850
916 intel_i830_setup_flush(); 851 intel_i830_setup_flush();
917 852
@@ -936,12 +871,12 @@ static int intel_fake_agp_configure(void)
936{ 871{
937 int i; 872 int i;
938 873
939 intel_enable_gtt(); 874 if (!intel_enable_gtt())
875 return -EIO;
940 876
941 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 877 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
942 878
943 for (i = intel_private.base.gtt_stolen_entries; 879 for (i = 0; i < intel_private.base.gtt_total_entries; i++) {
944 i < intel_private.base.gtt_total_entries; i++) {
945 intel_private.driver->write_entry(intel_private.scratch_page_dma, 880 intel_private.driver->write_entry(intel_private.scratch_page_dma,
946 i, 0); 881 i, 0);
947 } 882 }
@@ -965,10 +900,10 @@ static bool i830_check_flags(unsigned int flags)
965 return false; 900 return false;
966} 901}
967 902
968static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, 903void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
969 unsigned int sg_len, 904 unsigned int sg_len,
970 unsigned int pg_start, 905 unsigned int pg_start,
971 unsigned int flags) 906 unsigned int flags)
972{ 907{
973 struct scatterlist *sg; 908 struct scatterlist *sg;
974 unsigned int len, m; 909 unsigned int len, m;
@@ -989,27 +924,34 @@ static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
989 } 924 }
990 readl(intel_private.gtt+j-1); 925 readl(intel_private.gtt+j-1);
991} 926}
927EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
928
929void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
930 struct page **pages, unsigned int flags)
931{
932 int i, j;
933
934 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
935 dma_addr_t addr = page_to_phys(pages[i]);
936 intel_private.driver->write_entry(addr,
937 j, flags);
938 }
939 readl(intel_private.gtt+j-1);
940}
941EXPORT_SYMBOL(intel_gtt_insert_pages);
992 942
993static int intel_fake_agp_insert_entries(struct agp_memory *mem, 943static int intel_fake_agp_insert_entries(struct agp_memory *mem,
994 off_t pg_start, int type) 944 off_t pg_start, int type)
995{ 945{
996 int i, j;
997 int ret = -EINVAL; 946 int ret = -EINVAL;
998 947
948 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
949 return i810_insert_dcache_entries(mem, pg_start, type);
950
999 if (mem->page_count == 0) 951 if (mem->page_count == 0)
1000 goto out; 952 goto out;
1001 953
1002 if (pg_start < intel_private.base.gtt_stolen_entries) { 954 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
1003 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1004 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1005 pg_start, intel_private.base.gtt_stolen_entries);
1006
1007 dev_info(&intel_private.pcidev->dev,
1008 "trying to insert into local/stolen memory\n");
1009 goto out_err;
1010 }
1011
1012 if ((pg_start + mem->page_count) > intel_private.base.gtt_total_entries)
1013 goto out_err; 955 goto out_err;
1014 956
1015 if (type != mem->type) 957 if (type != mem->type)
@@ -1021,21 +963,17 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
1021 if (!mem->is_flushed) 963 if (!mem->is_flushed)
1022 global_cache_flush(); 964 global_cache_flush();
1023 965
1024 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { 966 if (intel_private.base.needs_dmar) {
1025 ret = intel_agp_map_memory(mem); 967 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
968 &mem->sg_list, &mem->num_sg);
1026 if (ret != 0) 969 if (ret != 0)
1027 return ret; 970 return ret;
1028 971
1029 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, 972 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
1030 pg_start, type); 973 pg_start, type);
1031 } else { 974 } else
1032 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 975 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
1033 dma_addr_t addr = page_to_phys(mem->pages[i]); 976 type);
1034 intel_private.driver->write_entry(addr,
1035 j, type);
1036 }
1037 readl(intel_private.gtt+j-1);
1038 }
1039 977
1040out: 978out:
1041 ret = 0; 979 ret = 0;
@@ -1044,40 +982,54 @@ out_err:
1044 return ret; 982 return ret;
1045} 983}
1046 984
985void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
986{
987 unsigned int i;
988
989 for (i = first_entry; i < (first_entry + num_entries); i++) {
990 intel_private.driver->write_entry(intel_private.scratch_page_dma,
991 i, 0);
992 }
993 readl(intel_private.gtt+i-1);
994}
995EXPORT_SYMBOL(intel_gtt_clear_range);
996
1047static int intel_fake_agp_remove_entries(struct agp_memory *mem, 997static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1048 off_t pg_start, int type) 998 off_t pg_start, int type)
1049{ 999{
1050 int i;
1051
1052 if (mem->page_count == 0) 1000 if (mem->page_count == 0)
1053 return 0; 1001 return 0;
1054 1002
1055 if (pg_start < intel_private.base.gtt_stolen_entries) { 1003 intel_gtt_clear_range(pg_start, mem->page_count);
1056 dev_info(&intel_private.pcidev->dev,
1057 "trying to disable local/stolen memory\n");
1058 return -EINVAL;
1059 }
1060
1061 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2)
1062 intel_agp_unmap_memory(mem);
1063 1004
1064 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1005 if (intel_private.base.needs_dmar) {
1065 intel_private.driver->write_entry(intel_private.scratch_page_dma, 1006 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
1066 i, 0); 1007 mem->sg_list = NULL;
1008 mem->num_sg = 0;
1067 } 1009 }
1068 readl(intel_private.gtt+i-1);
1069 1010
1070 return 0; 1011 return 0;
1071} 1012}
1072 1013
1073static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge)
1074{
1075 intel_private.driver->chipset_flush();
1076}
1077
1078static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1014static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1079 int type) 1015 int type)
1080{ 1016{
1017 struct agp_memory *new;
1018
1019 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1020 if (pg_count != intel_private.num_dcache_entries)
1021 return NULL;
1022
1023 new = agp_create_memory(1);
1024 if (new == NULL)
1025 return NULL;
1026
1027 new->type = AGP_DCACHE_MEMORY;
1028 new->page_count = pg_count;
1029 new->num_scratch_pages = 0;
1030 agp_free_page_array(new);
1031 return new;
1032 }
1081 if (type == AGP_PHYS_MEMORY) 1033 if (type == AGP_PHYS_MEMORY)
1082 return alloc_agpphysmem_i8xx(pg_count, type); 1034 return alloc_agpphysmem_i8xx(pg_count, type);
1083 /* always return NULL for other allocation types for now */ 1035 /* always return NULL for other allocation types for now */
@@ -1274,40 +1226,11 @@ static int i9xx_setup(void)
1274 intel_private.gtt_bus_addr = reg_addr + gtt_offset; 1226 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1275 } 1227 }
1276 1228
1277 intel_private.pte_bus_addr =
1278 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1279
1280 intel_i9xx_setup_flush(); 1229 intel_i9xx_setup_flush();
1281 1230
1282 return 0; 1231 return 0;
1283} 1232}
1284 1233
1285static const struct agp_bridge_driver intel_810_driver = {
1286 .owner = THIS_MODULE,
1287 .aperture_sizes = intel_i810_sizes,
1288 .size_type = FIXED_APER_SIZE,
1289 .num_aperture_sizes = 2,
1290 .needs_scratch_page = true,
1291 .configure = intel_i810_configure,
1292 .fetch_size = intel_i810_fetch_size,
1293 .cleanup = intel_i810_cleanup,
1294 .mask_memory = intel_i810_mask_memory,
1295 .masks = intel_i810_masks,
1296 .agp_enable = intel_fake_agp_enable,
1297 .cache_flush = global_cache_flush,
1298 .create_gatt_table = agp_generic_create_gatt_table,
1299 .free_gatt_table = agp_generic_free_gatt_table,
1300 .insert_memory = intel_i810_insert_entries,
1301 .remove_memory = intel_i810_remove_entries,
1302 .alloc_by_type = intel_i810_alloc_by_type,
1303 .free_by_type = intel_i810_free_by_type,
1304 .agp_alloc_page = agp_generic_alloc_page,
1305 .agp_alloc_pages = agp_generic_alloc_pages,
1306 .agp_destroy_page = agp_generic_destroy_page,
1307 .agp_destroy_pages = agp_generic_destroy_pages,
1308 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1309};
1310
1311static const struct agp_bridge_driver intel_fake_agp_driver = { 1234static const struct agp_bridge_driver intel_fake_agp_driver = {
1312 .owner = THIS_MODULE, 1235 .owner = THIS_MODULE,
1313 .size_type = FIXED_APER_SIZE, 1236 .size_type = FIXED_APER_SIZE,
@@ -1328,15 +1251,20 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
1328 .agp_alloc_pages = agp_generic_alloc_pages, 1251 .agp_alloc_pages = agp_generic_alloc_pages,
1329 .agp_destroy_page = agp_generic_destroy_page, 1252 .agp_destroy_page = agp_generic_destroy_page,
1330 .agp_destroy_pages = agp_generic_destroy_pages, 1253 .agp_destroy_pages = agp_generic_destroy_pages,
1331 .chipset_flush = intel_fake_agp_chipset_flush,
1332}; 1254};
1333 1255
1334static const struct intel_gtt_driver i81x_gtt_driver = { 1256static const struct intel_gtt_driver i81x_gtt_driver = {
1335 .gen = 1, 1257 .gen = 1,
1258 .has_pgtbl_enable = 1,
1336 .dma_mask_size = 32, 1259 .dma_mask_size = 32,
1260 .setup = i810_setup,
1261 .cleanup = i810_cleanup,
1262 .check_flags = i830_check_flags,
1263 .write_entry = i810_write_entry,
1337}; 1264};
1338static const struct intel_gtt_driver i8xx_gtt_driver = { 1265static const struct intel_gtt_driver i8xx_gtt_driver = {
1339 .gen = 2, 1266 .gen = 2,
1267 .has_pgtbl_enable = 1,
1340 .setup = i830_setup, 1268 .setup = i830_setup,
1341 .cleanup = i830_cleanup, 1269 .cleanup = i830_cleanup,
1342 .write_entry = i830_write_entry, 1270 .write_entry = i830_write_entry,
@@ -1346,10 +1274,11 @@ static const struct intel_gtt_driver i8xx_gtt_driver = {
1346}; 1274};
1347static const struct intel_gtt_driver i915_gtt_driver = { 1275static const struct intel_gtt_driver i915_gtt_driver = {
1348 .gen = 3, 1276 .gen = 3,
1277 .has_pgtbl_enable = 1,
1349 .setup = i9xx_setup, 1278 .setup = i9xx_setup,
1350 .cleanup = i9xx_cleanup, 1279 .cleanup = i9xx_cleanup,
1351 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1280 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1352 .write_entry = i830_write_entry, 1281 .write_entry = i830_write_entry,
1353 .dma_mask_size = 32, 1282 .dma_mask_size = 32,
1354 .check_flags = i830_check_flags, 1283 .check_flags = i830_check_flags,
1355 .chipset_flush = i9xx_chipset_flush, 1284 .chipset_flush = i9xx_chipset_flush,
@@ -1376,6 +1305,7 @@ static const struct intel_gtt_driver pineview_gtt_driver = {
1376}; 1305};
1377static const struct intel_gtt_driver i965_gtt_driver = { 1306static const struct intel_gtt_driver i965_gtt_driver = {
1378 .gen = 4, 1307 .gen = 4,
1308 .has_pgtbl_enable = 1,
1379 .setup = i9xx_setup, 1309 .setup = i9xx_setup,
1380 .cleanup = i9xx_cleanup, 1310 .cleanup = i9xx_cleanup,
1381 .write_entry = i965_write_entry, 1311 .write_entry = i965_write_entry,
@@ -1419,93 +1349,92 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
1419static const struct intel_gtt_driver_description { 1349static const struct intel_gtt_driver_description {
1420 unsigned int gmch_chip_id; 1350 unsigned int gmch_chip_id;
1421 char *name; 1351 char *name;
1422 const struct agp_bridge_driver *gmch_driver;
1423 const struct intel_gtt_driver *gtt_driver; 1352 const struct intel_gtt_driver *gtt_driver;
1424} intel_gtt_chipsets[] = { 1353} intel_gtt_chipsets[] = {
1425 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver, 1354 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1426 &i81x_gtt_driver}, 1355 &i81x_gtt_driver},
1427 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver, 1356 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1428 &i81x_gtt_driver}, 1357 &i81x_gtt_driver},
1429 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver, 1358 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1430 &i81x_gtt_driver}, 1359 &i81x_gtt_driver},
1431 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver, 1360 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1432 &i81x_gtt_driver}, 1361 &i81x_gtt_driver},
1433 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1362 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1434 &intel_fake_agp_driver, &i8xx_gtt_driver}, 1363 &i8xx_gtt_driver},
1435 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 1364 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1436 &intel_fake_agp_driver, &i8xx_gtt_driver}, 1365 &i8xx_gtt_driver},
1437 { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1366 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1438 &intel_fake_agp_driver, &i8xx_gtt_driver}, 1367 &i8xx_gtt_driver},
1439 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1368 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1440 &intel_fake_agp_driver, &i8xx_gtt_driver}, 1369 &i8xx_gtt_driver},
1441 { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1370 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1442 &intel_fake_agp_driver, &i8xx_gtt_driver}, 1371 &i8xx_gtt_driver},
1443 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1372 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1444 &intel_fake_agp_driver, &i915_gtt_driver }, 1373 &i915_gtt_driver },
1445 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1374 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1446 &intel_fake_agp_driver, &i915_gtt_driver }, 1375 &i915_gtt_driver },
1447 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1376 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1448 &intel_fake_agp_driver, &i915_gtt_driver }, 1377 &i915_gtt_driver },
1449 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1378 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1450 &intel_fake_agp_driver, &i915_gtt_driver }, 1379 &i915_gtt_driver },
1451 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1380 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1452 &intel_fake_agp_driver, &i915_gtt_driver }, 1381 &i915_gtt_driver },
1453 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1382 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1454 &intel_fake_agp_driver, &i915_gtt_driver }, 1383 &i915_gtt_driver },
1455 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1384 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1456 &intel_fake_agp_driver, &i965_gtt_driver }, 1385 &i965_gtt_driver },
1457 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1386 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1458 &intel_fake_agp_driver, &i965_gtt_driver }, 1387 &i965_gtt_driver },
1459 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1388 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1460 &intel_fake_agp_driver, &i965_gtt_driver }, 1389 &i965_gtt_driver },
1461 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1390 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1462 &intel_fake_agp_driver, &i965_gtt_driver }, 1391 &i965_gtt_driver },
1463 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1392 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1464 &intel_fake_agp_driver, &i965_gtt_driver }, 1393 &i965_gtt_driver },
1465 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1394 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1466 &intel_fake_agp_driver, &i965_gtt_driver }, 1395 &i965_gtt_driver },
1467 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1396 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1468 &intel_fake_agp_driver, &g33_gtt_driver }, 1397 &g33_gtt_driver },
1469 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1398 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1470 &intel_fake_agp_driver, &g33_gtt_driver }, 1399 &g33_gtt_driver },
1471 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1400 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1472 &intel_fake_agp_driver, &g33_gtt_driver }, 1401 &g33_gtt_driver },
1473 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1402 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1474 &intel_fake_agp_driver, &pineview_gtt_driver }, 1403 &pineview_gtt_driver },
1475 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1404 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1476 &intel_fake_agp_driver, &pineview_gtt_driver }, 1405 &pineview_gtt_driver },
1477 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1406 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1478 &intel_fake_agp_driver, &g4x_gtt_driver }, 1407 &g4x_gtt_driver },
1479 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1408 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1480 &intel_fake_agp_driver, &g4x_gtt_driver }, 1409 &g4x_gtt_driver },
1481 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1410 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1482 &intel_fake_agp_driver, &g4x_gtt_driver }, 1411 &g4x_gtt_driver },
1483 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1412 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1484 &intel_fake_agp_driver, &g4x_gtt_driver }, 1413 &g4x_gtt_driver },
1485 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1414 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1486 &intel_fake_agp_driver, &g4x_gtt_driver }, 1415 &g4x_gtt_driver },
1487 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1416 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1488 &intel_fake_agp_driver, &g4x_gtt_driver }, 1417 &g4x_gtt_driver },
1489 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1418 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1490 &intel_fake_agp_driver, &g4x_gtt_driver }, 1419 &g4x_gtt_driver },
1491 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1420 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1492 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver }, 1421 "HD Graphics", &ironlake_gtt_driver },
1493 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1422 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1494 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver }, 1423 "HD Graphics", &ironlake_gtt_driver },
1495 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 1424 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1496 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1425 "Sandybridge", &sandybridge_gtt_driver },
1497 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 1426 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1498 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1427 "Sandybridge", &sandybridge_gtt_driver },
1499 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 1428 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1500 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1429 "Sandybridge", &sandybridge_gtt_driver },
1501 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 1430 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1502 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1431 "Sandybridge", &sandybridge_gtt_driver },
1503 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 1432 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1504 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1433 "Sandybridge", &sandybridge_gtt_driver },
1505 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 1434 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1506 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1435 "Sandybridge", &sandybridge_gtt_driver },
1507 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 1436 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1508 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, 1437 "Sandybridge", &sandybridge_gtt_driver },
1509 { 0, NULL, NULL } 1438 { 0, NULL, NULL }
1510}; 1439};
1511 1440
@@ -1530,21 +1459,20 @@ int intel_gmch_probe(struct pci_dev *pdev,
1530 struct agp_bridge_data *bridge) 1459 struct agp_bridge_data *bridge)
1531{ 1460{
1532 int i, mask; 1461 int i, mask;
1533 bridge->driver = NULL; 1462 intel_private.driver = NULL;
1534 1463
1535 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 1464 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1536 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 1465 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1537 bridge->driver = 1466 intel_private.driver =
1538 intel_gtt_chipsets[i].gmch_driver;
1539 intel_private.driver =
1540 intel_gtt_chipsets[i].gtt_driver; 1467 intel_gtt_chipsets[i].gtt_driver;
1541 break; 1468 break;
1542 } 1469 }
1543 } 1470 }
1544 1471
1545 if (!bridge->driver) 1472 if (!intel_private.driver)
1546 return 0; 1473 return 0;
1547 1474
1475 bridge->driver = &intel_fake_agp_driver;
1548 bridge->dev_private_data = &intel_private; 1476 bridge->dev_private_data = &intel_private;
1549 bridge->dev = pdev; 1477 bridge->dev = pdev;
1550 1478
@@ -1560,8 +1488,8 @@ int intel_gmch_probe(struct pci_dev *pdev,
1560 pci_set_consistent_dma_mask(intel_private.pcidev, 1488 pci_set_consistent_dma_mask(intel_private.pcidev,
1561 DMA_BIT_MASK(mask)); 1489 DMA_BIT_MASK(mask));
1562 1490
1563 if (bridge->driver == &intel_810_driver) 1491 /*if (bridge->driver == &intel_810_driver)
1564 return 1; 1492 return 1;*/
1565 1493
1566 if (intel_gtt_init() != 0) 1494 if (intel_gtt_init() != 0)
1567 return 0; 1495 return 0;
@@ -1570,12 +1498,19 @@ int intel_gmch_probe(struct pci_dev *pdev,
1570} 1498}
1571EXPORT_SYMBOL(intel_gmch_probe); 1499EXPORT_SYMBOL(intel_gmch_probe);
1572 1500
1573struct intel_gtt *intel_gtt_get(void) 1501const struct intel_gtt *intel_gtt_get(void)
1574{ 1502{
1575 return &intel_private.base; 1503 return &intel_private.base;
1576} 1504}
1577EXPORT_SYMBOL(intel_gtt_get); 1505EXPORT_SYMBOL(intel_gtt_get);
1578 1506
1507void intel_gtt_chipset_flush(void)
1508{
1509 if (intel_private.driver->chipset_flush)
1510 intel_private.driver->chipset_flush();
1511}
1512EXPORT_SYMBOL(intel_gtt_chipset_flush);
1513
1579void intel_gmch_remove(struct pci_dev *pdev) 1514void intel_gmch_remove(struct pci_dev *pdev)
1580{ 1515{
1581 if (intel_private.pcidev) 1516 if (intel_private.pcidev)
diff --git a/drivers/char/cs5535_gpio.c b/drivers/char/cs5535_gpio.c
deleted file mode 100644
index 0cf1e5fad9ab..000000000000
--- a/drivers/char/cs5535_gpio.c
+++ /dev/null
@@ -1,259 +0,0 @@
1/*
2 * AMD CS5535/CS5536 GPIO driver.
3 * Allows a user space process to play with the GPIO pins.
4 *
5 * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the smems of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/cdev.h>
18#include <linux/ioport.h>
19#include <linux/pci.h>
20
21#include <asm/uaccess.h>
22#include <asm/io.h>
23
24
25#define NAME "cs5535_gpio"
26
27MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
28MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO Pin Driver");
29MODULE_LICENSE("GPL");
30
31static int major;
32module_param(major, int, 0);
33MODULE_PARM_DESC(major, "Major device number");
34
35static ulong mask;
36module_param(mask, ulong, 0);
37MODULE_PARM_DESC(mask, "GPIO channel mask");
38
39#define MSR_LBAR_GPIO 0x5140000C
40
41static u32 gpio_base;
42
43static struct pci_device_id divil_pci[] = {
44 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
45 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
46 { } /* NULL entry */
47};
48MODULE_DEVICE_TABLE(pci, divil_pci);
49
50static struct cdev cs5535_gpio_cdev;
51
52/* reserve 32 entries even though some aren't usable */
53#define CS5535_GPIO_COUNT 32
54
55/* IO block size */
56#define CS5535_GPIO_SIZE 256
57
58struct gpio_regmap {
59 u32 rd_offset;
60 u32 wr_offset;
61 char on;
62 char off;
63};
64static struct gpio_regmap rm[] =
65{
66 { 0x30, 0x00, '1', '0' }, /* GPIOx_READ_BACK / GPIOx_OUT_VAL */
67 { 0x20, 0x20, 'I', 'i' }, /* GPIOx_IN_EN */
68 { 0x04, 0x04, 'O', 'o' }, /* GPIOx_OUT_EN */
69 { 0x08, 0x08, 't', 'T' }, /* GPIOx_OUT_OD_EN */
70 { 0x18, 0x18, 'P', 'p' }, /* GPIOx_OUT_PU_EN */
71 { 0x1c, 0x1c, 'D', 'd' }, /* GPIOx_OUT_PD_EN */
72};
73
74
75/**
76 * Gets the register offset for the GPIO bank.
77 * Low (0-15) starts at 0x00, high (16-31) starts at 0x80
78 */
79static inline u32 cs5535_lowhigh_base(int reg)
80{
81 return (reg & 0x10) << 3;
82}
83
84static ssize_t cs5535_gpio_write(struct file *file, const char __user *data,
85 size_t len, loff_t *ppos)
86{
87 u32 m = iminor(file->f_path.dentry->d_inode);
88 int i, j;
89 u32 base = gpio_base + cs5535_lowhigh_base(m);
90 u32 m0, m1;
91 char c;
92
93 /**
94 * Creates the mask for atomic bit programming.
95 * The high 16 bits and the low 16 bits are used to set the mask.
96 * For example, GPIO 15 maps to 31,15: 0,1 => On; 1,0=> Off
97 */
98 m1 = 1 << (m & 0x0F);
99 m0 = m1 << 16;
100
101 for (i = 0; i < len; ++i) {
102 if (get_user(c, data+i))
103 return -EFAULT;
104
105 for (j = 0; j < ARRAY_SIZE(rm); j++) {
106 if (c == rm[j].on) {
107 outl(m1, base + rm[j].wr_offset);
108 /* If enabling output, turn off AUX 1 and AUX 2 */
109 if (c == 'O') {
110 outl(m0, base + 0x10);
111 outl(m0, base + 0x14);
112 }
113 break;
114 } else if (c == rm[j].off) {
115 outl(m0, base + rm[j].wr_offset);
116 break;
117 }
118 }
119 }
120 *ppos = 0;
121 return len;
122}
123
124static ssize_t cs5535_gpio_read(struct file *file, char __user *buf,
125 size_t len, loff_t *ppos)
126{
127 u32 m = iminor(file->f_path.dentry->d_inode);
128 u32 base = gpio_base + cs5535_lowhigh_base(m);
129 int rd_bit = 1 << (m & 0x0f);
130 int i;
131 char ch;
132 ssize_t count = 0;
133
134 if (*ppos >= ARRAY_SIZE(rm))
135 return 0;
136
137 for (i = *ppos; (i < (*ppos + len)) && (i < ARRAY_SIZE(rm)); i++) {
138 ch = (inl(base + rm[i].rd_offset) & rd_bit) ?
139 rm[i].on : rm[i].off;
140
141 if (put_user(ch, buf+count))
142 return -EFAULT;
143
144 count++;
145 }
146
147 /* add a line-feed if there is room */
148 if ((i == ARRAY_SIZE(rm)) && (count < len)) {
149 put_user('\n', buf + count);
150 count++;
151 }
152
153 *ppos += count;
154 return count;
155}
156
157static int cs5535_gpio_open(struct inode *inode, struct file *file)
158{
159 u32 m = iminor(inode);
160
161 /* the mask says which pins are usable by this driver */
162 if ((mask & (1 << m)) == 0)
163 return -EINVAL;
164
165 return nonseekable_open(inode, file);
166}
167
168static const struct file_operations cs5535_gpio_fops = {
169 .owner = THIS_MODULE,
170 .write = cs5535_gpio_write,
171 .read = cs5535_gpio_read,
172 .open = cs5535_gpio_open,
173 .llseek = no_llseek,
174};
175
176static int __init cs5535_gpio_init(void)
177{
178 dev_t dev_id;
179 u32 low, hi;
180 int retval;
181
182 if (pci_dev_present(divil_pci) == 0) {
183 printk(KERN_WARNING NAME ": DIVIL not found\n");
184 return -ENODEV;
185 }
186
187 /* Grab the GPIO I/O range */
188 rdmsr(MSR_LBAR_GPIO, low, hi);
189
190 /* Check the mask and whether GPIO is enabled (sanity check) */
191 if (hi != 0x0000f001) {
192 printk(KERN_WARNING NAME ": GPIO not enabled\n");
193 return -ENODEV;
194 }
195
196 /* Mask off the IO base address */
197 gpio_base = low & 0x0000ff00;
198
199 /**
200 * Some GPIO pins
201 * 31-29,23 : reserved (always mask out)
202 * 28 : Power Button
203 * 26 : PME#
204 * 22-16 : LPC
205 * 14,15 : SMBus
206 * 9,8 : UART1
207 * 7 : PCI INTB
208 * 3,4 : UART2/DDC
209 * 2 : IDE_IRQ0
210 * 0 : PCI INTA
211 *
212 * If a mask was not specified, be conservative and only allow:
213 * 1,2,5,6,10-13,24,25,27
214 */
215 if (mask != 0)
216 mask &= 0x1f7fffff;
217 else
218 mask = 0x0b003c66;
219
220 if (!request_region(gpio_base, CS5535_GPIO_SIZE, NAME)) {
221 printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n");
222 return -ENODEV;
223 }
224
225 if (major) {
226 dev_id = MKDEV(major, 0);
227 retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT,
228 NAME);
229 } else {
230 retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT,
231 NAME);
232 major = MAJOR(dev_id);
233 }
234
235 if (retval) {
236 release_region(gpio_base, CS5535_GPIO_SIZE);
237 return -1;
238 }
239
240 printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n",
241 gpio_base, mask, major);
242
243 cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops);
244 cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT);
245
246 return 0;
247}
248
249static void __exit cs5535_gpio_cleanup(void)
250{
251 dev_t dev_id = MKDEV(major, 0);
252
253 cdev_del(&cs5535_gpio_cdev);
254 unregister_chrdev_region(dev_id, CS5535_GPIO_COUNT);
255 release_region(gpio_base, CS5535_GPIO_SIZE);
256}
257
258module_init(cs5535_gpio_init);
259module_exit(cs5535_gpio_cleanup);
diff --git a/drivers/char/hvc_vio.c b/drivers/char/hvc_vio.c
index 27370e99c66f..5e2f52b33327 100644
--- a/drivers/char/hvc_vio.c
+++ b/drivers/char/hvc_vio.c
@@ -39,7 +39,7 @@
39 39
40#include "hvc_console.h" 40#include "hvc_console.h"
41 41
42char hvc_driver_name[] = "hvc_console"; 42static const char hvc_driver_name[] = "hvc_console";
43 43
44static struct vio_device_id hvc_driver_table[] __devinitdata = { 44static struct vio_device_id hvc_driver_table[] __devinitdata = {
45 {"serial", "hvterm1"}, 45 {"serial", "hvterm1"},
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index 794aacb715c1..d0387a84eec1 100644
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -24,6 +24,7 @@
24 * warranty of any kind, whether express or implied. 24 * warranty of any kind, whether express or implied.
25 */ 25 */
26 26
27#include <crypto/padlock.h>
27#include <linux/module.h> 28#include <linux/module.h>
28#include <linux/kernel.h> 29#include <linux/kernel.h>
29#include <linux/hw_random.h> 30#include <linux/hw_random.h>
@@ -34,7 +35,6 @@
34#include <asm/i387.h> 35#include <asm/i387.h>
35 36
36 37
37#define PFX KBUILD_MODNAME ": "
38 38
39 39
40enum { 40enum {
@@ -81,8 +81,7 @@ static inline u32 xstore(u32 *addr, u32 edx_in)
81 ts_state = irq_ts_save(); 81 ts_state = irq_ts_save();
82 82
83 asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */" 83 asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
84 :"=m"(*addr), "=a"(eax_out) 84 : "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr));
85 :"D"(addr), "d"(edx_in));
86 85
87 irq_ts_restore(ts_state); 86 irq_ts_restore(ts_state);
88 return eax_out; 87 return eax_out;
@@ -90,8 +89,10 @@ static inline u32 xstore(u32 *addr, u32 edx_in)
90 89
91static int via_rng_data_present(struct hwrng *rng, int wait) 90static int via_rng_data_present(struct hwrng *rng, int wait)
92{ 91{
92 char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
93 ((aligned(STACK_ALIGN)));
94 u32 *via_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
93 u32 bytes_out; 95 u32 bytes_out;
94 u32 *via_rng_datum = (u32 *)(&rng->priv);
95 int i; 96 int i;
96 97
97 /* We choose the recommended 1-byte-per-instruction RNG rate, 98 /* We choose the recommended 1-byte-per-instruction RNG rate,
@@ -115,6 +116,7 @@ static int via_rng_data_present(struct hwrng *rng, int wait)
115 break; 116 break;
116 udelay(10); 117 udelay(10);
117 } 118 }
119 rng->priv = *via_rng_datum;
118 return bytes_out ? 1 : 0; 120 return bytes_out ? 1 : 0;
119} 121}
120 122
diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c
index 2fe72f8edf44..38223e93aa98 100644
--- a/drivers/char/ipmi/ipmi_msghandler.c
+++ b/drivers/char/ipmi/ipmi_msghandler.c
@@ -970,6 +970,33 @@ out_kfree:
970} 970}
971EXPORT_SYMBOL(ipmi_create_user); 971EXPORT_SYMBOL(ipmi_create_user);
972 972
973int ipmi_get_smi_info(int if_num, struct ipmi_smi_info *data)
974{
975 int rv = 0;
976 ipmi_smi_t intf;
977 struct ipmi_smi_handlers *handlers;
978
979 mutex_lock(&ipmi_interfaces_mutex);
980 list_for_each_entry_rcu(intf, &ipmi_interfaces, link) {
981 if (intf->intf_num == if_num)
982 goto found;
983 }
984 /* Not found, return an error */
985 rv = -EINVAL;
986 mutex_unlock(&ipmi_interfaces_mutex);
987 return rv;
988
989found:
990 handlers = intf->handlers;
991 rv = -ENOSYS;
992 if (handlers->get_smi_info)
993 rv = handlers->get_smi_info(intf->send_info, data);
994 mutex_unlock(&ipmi_interfaces_mutex);
995
996 return rv;
997}
998EXPORT_SYMBOL(ipmi_get_smi_info);
999
973static void free_user(struct kref *ref) 1000static void free_user(struct kref *ref)
974{ 1001{
975 ipmi_user_t user = container_of(ref, struct ipmi_user, refcount); 1002 ipmi_user_t user = container_of(ref, struct ipmi_user, refcount);
diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c
index 035da9e64a17..b6ae6e9a9c5f 100644
--- a/drivers/char/ipmi/ipmi_si_intf.c
+++ b/drivers/char/ipmi/ipmi_si_intf.c
@@ -57,6 +57,7 @@
57#include <asm/irq.h> 57#include <asm/irq.h>
58#include <linux/interrupt.h> 58#include <linux/interrupt.h>
59#include <linux/rcupdate.h> 59#include <linux/rcupdate.h>
60#include <linux/ipmi.h>
60#include <linux/ipmi_smi.h> 61#include <linux/ipmi_smi.h>
61#include <asm/io.h> 62#include <asm/io.h>
62#include "ipmi_si_sm.h" 63#include "ipmi_si_sm.h"
@@ -69,6 +70,8 @@
69#ifdef CONFIG_PPC_OF 70#ifdef CONFIG_PPC_OF
70#include <linux/of_device.h> 71#include <linux/of_device.h>
71#include <linux/of_platform.h> 72#include <linux/of_platform.h>
73#include <linux/of_address.h>
74#include <linux/of_irq.h>
72#endif 75#endif
73 76
74#define PFX "ipmi_si: " 77#define PFX "ipmi_si: "
@@ -107,10 +110,6 @@ enum si_type {
107}; 110};
108static char *si_to_str[] = { "kcs", "smic", "bt" }; 111static char *si_to_str[] = { "kcs", "smic", "bt" };
109 112
110enum ipmi_addr_src {
111 SI_INVALID = 0, SI_HOTMOD, SI_HARDCODED, SI_SPMI, SI_ACPI, SI_SMBIOS,
112 SI_PCI, SI_DEVICETREE, SI_DEFAULT
113};
114static char *ipmi_addr_src_to_str[] = { NULL, "hotmod", "hardcoded", "SPMI", 113static char *ipmi_addr_src_to_str[] = { NULL, "hotmod", "hardcoded", "SPMI",
115 "ACPI", "SMBIOS", "PCI", 114 "ACPI", "SMBIOS", "PCI",
116 "device-tree", "default" }; 115 "device-tree", "default" };
@@ -291,6 +290,7 @@ struct smi_info {
291 struct task_struct *thread; 290 struct task_struct *thread;
292 291
293 struct list_head link; 292 struct list_head link;
293 union ipmi_smi_info_union addr_info;
294}; 294};
295 295
296#define smi_inc_stat(smi, stat) \ 296#define smi_inc_stat(smi, stat) \
@@ -1186,6 +1186,18 @@ static int smi_start_processing(void *send_info,
1186 return 0; 1186 return 0;
1187} 1187}
1188 1188
1189static int get_smi_info(void *send_info, struct ipmi_smi_info *data)
1190{
1191 struct smi_info *smi = send_info;
1192
1193 data->addr_src = smi->addr_source;
1194 data->dev = smi->dev;
1195 data->addr_info = smi->addr_info;
1196 get_device(smi->dev);
1197
1198 return 0;
1199}
1200
1189static void set_maintenance_mode(void *send_info, int enable) 1201static void set_maintenance_mode(void *send_info, int enable)
1190{ 1202{
1191 struct smi_info *smi_info = send_info; 1203 struct smi_info *smi_info = send_info;
@@ -1197,6 +1209,7 @@ static void set_maintenance_mode(void *send_info, int enable)
1197static struct ipmi_smi_handlers handlers = { 1209static struct ipmi_smi_handlers handlers = {
1198 .owner = THIS_MODULE, 1210 .owner = THIS_MODULE,
1199 .start_processing = smi_start_processing, 1211 .start_processing = smi_start_processing,
1212 .get_smi_info = get_smi_info,
1200 .sender = sender, 1213 .sender = sender,
1201 .request_events = request_events, 1214 .request_events = request_events,
1202 .set_maintenance_mode = set_maintenance_mode, 1215 .set_maintenance_mode = set_maintenance_mode,
@@ -1928,7 +1941,8 @@ static void __devinit hardcode_find_bmc(void)
1928static int acpi_failure; 1941static int acpi_failure;
1929 1942
1930/* For GPE-type interrupts. */ 1943/* For GPE-type interrupts. */
1931static u32 ipmi_acpi_gpe(void *context) 1944static u32 ipmi_acpi_gpe(acpi_handle gpe_device,
1945 u32 gpe_number, void *context)
1932{ 1946{
1933 struct smi_info *smi_info = context; 1947 struct smi_info *smi_info = context;
1934 unsigned long flags; 1948 unsigned long flags;
@@ -2156,6 +2170,7 @@ static int __devinit ipmi_pnp_probe(struct pnp_dev *dev,
2156 printk(KERN_INFO PFX "probing via ACPI\n"); 2170 printk(KERN_INFO PFX "probing via ACPI\n");
2157 2171
2158 handle = acpi_dev->handle; 2172 handle = acpi_dev->handle;
2173 info->addr_info.acpi_info.acpi_handle = handle;
2159 2174
2160 /* _IFT tells us the interface type: KCS, BT, etc */ 2175 /* _IFT tells us the interface type: KCS, BT, etc */
2161 status = acpi_evaluate_integer(handle, "_IFT", NULL, &tmp); 2176 status = acpi_evaluate_integer(handle, "_IFT", NULL, &tmp);
@@ -2546,7 +2561,7 @@ static int __devinit ipmi_of_probe(struct platform_device *dev,
2546{ 2561{
2547 struct smi_info *info; 2562 struct smi_info *info;
2548 struct resource resource; 2563 struct resource resource;
2549 const int *regsize, *regspacing, *regshift; 2564 const __be32 *regsize, *regspacing, *regshift;
2550 struct device_node *np = dev->dev.of_node; 2565 struct device_node *np = dev->dev.of_node;
2551 int ret; 2566 int ret;
2552 int proplen; 2567 int proplen;
@@ -2599,9 +2614,9 @@ static int __devinit ipmi_of_probe(struct platform_device *dev,
2599 2614
2600 info->io.addr_data = resource.start; 2615 info->io.addr_data = resource.start;
2601 2616
2602 info->io.regsize = regsize ? *regsize : DEFAULT_REGSIZE; 2617 info->io.regsize = regsize ? be32_to_cpup(regsize) : DEFAULT_REGSIZE;
2603 info->io.regspacing = regspacing ? *regspacing : DEFAULT_REGSPACING; 2618 info->io.regspacing = regspacing ? be32_to_cpup(regspacing) : DEFAULT_REGSPACING;
2604 info->io.regshift = regshift ? *regshift : 0; 2619 info->io.regshift = regshift ? be32_to_cpup(regshift) : 0;
2605 2620
2606 info->irq = irq_of_parse_and_map(dev->dev.of_node, 0); 2621 info->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
2607 info->dev = &dev->dev; 2622 info->dev = &dev->dev;
diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_watchdog.c
index f4d334f2536e..320668f4c3aa 100644
--- a/drivers/char/ipmi/ipmi_watchdog.c
+++ b/drivers/char/ipmi/ipmi_watchdog.c
@@ -1081,7 +1081,7 @@ ipmi_nmi(struct notifier_block *self, unsigned long val, void *data)
1081{ 1081{
1082 struct die_args *args = data; 1082 struct die_args *args = data;
1083 1083
1084 if (val != DIE_NMI) 1084 if (val != DIE_NMIUNKNOWN)
1085 return NOTIFY_OK; 1085 return NOTIFY_OK;
1086 1086
1087 /* Hack, if it's a memory or I/O error, ignore it. */ 1087 /* Hack, if it's a memory or I/O error, ignore it. */
diff --git a/drivers/char/ramoops.c b/drivers/char/ramoops.c
index d3d63be2cd37..1a9f5f6d6ac5 100644
--- a/drivers/char/ramoops.c
+++ b/drivers/char/ramoops.c
@@ -30,7 +30,7 @@
30 30
31#define RAMOOPS_KERNMSG_HDR "====" 31#define RAMOOPS_KERNMSG_HDR "===="
32 32
33#define RECORD_SIZE 4096 33#define RECORD_SIZE 4096UL
34 34
35static ulong mem_address; 35static ulong mem_address;
36module_param(mem_address, ulong, 0400); 36module_param(mem_address, ulong, 0400);
@@ -68,11 +68,16 @@ static void ramoops_do_dump(struct kmsg_dumper *dumper,
68 char *buf, *buf_orig; 68 char *buf, *buf_orig;
69 struct timeval timestamp; 69 struct timeval timestamp;
70 70
71 if (reason != KMSG_DUMP_OOPS &&
72 reason != KMSG_DUMP_PANIC &&
73 reason != KMSG_DUMP_KEXEC)
74 return;
75
71 /* Only dump oopses if dump_oops is set */ 76 /* Only dump oopses if dump_oops is set */
72 if (reason == KMSG_DUMP_OOPS && !dump_oops) 77 if (reason == KMSG_DUMP_OOPS && !dump_oops)
73 return; 78 return;
74 79
75 buf = (char *)(cxt->virt_addr + (cxt->count * RECORD_SIZE)); 80 buf = cxt->virt_addr + (cxt->count * RECORD_SIZE);
76 buf_orig = buf; 81 buf_orig = buf;
77 82
78 memset(buf, '\0', RECORD_SIZE); 83 memset(buf, '\0', RECORD_SIZE);
@@ -83,8 +88,8 @@ static void ramoops_do_dump(struct kmsg_dumper *dumper,
83 buf += res; 88 buf += res;
84 89
85 hdr_size = buf - buf_orig; 90 hdr_size = buf - buf_orig;
86 l2_cpy = min(l2, (unsigned long)(RECORD_SIZE - hdr_size)); 91 l2_cpy = min(l2, RECORD_SIZE - hdr_size);
87 l1_cpy = min(l1, (unsigned long)(RECORD_SIZE - hdr_size) - l2_cpy); 92 l1_cpy = min(l1, RECORD_SIZE - hdr_size - l2_cpy);
88 93
89 s2_start = l2 - l2_cpy; 94 s2_start = l2 - l2_cpy;
90 s1_start = l1 - l1_cpy; 95 s1_start = l1 - l1_cpy;
diff --git a/drivers/char/raw.c b/drivers/char/raw.c
index bfe25ea9766b..b4b9d5a47885 100644
--- a/drivers/char/raw.c
+++ b/drivers/char/raw.c
@@ -65,15 +65,12 @@ static int raw_open(struct inode *inode, struct file *filp)
65 if (!bdev) 65 if (!bdev)
66 goto out; 66 goto out;
67 igrab(bdev->bd_inode); 67 igrab(bdev->bd_inode);
68 err = blkdev_get(bdev, filp->f_mode); 68 err = blkdev_get(bdev, filp->f_mode | FMODE_EXCL, raw_open);
69 if (err) 69 if (err)
70 goto out; 70 goto out;
71 err = bd_claim(bdev, raw_open);
72 if (err)
73 goto out1;
74 err = set_blocksize(bdev, bdev_logical_block_size(bdev)); 71 err = set_blocksize(bdev, bdev_logical_block_size(bdev));
75 if (err) 72 if (err)
76 goto out2; 73 goto out1;
77 filp->f_flags |= O_DIRECT; 74 filp->f_flags |= O_DIRECT;
78 filp->f_mapping = bdev->bd_inode->i_mapping; 75 filp->f_mapping = bdev->bd_inode->i_mapping;
79 if (++raw_devices[minor].inuse == 1) 76 if (++raw_devices[minor].inuse == 1)
@@ -83,10 +80,8 @@ static int raw_open(struct inode *inode, struct file *filp)
83 mutex_unlock(&raw_mutex); 80 mutex_unlock(&raw_mutex);
84 return 0; 81 return 0;
85 82
86out2:
87 bd_release(bdev);
88out1: 83out1:
89 blkdev_put(bdev, filp->f_mode); 84 blkdev_put(bdev, filp->f_mode | FMODE_EXCL);
90out: 85out:
91 mutex_unlock(&raw_mutex); 86 mutex_unlock(&raw_mutex);
92 return err; 87 return err;
@@ -110,8 +105,7 @@ static int raw_release(struct inode *inode, struct file *filp)
110 } 105 }
111 mutex_unlock(&raw_mutex); 106 mutex_unlock(&raw_mutex);
112 107
113 bd_release(bdev); 108 blkdev_put(bdev, filp->f_mode | FMODE_EXCL);
114 blkdev_put(bdev, filp->f_mode);
115 return 0; 109 return 0;
116} 110}
117 111
diff --git a/drivers/char/snsc.h b/drivers/char/snsc.h
index 4be62eda9fbc..e8c52c882b21 100644
--- a/drivers/char/snsc.h
+++ b/drivers/char/snsc.h
@@ -19,7 +19,6 @@
19#include <linux/types.h> 19#include <linux/types.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <linux/wait.h> 21#include <linux/wait.h>
22#include <linux/kobject.h>
23#include <linux/fs.h> 22#include <linux/fs.h>
24#include <linux/cdev.h> 23#include <linux/cdev.h>
25#include <linux/semaphore.h> 24#include <linux/semaphore.h>
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c
index 0b3af3fe6766..1f46f1cd9225 100644
--- a/drivers/char/tpm/tpm.c
+++ b/drivers/char/tpm/tpm.c
@@ -736,7 +736,7 @@ int tpm_pcr_read(u32 chip_num, int pcr_idx, u8 *res_buf)
736 if (chip == NULL) 736 if (chip == NULL)
737 return -ENODEV; 737 return -ENODEV;
738 rc = __tpm_pcr_read(chip, pcr_idx, res_buf); 738 rc = __tpm_pcr_read(chip, pcr_idx, res_buf);
739 module_put(chip->dev->driver->owner); 739 tpm_chip_put(chip);
740 return rc; 740 return rc;
741} 741}
742EXPORT_SYMBOL_GPL(tpm_pcr_read); 742EXPORT_SYMBOL_GPL(tpm_pcr_read);
@@ -775,11 +775,27 @@ int tpm_pcr_extend(u32 chip_num, int pcr_idx, const u8 *hash)
775 rc = transmit_cmd(chip, &cmd, EXTEND_PCR_RESULT_SIZE, 775 rc = transmit_cmd(chip, &cmd, EXTEND_PCR_RESULT_SIZE,
776 "attempting extend a PCR value"); 776 "attempting extend a PCR value");
777 777
778 module_put(chip->dev->driver->owner); 778 tpm_chip_put(chip);
779 return rc; 779 return rc;
780} 780}
781EXPORT_SYMBOL_GPL(tpm_pcr_extend); 781EXPORT_SYMBOL_GPL(tpm_pcr_extend);
782 782
783int tpm_send(u32 chip_num, void *cmd, size_t buflen)
784{
785 struct tpm_chip *chip;
786 int rc;
787
788 chip = tpm_chip_find_get(chip_num);
789 if (chip == NULL)
790 return -ENODEV;
791
792 rc = transmit_cmd(chip, cmd, buflen, "attempting tpm_cmd");
793
794 tpm_chip_put(chip);
795 return rc;
796}
797EXPORT_SYMBOL_GPL(tpm_send);
798
783ssize_t tpm_show_pcrs(struct device *dev, struct device_attribute *attr, 799ssize_t tpm_show_pcrs(struct device *dev, struct device_attribute *attr,
784 char *buf) 800 char *buf)
785{ 801{
diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
index 792868d24f2a..72ddb031b69a 100644
--- a/drivers/char/tpm/tpm.h
+++ b/drivers/char/tpm/tpm.h
@@ -113,6 +113,11 @@ struct tpm_chip {
113 113
114#define to_tpm_chip(n) container_of(n, struct tpm_chip, vendor) 114#define to_tpm_chip(n) container_of(n, struct tpm_chip, vendor)
115 115
116static inline void tpm_chip_put(struct tpm_chip *chip)
117{
118 module_put(chip->dev->driver->owner);
119}
120
116static inline int tpm_read_index(int base, int index) 121static inline int tpm_read_index(int base, int index)
117{ 122{
118 outb(index, base); 123 outb(index, base);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 00:21:19 -0500