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authorVladimir Barinov <vbarinov@ru.mvista.com>2007-06-12 10:09:50 -0400
committerWim Van Sebroeck <wim@iguana.be>2007-07-23 13:22:21 -0400
commit7d831bf59a6991f399170bd2934dad4450891024 (patch)
treee0e6d8e5f51f00b3e4a725a32d1153abe81831bb /drivers/char/watchdog
parent1e6d320f40685694708cef872edb10f4f9175989 (diff)
[WATCHDOG] davinci watchdog driver
Add watchdog support for TI Davinci DM644x/DM646x processors. Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/char/watchdog')
-rw-r--r--drivers/char/watchdog/Kconfig12
-rw-r--r--drivers/char/watchdog/Makefile1
-rw-r--r--drivers/char/watchdog/davinci_wdt.c284
3 files changed, 297 insertions, 0 deletions
diff --git a/drivers/char/watchdog/Kconfig b/drivers/char/watchdog/Kconfig
index 2dfaf969f1a9..d9c2eb055f0e 100644
--- a/drivers/char/watchdog/Kconfig
+++ b/drivers/char/watchdog/Kconfig
@@ -203,6 +203,18 @@ config IOP_WATCHDOG
203 operating as an Root Complex and/or Central Resource, the PCI-X 203 operating as an Root Complex and/or Central Resource, the PCI-X
204 and/or PCIe busses will also be reset. THIS IS A VERY BIG HAMMER. 204 and/or PCIe busses will also be reset. THIS IS A VERY BIG HAMMER.
205 205
206config DAVINCI_WATCHDOG
207 tristate "DaVinci watchdog"
208 depends on WATCHDOG && ARCH_DAVINCI
209 help
210 Say Y here if to include support for the watchdog timer
211 in the DaVinci DM644x/DM646x processors.
212 To compile this driver as a module, choose M here: the
213 module will be called davinci_wdt.
214
215 NOTE: once enabled, this timer cannot be disabled.
216 Say N if you are unsure.
217
206# AVR32 Architecture 218# AVR32 Architecture
207 219
208config AT32AP700X_WDT 220config AT32AP700X_WDT
diff --git a/drivers/char/watchdog/Makefile b/drivers/char/watchdog/Makefile
index 6f2342ee380f..edbf30eecdf6 100644
--- a/drivers/char/watchdog/Makefile
+++ b/drivers/char/watchdog/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
36obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o 36obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
37obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o 37obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
38obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o 38obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
39obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
39 40
40# AVR32 Architecture 41# AVR32 Architecture
41obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o 42obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/char/watchdog/davinci_wdt.c b/drivers/char/watchdog/davinci_wdt.c
new file mode 100644
index 000000000000..27b4f66c000b
--- /dev/null
+++ b/drivers/char/watchdog/davinci_wdt.c
@@ -0,0 +1,284 @@
1/*
2 * drivers/char/watchdog/davinci_wdt.c
3 *
4 * Watchdog driver for DaVinci DM644x/DM646x processors
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 *
8 * 2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/fs.h>
19#include <linux/miscdevice.h>
20#include <linux/watchdog.h>
21#include <linux/init.h>
22#include <linux/bitops.h>
23#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25
26#include <asm/hardware.h>
27#include <asm/uaccess.h>
28#include <asm/io.h>
29
30#define MODULE_NAME "DAVINCI-WDT: "
31
32#define DEFAULT_HEARTBEAT 60
33#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
34
35/* Timer register set definition */
36#define PID12 (0x0)
37#define EMUMGT (0x4)
38#define TIM12 (0x10)
39#define TIM34 (0x14)
40#define PRD12 (0x18)
41#define PRD34 (0x1C)
42#define TCR (0x20)
43#define TGCR (0x24)
44#define WDTCR (0x28)
45
46/* TCR bit definitions */
47#define ENAMODE12_DISABLED (0 << 6)
48#define ENAMODE12_ONESHOT (1 << 6)
49#define ENAMODE12_PERIODIC (2 << 6)
50
51/* TGCR bit definitions */
52#define TIM12RS_UNRESET (1 << 0)
53#define TIM34RS_UNRESET (1 << 1)
54#define TIMMODE_64BIT_WDOG (2 << 2)
55
56/* WDTCR bit definitions */
57#define WDEN (1 << 14)
58#define WDFLAG (1 << 15)
59#define WDKEY_SEQ0 (0xa5c6 << 16)
60#define WDKEY_SEQ1 (0xda7e << 16)
61
62static int heartbeat = DEFAULT_HEARTBEAT;
63
64static spinlock_t io_lock;
65static unsigned long wdt_status;
66#define WDT_IN_USE 0
67#define WDT_OK_TO_CLOSE 1
68#define WDT_REGION_INITED 2
69#define WDT_DEVICE_INITED 3
70
71static struct resource *wdt_mem;
72static void __iomem *wdt_base;
73
74static void wdt_service(void)
75{
76 spin_lock(&io_lock);
77
78 /* put watchdog in service state */
79 davinci_writel(WDKEY_SEQ0, wdt_base + WDTCR);
80 /* put watchdog in active state */
81 davinci_writel(WDKEY_SEQ1, wdt_base + WDTCR);
82
83 spin_unlock(&io_lock);
84}
85
86static void wdt_enable(void)
87{
88 u32 tgcr;
89 u32 timer_margin;
90
91 spin_lock(&io_lock);
92
93 /* disable, internal clock source */
94 davinci_writel(0, wdt_base + TCR);
95 /* reset timer, set mode to 64-bit watchdog, and unreset */
96 davinci_writel(0, wdt_base + TGCR);
97 tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
98 davinci_writel(tgcr, wdt_base + TGCR);
99 /* clear counter regs */
100 davinci_writel(0, wdt_base + TIM12);
101 davinci_writel(0, wdt_base + TIM34);
102 /* set timeout period */
103 timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff);
104 davinci_writel(timer_margin, wdt_base + PRD12);
105 timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32);
106 davinci_writel(timer_margin, wdt_base + PRD34);
107 /* enable run continuously */
108 davinci_writel(ENAMODE12_PERIODIC, wdt_base + TCR);
109 /* Once the WDT is in pre-active state write to
110 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
111 * write protected (except for the WDKEY field)
112 */
113 /* put watchdog in pre-active state */
114 davinci_writel(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
115 /* put watchdog in active state */
116 davinci_writel(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
117
118 spin_unlock(&io_lock);
119}
120
121static int davinci_wdt_open(struct inode *inode, struct file *file)
122{
123 if (test_and_set_bit(WDT_IN_USE, &wdt_status))
124 return -EBUSY;
125
126 wdt_enable();
127
128 return nonseekable_open(inode, file);
129}
130
131static ssize_t
132davinci_wdt_write(struct file *file, const char *data, size_t len,
133 loff_t *ppos)
134{
135 /* Can't seek (pwrite) on this device */
136 if (ppos != &file->f_pos)
137 return -ESPIPE;
138
139 if (len)
140 wdt_service();
141
142 return len;
143}
144
145static struct watchdog_info ident = {
146 .options = WDIOF_CARDRESET | WDIOF_KEEPALIVEPING,
147 .identity = "DaVinci Watchdog",
148};
149
150static int
151davinci_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
152 unsigned long arg)
153{
154 int ret = -ENOTTY;
155
156 switch (cmd) {
157 case WDIOC_GETSUPPORT:
158 ret = copy_to_user((struct watchdog_info *)arg, &ident,
159 sizeof(ident)) ? -EFAULT : 0;
160 break;
161
162 case WDIOC_GETSTATUS:
163 ret = put_user(0, (int *)arg);
164 break;
165
166 case WDIOC_GETTIMEOUT:
167 ret = put_user(heartbeat, (int *)arg);
168 break;
169
170 case WDIOC_KEEPALIVE:
171 wdt_service();
172 ret = 0;
173 break;
174 }
175 return ret;
176}
177
178static int davinci_wdt_release(struct inode *inode, struct file *file)
179{
180 wdt_service();
181 clear_bit(WDT_IN_USE, &wdt_status);
182
183 return 0;
184}
185
186static const struct file_operations davinci_wdt_fops = {
187 .owner = THIS_MODULE,
188 .llseek = no_llseek,
189 .write = davinci_wdt_write,
190 .ioctl = davinci_wdt_ioctl,
191 .open = davinci_wdt_open,
192 .release = davinci_wdt_release,
193};
194
195static struct miscdevice davinci_wdt_miscdev = {
196 .minor = WATCHDOG_MINOR,
197 .name = "watchdog",
198 .fops = &davinci_wdt_fops,
199};
200
201static int davinci_wdt_probe(struct platform_device *pdev)
202{
203 int ret = 0, size;
204 struct resource *res;
205
206 spin_lock_init(&io_lock);
207
208 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
209 heartbeat = DEFAULT_HEARTBEAT;
210
211 printk(KERN_INFO MODULE_NAME
212 "DaVinci Watchdog Timer: heartbeat %d sec\n", heartbeat);
213
214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215 if (res == NULL) {
216 printk(KERN_INFO MODULE_NAME
217 "failed to get memory region resource\n");
218 return -ENOENT;
219 }
220
221 size = res->end - res->start + 1;
222 wdt_mem = request_mem_region(res->start, size, pdev->name);
223
224 if (wdt_mem == NULL) {
225 printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
226 return -ENOENT;
227 }
228 wdt_base = (void __iomem *)(res->start);
229
230 ret = misc_register(&davinci_wdt_miscdev);
231 if (ret < 0) {
232 printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
233 release_resource(wdt_mem);
234 kfree(wdt_mem);
235 } else {
236 set_bit(WDT_DEVICE_INITED, &wdt_status);
237 }
238
239 return ret;
240}
241
242static int davinci_wdt_remove(struct platform_device *pdev)
243{
244 misc_deregister(&davinci_wdt_miscdev);
245 if (wdt_mem) {
246 release_resource(wdt_mem);
247 kfree(wdt_mem);
248 wdt_mem = NULL;
249 }
250 return 0;
251}
252
253static struct platform_driver platform_wdt_driver = {
254 .driver = {
255 .name = "watchdog",
256 },
257 .probe = davinci_wdt_probe,
258 .remove = davinci_wdt_remove,
259};
260
261static int __init davinci_wdt_init(void)
262{
263 return platform_driver_register(&platform_wdt_driver);
264}
265
266static void __exit davinci_wdt_exit(void)
267{
268 return platform_driver_unregister(&platform_wdt_driver);
269}
270
271module_init(davinci_wdt_init);
272module_exit(davinci_wdt_exit);
273
274MODULE_AUTHOR("Texas Instruments");
275MODULE_DESCRIPTION("DaVinci Watchdog Driver");
276
277module_param(heartbeat, int, 0);
278MODULE_PARM_DESC(heartbeat,
279 "Watchdog heartbeat period in seconds from 1 to "
280 __MODULE_STRING(MAX_HEARTBEAT) ", default "
281 __MODULE_STRING(DEFAULT_HEARTBEAT));
282
283MODULE_LICENSE("GPL");
284MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);