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authorBen Widawsky <ben@bwidawsk.net>2013-01-18 15:30:31 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-01-20 07:11:11 -0500
commita81cc00c11ab6816fbcb7dd99a60b50e71765d25 (patch)
tree506c92848c259bfa397e69d805508511e2024458 /drivers/char/agp/intel-gtt.c
parentabedc077b45eff0b5a8630af8431ad5d59213582 (diff)
drm/i915: Cut out the infamous ILK w/a from AGP layer
And, move it to where the rest of the logic is. There is some slight functionality changes. There was extra paranoid checks in AGP code making sure we never do idle maps on gen2 parts. That was not duplicated as the simple PCI id check should do the right thing. v2: use IS_GEN5 && IS_MOBILE check instead. For now, this is the same as IS_IRONLAKE_M but is more future proof. The workaround docs hint that more than one platform may be effected, but we've never seen such a platform in the wild. (Rodrigo, Daniel) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> (v1) Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c27
1 files changed, 0 insertions, 27 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index c8d9dcb15db0..12c31026eb56 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -840,9 +840,6 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
840{ 840{
841 int ret = -EINVAL; 841 int ret = -EINVAL;
842 842
843 if (intel_private.base.do_idle_maps)
844 return -ENODEV;
845
846 if (intel_private.clear_fake_agp) { 843 if (intel_private.clear_fake_agp) {
847 int start = intel_private.base.stolen_size / PAGE_SIZE; 844 int start = intel_private.base.stolen_size / PAGE_SIZE;
848 int end = intel_private.base.gtt_mappable_entries; 845 int end = intel_private.base.gtt_mappable_entries;
@@ -907,9 +904,6 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem,
907 if (mem->page_count == 0) 904 if (mem->page_count == 0)
908 return 0; 905 return 0;
909 906
910 if (intel_private.base.do_idle_maps)
911 return -ENODEV;
912
913 intel_gtt_clear_range(pg_start, mem->page_count); 907 intel_gtt_clear_range(pg_start, mem->page_count);
914 908
915 if (intel_private.base.needs_dmar) { 909 if (intel_private.base.needs_dmar) {
@@ -1069,24 +1063,6 @@ static void i965_write_entry(dma_addr_t addr,
1069 writel(addr | pte_flags, intel_private.gtt + entry); 1063 writel(addr | pte_flags, intel_private.gtt + entry);
1070} 1064}
1071 1065
1072/* Certain Gen5 chipsets require require idling the GPU before
1073 * unmapping anything from the GTT when VT-d is enabled.
1074 */
1075static inline int needs_idle_maps(void)
1076{
1077#ifdef CONFIG_INTEL_IOMMU
1078 const unsigned short gpu_devid = intel_private.pcidev->device;
1079
1080 /* Query intel_iommu to see if we need the workaround. Presumably that
1081 * was loaded first.
1082 */
1083 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1084 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1085 intel_iommu_gfx_mapped)
1086 return 1;
1087#endif
1088 return 0;
1089}
1090 1066
1091static int i9xx_setup(void) 1067static int i9xx_setup(void)
1092{ 1068{
@@ -1115,9 +1091,6 @@ static int i9xx_setup(void)
1115 break; 1091 break;
1116 } 1092 }
1117 1093
1118 if (needs_idle_maps())
1119 intel_private.base.do_idle_maps = 1;
1120
1121 intel_i9xx_setup_flush(); 1094 intel_i9xx_setup_flush();
1122 1095
1123 return 0; 1096 return 0;