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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-09-11 17:55:20 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:37:05 -0400
commit90cb149e1a85f8296daa1989c055db18fbf4ea88 (patch)
treea8e4b4c7485baa9bb95dc29e6cd1adc2106dcd4a /drivers/char/agp/intel-gtt.c
parent450f2b3d51025a1749b694ee13f0e4e23ed58750 (diff)
intel-gtt: generic (insert|remove)_entries for sandybridge
Like before, but now with the added bonus of being able to kill quite a bit of no-longer userful code (the old dmar support stuff). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c144
1 files changed, 8 insertions, 136 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index dc06b23c1431..44722c6790b2 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -177,61 +177,6 @@ static void intel_agp_unmap_memory(struct agp_memory *mem)
177 intel_agp_free_sglist(mem); 177 intel_agp_free_sglist(mem);
178} 178}
179 179
180#if USE_PCI_DMA_API
181static void intel_agp_insert_sg_entries(struct agp_memory *mem,
182 off_t pg_start, int mask_type)
183{
184 struct scatterlist *sg;
185 int i, j;
186
187 j = pg_start;
188
189 WARN_ON(!mem->num_sg);
190
191 if (mem->num_sg == mem->page_count) {
192 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
193 writel(agp_bridge->driver->mask_memory(agp_bridge,
194 sg_dma_address(sg), mask_type),
195 intel_private.gtt+j);
196 j++;
197 }
198 } else {
199 /* sg may merge pages, but we have to separate
200 * per-page addr for GTT */
201 unsigned int len, m;
202
203 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
204 len = sg_dma_len(sg) / PAGE_SIZE;
205 for (m = 0; m < len; m++) {
206 writel(agp_bridge->driver->mask_memory(agp_bridge,
207 sg_dma_address(sg) + m * PAGE_SIZE,
208 mask_type),
209 intel_private.gtt+j);
210 j++;
211 }
212 }
213 }
214 readl(intel_private.gtt+j-1);
215}
216
217#else
218
219static void intel_agp_insert_sg_entries(struct agp_memory *mem,
220 off_t pg_start, int mask_type)
221{
222 int i, j;
223
224 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
225 writel(agp_bridge->driver->mask_memory(agp_bridge,
226 page_to_phys(mem->pages[i]), mask_type),
227 intel_private.gtt+j);
228 }
229
230 readl(intel_private.gtt+j-1);
231}
232
233#endif
234
235static int intel_i810_fetch_size(void) 180static int intel_i810_fetch_size(void)
236{ 181{
237 u32 smram_miscc; 182 u32 smram_miscc;
@@ -1266,81 +1211,6 @@ static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1266 writel(1, intel_private.i9xx_flush_page); 1211 writel(1, intel_private.i9xx_flush_page);
1267} 1212}
1268 1213
1269static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1270 int type)
1271{
1272 int num_entries;
1273 void *temp;
1274 int ret = -EINVAL;
1275 int mask_type;
1276
1277 if (mem->page_count == 0)
1278 goto out;
1279
1280 temp = agp_bridge->current_size;
1281 num_entries = A_SIZE_FIX(temp)->num_entries;
1282
1283 if (pg_start < intel_private.base.gtt_stolen_entries) {
1284 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1285 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1286 pg_start, intel_private.base.gtt_stolen_entries);
1287
1288 dev_info(&intel_private.pcidev->dev,
1289 "trying to insert into local/stolen memory\n");
1290 goto out_err;
1291 }
1292
1293 if ((pg_start + mem->page_count) > num_entries)
1294 goto out_err;
1295
1296 /* The i915 can't check the GTT for entries since it's read only;
1297 * depend on the caller to make the correct offset decisions.
1298 */
1299
1300 if (type != mem->type)
1301 goto out_err;
1302
1303 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1304
1305 if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1306 mask_type != AGP_PHYS_MEMORY &&
1307 mask_type != INTEL_AGP_CACHED_MEMORY)
1308 goto out_err;
1309
1310 if (!mem->is_flushed)
1311 global_cache_flush();
1312
1313 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1314
1315 out:
1316 ret = 0;
1317 out_err:
1318 mem->is_flushed = true;
1319 return ret;
1320}
1321
1322static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1323 int type)
1324{
1325 int i;
1326
1327 if (mem->page_count == 0)
1328 return 0;
1329
1330 if (pg_start < intel_private.base.gtt_stolen_entries) {
1331 dev_info(&intel_private.pcidev->dev,
1332 "trying to disable local/stolen memory\n");
1333 return -EINVAL;
1334 }
1335
1336 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1337 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1338
1339 readl(intel_private.gtt+i-1);
1340
1341 return 0;
1342}
1343
1344static void i965_write_entry(dma_addr_t addr, unsigned int entry, 1214static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1345 unsigned int flags) 1215 unsigned int flags)
1346{ 1216{
@@ -1349,6 +1219,11 @@ static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1349 writel(addr | I810_PTE_VALID, intel_private.gtt + entry); 1219 writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
1350} 1220}
1351 1221
1222static bool gen6_check_flags(unsigned int flags)
1223{
1224 return true;
1225}
1226
1352static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 1227static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1353 unsigned int flags) 1228 unsigned int flags)
1354{ 1229{
@@ -1562,8 +1437,8 @@ static const struct agp_bridge_driver intel_gen6_driver = {
1562 .cache_flush = global_cache_flush, 1437 .cache_flush = global_cache_flush,
1563 .create_gatt_table = intel_fake_agp_create_gatt_table, 1438 .create_gatt_table = intel_fake_agp_create_gatt_table,
1564 .free_gatt_table = intel_fake_agp_free_gatt_table, 1439 .free_gatt_table = intel_fake_agp_free_gatt_table,
1565 .insert_memory = intel_i915_insert_entries, 1440 .insert_memory = intel_fake_agp_insert_entries,
1566 .remove_memory = intel_i915_remove_entries, 1441 .remove_memory = intel_fake_agp_remove_entries,
1567 .alloc_by_type = intel_fake_agp_alloc_by_type, 1442 .alloc_by_type = intel_fake_agp_alloc_by_type,
1568 .free_by_type = intel_i810_free_by_type, 1443 .free_by_type = intel_i810_free_by_type,
1569 .agp_alloc_page = agp_generic_alloc_page, 1444 .agp_alloc_page = agp_generic_alloc_page,
@@ -1572,10 +1447,6 @@ static const struct agp_bridge_driver intel_gen6_driver = {
1572 .agp_destroy_pages = agp_generic_destroy_pages, 1447 .agp_destroy_pages = agp_generic_destroy_pages,
1573 .agp_type_to_mask_type = intel_gen6_type_to_mask_type, 1448 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1574 .chipset_flush = intel_i915_chipset_flush, 1449 .chipset_flush = intel_i915_chipset_flush,
1575#if USE_PCI_DMA_API
1576 .agp_map_memory = intel_agp_map_memory,
1577 .agp_unmap_memory = intel_agp_unmap_memory,
1578#endif
1579}; 1450};
1580 1451
1581static const struct agp_bridge_driver intel_g33_driver = { 1452static const struct agp_bridge_driver intel_g33_driver = {
@@ -1654,6 +1525,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
1654 .gen = 6, 1525 .gen = 6,
1655 .setup = i9xx_setup, 1526 .setup = i9xx_setup,
1656 .write_entry = gen6_write_entry, 1527 .write_entry = gen6_write_entry,
1528 .check_flags = gen6_check_flags,
1657}; 1529};
1658 1530
1659/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1531/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of