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authorBjorn Helgaas <bhelgaas@google.com>2014-01-03 20:28:31 -0500
committerBjorn Helgaas <bhelgaas@google.com>2014-01-07 13:37:06 -0500
commit5ef6d8f49533bb28a90ae9eec177ffd1ade54267 (patch)
treeda7d02e5d8964935b520970bb478d5b217a5d80a /drivers/char/agp/intel-gtt.c
parent545b0a746b79f54a45cd3b595dce67abbf35233f (diff)
agp/intel: Use pci_bus_address() to get MMADR bus address
Per the Intel 915G/915GV/... Chipset spec (document number 301467-005), MMADR is a standard PCI BAR. The PCI core reads MMADR at enumeration-time. Use pci_bus_address() instead of reading it again in the driver. This works correctly for both 32-bit and 64-bit BARs. The spec above only mentions 32-bit MMADR, but we should still use the standard interface. Also, stop clearing the low 19 bits of the bus address because it's invalid to use addresses outside the region defined by the BAR. The spec claims MMADR is 512KB; if that's the case, those bits will be zero anyway. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 560f66bffebb..58916f32c0f3 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -181,8 +181,7 @@ static int i810_setup(void)
181 return -ENOMEM; 181 return -ENOMEM;
182 intel_private.i81x_gtt_table = gtt_table; 182 intel_private.i81x_gtt_table = gtt_table;
183 183
184 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr); 184 reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR);
185 reg_addr &= 0xfff80000;
186 185
187 intel_private.registers = ioremap(reg_addr, KB(64)); 186 intel_private.registers = ioremap(reg_addr, KB(64));
188 if (!intel_private.registers) 187 if (!intel_private.registers)
@@ -785,8 +784,7 @@ static int i830_setup(void)
785{ 784{
786 u32 reg_addr; 785 u32 reg_addr;
787 786
788 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr); 787 reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR);
789 reg_addr &= 0xfff80000;
790 788
791 intel_private.registers = ioremap(reg_addr, KB(64)); 789 intel_private.registers = ioremap(reg_addr, KB(64));
792 if (!intel_private.registers) 790 if (!intel_private.registers)
@@ -1107,9 +1105,7 @@ static int i9xx_setup(void)
1107 u32 reg_addr, gtt_addr; 1105 u32 reg_addr, gtt_addr;
1108 int size = KB(512); 1106 int size = KB(512);
1109 1107
1110 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr); 1108 reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR);
1111
1112 reg_addr &= 0xfff80000;
1113 1109
1114 intel_private.registers = ioremap(reg_addr, size); 1110 intel_private.registers = ioremap(reg_addr, size);
1115 if (!intel_private.registers) 1111 if (!intel_private.registers)