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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-09-07 16:41:04 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:35:18 -0400
commit351bb278d2fd2df93526c15f37500070347328b4 (patch)
tree9e351eac4867c206f273e121ab061b0d62ec931f /drivers/char/agp/intel-gtt.c
parent0e87d2b06cb4651c874d0b208d31c73addbd638b (diff)
intel-gtt: introduce pte write function for i8xx/i915/i945
And put it to use in the gtt configuration code that writes the scratch page addr in all gtt ptes. This makes intel_i830_configure generic, hence rename it to intel_fake_agp_configure. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c41
1 files changed, 32 insertions, 9 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index e386a44330b8..4d768e085382 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -90,6 +90,10 @@ struct intel_gtt_driver {
90 unsigned int is_ironlake : 1; 90 unsigned int is_ironlake : 1;
91 /* Chipset specific GTT setup */ 91 /* Chipset specific GTT setup */
92 int (*setup)(void); 92 int (*setup)(void);
93 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
94 /* Flags is a more or less chipset specific opaque value.
95 * For chipsets that need to support old ums (non-gem) code, this
96 * needs to be identical to the various supported agp memory types! */
93}; 97};
94 98
95static struct _intel_private { 99static struct _intel_private {
@@ -954,6 +958,23 @@ static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
954 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 958 printk(KERN_ERR "Timed out waiting for cache flush.\n");
955} 959}
956 960
961static void i830_write_entry(dma_addr_t addr, unsigned int entry,
962 unsigned int flags)
963{
964 u32 pte_flags = I810_PTE_VALID;
965
966 switch (flags) {
967 case AGP_DCACHE_MEMORY:
968 pte_flags |= I810_PTE_LOCAL;
969 break;
970 case AGP_USER_CACHED_MEMORY:
971 pte_flags |= I830_PTE_SYSTEM_CACHED;
972 break;
973 }
974
975 writel(addr | pte_flags, intel_private.gtt + entry);
976}
977
957static void intel_enable_gtt(void) 978static void intel_enable_gtt(void)
958{ 979{
959 u32 gma_addr; 980 u32 gma_addr;
@@ -1011,7 +1032,7 @@ static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
1011 return 0; 1032 return 0;
1012} 1033}
1013 1034
1014static int intel_i830_configure(void) 1035static int intel_fake_agp_configure(void)
1015{ 1036{
1016 int i; 1037 int i;
1017 1038
@@ -1019,13 +1040,12 @@ static int intel_i830_configure(void)
1019 1040
1020 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 1041 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1021 1042
1022 if (agp_bridge->driver->needs_scratch_page) { 1043 for (i = intel_private.base.gtt_stolen_entries;
1023 for (i = intel_private.base.gtt_stolen_entries; 1044 i < intel_private.base.gtt_total_entries; i++) {
1024 i < intel_private.base.gtt_total_entries; i++) { 1045 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1025 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1046 i, 0);
1026 }
1027 readl(intel_private.gtt+i-1); /* PCI Posting. */
1028 } 1047 }
1048 readl(intel_private.gtt+i-1); /* PCI Posting. */
1029 1049
1030 global_cache_flush(); 1050 global_cache_flush();
1031 1051
@@ -1417,7 +1437,7 @@ static const struct agp_bridge_driver intel_830_driver = {
1417 .aperture_sizes = intel_fake_agp_sizes, 1437 .aperture_sizes = intel_fake_agp_sizes,
1418 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1438 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1419 .needs_scratch_page = true, 1439 .needs_scratch_page = true,
1420 .configure = intel_i830_configure, 1440 .configure = intel_fake_agp_configure,
1421 .fetch_size = intel_fake_agp_fetch_size, 1441 .fetch_size = intel_fake_agp_fetch_size,
1422 .cleanup = intel_gtt_cleanup, 1442 .cleanup = intel_gtt_cleanup,
1423 .mask_memory = intel_i810_mask_memory, 1443 .mask_memory = intel_i810_mask_memory,
@@ -1444,7 +1464,7 @@ static const struct agp_bridge_driver intel_915_driver = {
1444 .aperture_sizes = intel_fake_agp_sizes, 1464 .aperture_sizes = intel_fake_agp_sizes,
1445 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1465 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1446 .needs_scratch_page = true, 1466 .needs_scratch_page = true,
1447 .configure = intel_i9xx_configure, 1467 .configure = intel_fake_agp_configure,
1448 .fetch_size = intel_fake_agp_fetch_size, 1468 .fetch_size = intel_fake_agp_fetch_size,
1449 .cleanup = intel_gtt_cleanup, 1469 .cleanup = intel_gtt_cleanup,
1450 .mask_memory = intel_i810_mask_memory, 1470 .mask_memory = intel_i810_mask_memory,
@@ -1573,10 +1593,13 @@ static const struct agp_bridge_driver intel_g33_driver = {
1573static const struct intel_gtt_driver i8xx_gtt_driver = { 1593static const struct intel_gtt_driver i8xx_gtt_driver = {
1574 .gen = 2, 1594 .gen = 2,
1575 .setup = i830_setup, 1595 .setup = i830_setup,
1596 .write_entry = i830_write_entry,
1576}; 1597};
1577static const struct intel_gtt_driver i915_gtt_driver = { 1598static const struct intel_gtt_driver i915_gtt_driver = {
1578 .gen = 3, 1599 .gen = 3,
1579 .setup = i9xx_setup, 1600 .setup = i9xx_setup,
1601 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1602 .write_entry = i830_write_entry,
1580}; 1603};
1581static const struct intel_gtt_driver g33_gtt_driver = { 1604static const struct intel_gtt_driver g33_gtt_driver = {
1582 .gen = 3, 1605 .gen = 3,