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authorNishanth Menon <nm@ti.com>2014-04-11 12:38:10 -0400
committerNishanth Menon <nm@ti.com>2014-05-05 15:33:19 -0400
commit3ae9af7c90f8113365cf2600797115ee35e42d0d (patch)
treeeac31e2ce235c84e8da9dae4e3f119553562f331 /drivers/bus
parentf0a6e654d8db2dfa3eb8b99380ad449d5e092c33 (diff)
bus: omap_l3_noc: convert target information into a structure
Currently the target instance information is organized indexed by bit field offset into multiple arrays. 1. We currently have offsets specific to each target associated with each clock domains are in seperate arrays: l3_targ_inst_clk1 l3_targ_inst_clk2 l3_targ_inst_clk3 2. Then they are organized per master index in l3_targ. 3. We have names in l3_targ_inst_name as an array to array of strings corresponding to the above with offsets. Simplify the same by defining a structure for information containing both target offset and name. this is then stored in arrays per domain and organized into an array indexed off domain. The array is still indexed based on bit field offset. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'drivers/bus')
-rw-r--r--drivers/bus/omap_l3_noc.c9
-rw-r--r--drivers/bus/omap_l3_noc.h129
2 files changed, 54 insertions, 84 deletions
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index f7d3bf4f7284..343f002a06f7 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -57,6 +57,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
57 void __iomem *base, *l3_targ_base; 57 void __iomem *base, *l3_targ_base;
58 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr; 58 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
59 char *target_name, *master_name = "UN IDENTIFIED"; 59 char *target_name, *master_name = "UN IDENTIFIED";
60 struct l3_target_data *l3_targ_inst;
60 61
61 /* Get the Type of interrupt */ 62 /* Get the Type of interrupt */
62 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 63 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -74,9 +75,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
74 if (err_reg) { 75 if (err_reg) {
75 /* Identify the source from control status register */ 76 /* Identify the source from control status register */
76 err_src = __ffs(err_reg); 77 err_src = __ffs(err_reg);
78 l3_targ_inst = &l3_targ[i][err_src];
79 target_name = l3_targ_inst->name;
80 l3_targ_base = base + l3_targ_inst->offset;
77 81
78 /* Read the stderrlog_main_source from clk domain */ 82 /* Read the stderrlog_main_source from clk domain */
79 l3_targ_base = base + l3_targ[i][err_src];
80 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN; 83 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
81 l3_targ_slvofslsb = l3_targ_base + 84 l3_targ_slvofslsb = l3_targ_base +
82 L3_TARG_STDERRLOG_SLVOFSLSB; 85 L3_TARG_STDERRLOG_SLVOFSLSB;
@@ -88,8 +91,6 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
88 91
89 switch (std_err_main & CUSTOM_ERROR) { 92 switch (std_err_main & CUSTOM_ERROR) {
90 case STANDARD_ERROR: 93 case STANDARD_ERROR:
91 target_name =
92 l3_targ_inst_name[i][err_src];
93 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n", 94 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
94 target_name, 95 target_name,
95 readl_relaxed(l3_targ_slvofslsb)); 96 readl_relaxed(l3_targ_slvofslsb));
@@ -99,8 +100,6 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
99 break; 100 break;
100 101
101 case CUSTOM_ERROR: 102 case CUSTOM_ERROR:
102 target_name =
103 l3_targ_inst_name[i][err_src];
104 for (k = 0; k < NUM_OF_L3_MASTERS; k++) { 103 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
105 if (masterid == l3_masters[k].id) 104 if (masterid == l3_masters[k].id)
106 master_name = 105 master_name =
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index 059c707fdc84..ae2878464efa 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -43,51 +43,62 @@ struct l3_masters_data {
43 char *name; 43 char *name;
44}; 44};
45 45
46/**
47 * struct l3_target_data - L3 Target information
48 * @offset: Offset from base for L3 Target
49 * @name: Target name
50 *
51 * Target information is organized indexed by bit field definitions.
52 */
53struct l3_target_data {
54 u32 offset;
55 char *name;
56};
57
46static u32 l3_flagmux[L3_MODULES] = { 58static u32 l3_flagmux[L3_MODULES] = {
47 0x500, 59 0x500,
48 0x1000, 60 0x1000,
49 0X0200 61 0X0200
50}; 62};
51 63
52/* L3 Target standard Error register offsets */ 64static struct l3_target_data l3_target_inst_data_clk1[] = {
53static u32 l3_targ_inst_clk1[] = { 65 {0x100, "DMM1",},
54 0x100, /* DMM1 */ 66 {0x200, "DMM2",},
55 0x200, /* DMM2 */ 67 {0x300, "ABE",},
56 0x300, /* ABE */ 68 {0x400, "L4CFG",},
57 0x400, /* L4CFG */ 69 {0x600, "CLK2PWRDISC",},
58 0x600, /* CLK2 PWR DISC */ 70 {0x0, "HOSTCLK1",},
59 0x0, /* Host CLK1 */ 71 {0x900, "L4WAKEUP",},
60 0x900 /* L4 Wakeup */
61}; 72};
62 73
63static u32 l3_targ_inst_clk2[] = { 74static struct l3_target_data l3_target_inst_data_clk2[] = {
64 0x500, /* CORTEX M3 */ 75 {0x500, "CORTEXM3",},
65 0x300, /* DSS */ 76 {0x300, "DSS",},
66 0x100, /* GPMC */ 77 {0x100, "GPMC",},
67 0x400, /* ISS */ 78 {0x400, "ISS",},
68 0x700, /* IVAHD */ 79 {0x700, "IVAHD",},
69 0xD00, /* missing in TRM corresponds to AES1*/ 80 {0xD00, "AES1",},
70 0x900, /* L4 PER0*/ 81 {0x900, "L4PER0",},
71 0x200, /* OCMRAM */ 82 {0x200, "OCMRAM",},
72 0x100, /* missing in TRM corresponds to GPMC sERROR*/ 83 {0x100, "GPMCsERROR",},
73 0x600, /* SGX */ 84 {0x600, "SGX",},
74 0x800, /* SL2 */ 85 {0x800, "SL2",},
75 0x1600, /* C2C */ 86 {0x1600, "C2C",},
76 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/ 87 {0x1100, "PWRDISCCLK1",},
77 0xF00, /* missing in TRM corrsponds to SHA1*/ 88 {0xF00, "SHA1",},
78 0xE00, /* missing in TRM corresponds to AES2*/ 89 {0xE00, "AES2",},
79 0xC00, /* L4 PER3 */ 90 {0xC00, "L4PER3",},
80 0xA00, /* L4 PER1*/ 91 {0xA00, "L4PER1",},
81 0xB00, /* L4 PER2*/ 92 {0xB00, "L4PER2",},
82 0x0, /* HOST CLK2 */ 93 {0x0, "HOSTCLK2",},
83 0x1800, /* CAL */ 94 {0x1800, "CAL",},
84 0x1700 /* LLI */ 95 {0x1700, "LLI",},
85}; 96};
86 97
87static u32 l3_targ_inst_clk3[] = { 98static struct l3_target_data l3_target_inst_data_clk3[] = {
88 0x0100 /* EMUSS */, 99 {0x0100, "EMUSS",},
89 0x0300, /* DEBUGSS_CT_TBR */ 100 {0x0300, "DEBUG SOURCE",},
90 0x0 /* HOST CLK3 */ 101 {0x0, "HOST CLK3",},
91}; 102};
92 103
93static struct l3_masters_data l3_masters[] = { 104static struct l3_masters_data l3_masters[] = {
@@ -118,50 +129,10 @@ static struct l3_masters_data l3_masters[] = {
118 { 0xC8, "USBHOSTFS"} 129 { 0xC8, "USBHOSTFS"}
119}; 130};
120 131
121static char *l3_targ_inst_name[L3_MODULES][21] = { 132static struct l3_target_data *l3_targ[L3_MODULES] = {
122 { 133 l3_target_inst_data_clk1,
123 "DMM1", 134 l3_target_inst_data_clk2,
124 "DMM2", 135 l3_target_inst_data_clk3,
125 "ABE",
126 "L4CFG",
127 "CLK2 PWR DISC",
128 "HOST CLK1",
129 "L4 WAKEUP"
130 },
131 {
132 "CORTEX M3" ,
133 "DSS ",
134 "GPMC ",
135 "ISS ",
136 "IVAHD ",
137 "AES1",
138 "L4 PER0",
139 "OCMRAM ",
140 "GPMC sERROR",
141 "SGX ",
142 "SL2 ",
143 "C2C ",
144 "PWR DISC CLK1",
145 "SHA1",
146 "AES2",
147 "L4 PER3",
148 "L4 PER1",
149 "L4 PER2",
150 "HOST CLK2",
151 "CAL",
152 "LLI"
153 },
154 {
155 "EMUSS",
156 "DEBUG SOURCE",
157 "HOST CLK3"
158 },
159};
160
161static u32 *l3_targ[L3_MODULES] = {
162 l3_targ_inst_clk1,
163 l3_targ_inst_clk2,
164 l3_targ_inst_clk3,
165}; 136};
166 137
167struct omap_l3 { 138struct omap_l3 {