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authorNathan Hintz <nlhintz@hotmail.com>2013-01-11 01:24:03 -0500
committerJohn W. Linville <linville@tuxdriver.com>2013-01-11 14:50:00 -0500
commit990debe2ca8379863709721926550a55f47f3880 (patch)
tree99bd665aaec5f0ff39b529ab1036954385e78496 /drivers/bcma
parenteab6d7921d5704128c941d7cc647dacd4d50697c (diff)
bcma: update pci configuration for bcm4706/bcm4716
Update the PCI configuration for BCM4706 and BCM4716 per the 2011 Broadcom SDK. Signed-off-by: Nathan Hintz <nlhintz@hotmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/bcma')
-rw-r--r--drivers/bcma/driver_pci_host.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c
index ef9f0938da77..37d1777dcd47 100644
--- a/drivers/bcma/driver_pci_host.c
+++ b/drivers/bcma/driver_pci_host.c
@@ -427,7 +427,7 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
427 /* Reset RC */ 427 /* Reset RC */
428 usleep_range(3000, 5000); 428 usleep_range(3000, 5000);
429 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); 429 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
430 usleep_range(1000, 2000); 430 msleep(50);
431 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | 431 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
432 BCMA_CORE_PCI_CTL_RST_OE); 432 BCMA_CORE_PCI_CTL_RST_OE);
433 433
@@ -489,6 +489,17 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
489 489
490 bcma_core_pci_enable_crs(pc); 490 bcma_core_pci_enable_crs(pc);
491 491
492 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
493 bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
494 u16 val16;
495 bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
496 &val16, sizeof(val16));
497 val16 |= (2 << 5); /* Max payload size of 512 */
498 val16 |= (2 << 12); /* MRRS 512 */
499 bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
500 &val16, sizeof(val16));
501 }
502
492 /* Enable PCI bridge BAR0 memory & master access */ 503 /* Enable PCI bridge BAR0 memory & master access */
493 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 504 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
494 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); 505 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));